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2be2c6cc | 1 | /* |
73225245 GI |
2 | * (C) Copyright 2008-2010 |
3 | * GraÅžvydas Ignotas <notasas@gmail.com> | |
2be2c6cc DB |
4 | * |
5 | * Configuration settings for the OMAP3 Pandora. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
2be2c6cc DB |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
2be2c6cc DB |
12 | |
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
2be2c6cc DB |
16 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
17 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
2be2c6cc | 18 | #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ |
308252ad | 19 | #define CONFIG_OMAP_GPIO |
806d2792 | 20 | #define CONFIG_OMAP_COMMON |
2be2c6cc | 21 | |
cae377b5 VH |
22 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
23 | ||
2be2c6cc DB |
24 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
25 | #include <asm/arch/omap3.h> | |
26 | ||
6a6b62e3 SP |
27 | /* |
28 | * Display CPU and Board information | |
29 | */ | |
30 | #define CONFIG_DISPLAY_CPUINFO 1 | |
31 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
32 | ||
2be2c6cc DB |
33 | /* Clock Defines */ |
34 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
35 | #define V_SCLK (V_OSCK >> 1) | |
36 | ||
2be2c6cc DB |
37 | #define CONFIG_MISC_INIT_R |
38 | ||
39 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
40 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
41 | #define CONFIG_INITRD_TAG 1 | |
42 | #define CONFIG_REVISION_TAG 1 | |
43 | ||
2fa8ca98 GL |
44 | #define CONFIG_OF_LIBFDT 1 |
45 | ||
2be2c6cc DB |
46 | /* |
47 | * Size of malloc() pool | |
48 | */ | |
9c44ddcc | 49 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
73225245 | 50 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) |
2be2c6cc DB |
51 | |
52 | /* | |
53 | * Hardware drivers | |
54 | */ | |
55 | ||
73225245 GI |
56 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
57 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
58 | ||
59 | /* USB */ | |
60 | #define CONFIG_MUSB_UDC 1 | |
61 | #define CONFIG_USB_OMAP3 1 | |
62 | #define CONFIG_TWL4030_USB 1 | |
63 | ||
64 | /* USB device configuration */ | |
65 | #define CONFIG_USB_DEVICE 1 | |
66 | #define CONFIG_USB_TTY 1 | |
67 | ||
2be2c6cc DB |
68 | /* |
69 | * NS16550 Configuration | |
70 | */ | |
71 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
72 | ||
73 | #define CONFIG_SYS_NS16550 | |
74 | #define CONFIG_SYS_NS16550_SERIAL | |
75 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
76 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
77 | ||
78 | /* | |
79 | * select serial console configuration | |
80 | */ | |
81 | #define CONFIG_CONS_INDEX 3 | |
82 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
83 | #define CONFIG_SERIAL3 3 | |
84 | ||
85 | /* allow to overwrite serial and ethaddr */ | |
86 | #define CONFIG_ENV_OVERWRITE | |
87 | #define CONFIG_BAUDRATE 115200 | |
88 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ | |
89 | 115200} | |
86c5c544 | 90 | #define CONFIG_GENERIC_MMC 1 |
2be2c6cc | 91 | #define CONFIG_MMC 1 |
86c5c544 | 92 | #define CONFIG_OMAP_HSMMC 1 |
2be2c6cc DB |
93 | #define CONFIG_DOS_PARTITION 1 |
94 | ||
95 | /* commands to include */ | |
96 | #include <config_cmd_default.h> | |
97 | ||
98 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
99 | #define CONFIG_CMD_FAT /* FAT support */ | |
2be2c6cc DB |
100 | |
101 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
102 | #define CONFIG_CMD_MMC /* MMC support */ | |
103 | #define CONFIG_CMD_NAND /* NAND support */ | |
73225245 | 104 | #define CONFIG_CMD_CACHE /* Cache control */ |
2be2c6cc DB |
105 | |
106 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
107 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
108 | #undef CONFIG_CMD_IMI /* iminfo */ | |
109 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
110 | #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
111 | #undef CONFIG_CMD_NFS /* NFS support */ | |
112 | ||
113 | #define CONFIG_SYS_NO_FLASH | |
6789e84e HS |
114 | #define CONFIG_SYS_I2C |
115 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
116 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
117 | #define CONFIG_SYS_I2C_OMAP34XX | |
2be2c6cc | 118 | |
2c155130 TR |
119 | /* |
120 | * TWL4030 | |
121 | */ | |
122 | #define CONFIG_TWL4030_POWER 1 | |
123 | #define CONFIG_TWL4030_LED 1 | |
124 | ||
2be2c6cc DB |
125 | /* |
126 | * Board NAND Info. | |
127 | */ | |
128 | #define CONFIG_NAND_OMAP_GPMC | |
129 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
130 | /* to access nand */ | |
131 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
132 | /* to access nand */ | |
133 | /* at CS0 */ | |
134 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
135 | ||
136 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
137 | /* devices */ | |
73225245 GI |
138 | |
139 | #ifdef CONFIG_CMD_NAND | |
140 | #define CONFIG_CMD_MTDPARTS | |
141 | #define CONFIG_MTD_PARTITIONS | |
142 | #define CONFIG_MTD_DEVICE | |
143 | #define CONFIG_CMD_UBI | |
144 | #define CONFIG_CMD_UBIFS | |
145 | #define CONFIG_RBTREE | |
146 | #define CONFIG_LZO | |
147 | ||
148 | #define MTDIDS_DEFAULT "nand0=nand" | |
149 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\ | |
150 | "1920k(uboot),128k(uboot-env),"\ | |
151 | "10m(boot),-(rootfs)" | |
152 | #else | |
153 | #define MTDPARTS_DEFAULT | |
154 | #endif | |
2be2c6cc DB |
155 | |
156 | /* Environment information */ | |
157 | #define CONFIG_BOOTDELAY 1 | |
158 | ||
159 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
73225245 | 160 | "usbtty=cdc_acm\0" \ |
2be2c6cc | 161 | "loadaddr=0x82000000\0" \ |
73225245 | 162 | "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ |
9baa37b1 | 163 | "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ |
73225245 | 164 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
2be2c6cc DB |
165 | |
166 | #define CONFIG_BOOTCOMMAND \ | |
86c5c544 | 167 | "if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \ |
73225245 GI |
168 | "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \ |
169 | "source ${loadaddr}; " \ | |
170 | "fi; " \ | |
949a7710 JH |
171 | "ubi part boot && ubifsmount ubi:boot && " \ |
172 | "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" | |
2be2c6cc DB |
173 | |
174 | #define CONFIG_AUTO_COMPLETE 1 | |
175 | /* | |
176 | * Miscellaneous configurable options | |
177 | */ | |
2be2c6cc DB |
178 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
179 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
1270ec13 | 180 | #define CONFIG_SYS_PROMPT "Pandora # " |
f62b1257 | 181 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
2be2c6cc DB |
182 | /* Print Buffer Size */ |
183 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
184 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
185 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
186 | /* args */ | |
187 | /* Boot Argument Buffer Size */ | |
188 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
189 | /* memtest works on */ | |
190 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
191 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
192 | 0x01F00000) /* 31MB */ | |
193 | ||
2be2c6cc DB |
194 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ |
195 | /* address */ | |
196 | ||
197 | /* | |
d3a513c2 MP |
198 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
199 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
200 | * This rate is divided by a local divisor. | |
2be2c6cc | 201 | */ |
d3a513c2 MP |
202 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 |
203 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
2be2c6cc | 204 | |
2be2c6cc DB |
205 | /*----------------------------------------------------------------------- |
206 | * Physical Memory Map | |
207 | */ | |
208 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
209 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
2be2c6cc DB |
210 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
211 | ||
23df4f69 GI |
212 | #define CONFIG_SYS_TEXT_BASE 0x80008000 |
213 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
214 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
215 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
216 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
217 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
218 | GENERATED_GBL_DATA_SIZE) | |
219 | ||
2be2c6cc DB |
220 | /*----------------------------------------------------------------------- |
221 | * FLASH and environment organization | |
222 | */ | |
223 | ||
224 | /* **** PISMO SUPPORT *** */ | |
225 | ||
226 | /* Configure the PISMO */ | |
227 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
228 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
229 | ||
9c44ddcc | 230 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
2be2c6cc | 231 | |
6cbec7b3 LC |
232 | #if defined(CONFIG_CMD_NAND) |
233 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
234 | #endif | |
2be2c6cc DB |
235 | |
236 | /* Monitor at start of flash */ | |
237 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
2be2c6cc DB |
238 | |
239 | #define CONFIG_ENV_IS_IN_NAND 1 | |
73225245 | 240 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
2be2c6cc | 241 | |
6cbec7b3 LC |
242 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
243 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
2be2c6cc DB |
244 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
245 | ||
8e40852f A |
246 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
247 | ||
2be2c6cc | 248 | #endif /* __CONFIG_H */ |