[people/ms/u-boot.git] / include / configs / omap3_pandora.h

/*
 * (C) Copyright 2008-2010
 * Gražvydas Ignotas <notasas@gmail.com>
 *
 * Configuration settings for the OMAP3 Pandora.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)

/*
 * Hardware drivers
 */

#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
#define CONFIG_SYS_DEVICE_NULLDEV	1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_CACHE	/* Cache control		*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand */
							/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
						/* devices */

#ifdef CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO

#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(xloader),"\
					"1920k(uboot),128k(uboot-env),"\
					"10m(boot),-(rootfs)"
#else
#define MTDPARTS_DEFAULT
#endif

/* Environment information */
#define CONFIG_BOOTDELAY		1

#define CONFIG_EXTRA_ENV_SETTINGS \
	"usbtty=cdc_acm\0" \
	"loadaddr=0x82000000\0" \
	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
			"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
		"source ${loadaddr}; " \
	"fi; " \
	"ubi part boot && ubifsmount ubi:boot && " \
		"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"Pandora # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_CACHELINE_SIZE	64

#endif				/* __CONFIG_H */
Commit	Line	Data
2be2c6cc	1	/*
73225245 GI	2	* (C) Copyright 2008-2010
73225245 GI	3	* Gražvydas Ignotas <notasas@gmail.com>
2be2c6cc DB	4	*
	5	* Configuration settings for the OMAP3 Pandora.
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
2be2c6cc DB	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
2be2c6cc DB	12
	13	/*
	14	* High Level Configuration Options
	15	*/
2be2c6cc DB	16	#define CONFIG_OMAP 1 /* in a TI OMAP core */
2be2c6cc DB	17	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
2be2c6cc	18	#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
308252ad	19	#define CONFIG_OMAP_GPIO
806d2792	20	#define CONFIG_OMAP_COMMON
2be2c6cc	21
cae377b5 VH	22	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	23
2be2c6cc DB	24	#include <asm/arch/cpu.h> /* get chip and board defs */
	25	#include <asm/arch/omap3.h>
	26
6a6b62e3 SP	27	/*
	28	* Display CPU and Board information
	29	*/
	30	#define CONFIG_DISPLAY_CPUINFO 1
	31	#define CONFIG_DISPLAY_BOARDINFO 1
	32
2be2c6cc DB	33	/* Clock Defines */
	34	#define V_OSCK 26000000 /* Clock output from T2 */
	35	#define V_SCLK (V_OSCK >> 1)
	36
2be2c6cc DB	37	#define CONFIG_MISC_INIT_R
	38
	39	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	40	#define CONFIG_SETUP_MEMORY_TAGS 1
	41	#define CONFIG_INITRD_TAG 1
	42	#define CONFIG_REVISION_TAG 1
	43
2fa8ca98 GL	44	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	45
2be2c6cc DB	46	/*
	47	* Size of malloc() pool
	48	*/
9c44ddcc	49	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
73225245	50	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
2be2c6cc DB	51
	52	/*
	53	* Hardware drivers
	54	*/
	55
73225245 GI	56	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	57	#define CONFIG_SYS_DEVICE_NULLDEV 1
	58
	59	/* USB */
	60	#define CONFIG_MUSB_UDC 1
	61	#define CONFIG_USB_OMAP3 1
	62	#define CONFIG_TWL4030_USB 1
	63
	64	/* USB device configuration */
	65	#define CONFIG_USB_DEVICE 1
	66	#define CONFIG_USB_TTY 1
	67
2be2c6cc DB	68	/*
	69	* NS16550 Configuration
	70	*/
	71	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	72
	73	#define CONFIG_SYS_NS16550
	74	#define CONFIG_SYS_NS16550_SERIAL
	75	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	76	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	77
	78	/*
	79	* select serial console configuration
	80	*/
	81	#define CONFIG_CONS_INDEX 3
	82	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	83	#define CONFIG_SERIAL3 3
	84
	85	/* allow to overwrite serial and ethaddr */
	86	#define CONFIG_ENV_OVERWRITE
	87	#define CONFIG_BAUDRATE 115200
	88	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
	89	115200}
86c5c544	90	#define CONFIG_GENERIC_MMC 1
2be2c6cc	91	#define CONFIG_MMC 1
86c5c544	92	#define CONFIG_OMAP_HSMMC 1
2be2c6cc DB	93	#define CONFIG_DOS_PARTITION 1
	94
	95	/* commands to include */
	96	#include <config_cmd_default.h>
	97
	98	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	99	#define CONFIG_CMD_FAT /* FAT support */
2be2c6cc DB	100
	101	#define CONFIG_CMD_I2C /* I2C serial bus support */
	102	#define CONFIG_CMD_MMC /* MMC support */
	103	#define CONFIG_CMD_NAND /* NAND support */
73225245	104	#define CONFIG_CMD_CACHE /* Cache control */
2be2c6cc DB	105
	106	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	107	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	108	#undef CONFIG_CMD_IMI /* iminfo */
	109	#undef CONFIG_CMD_IMLS /* List all found images */
	110	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	111	#undef CONFIG_CMD_NFS /* NFS support */
	112
	113	#define CONFIG_SYS_NO_FLASH
0297ec7e	114	#define CONFIG_HARD_I2C 1
2be2c6cc DB	115	#define CONFIG_SYS_I2C_SPEED 100000
2be2c6cc DB	116	#define CONFIG_SYS_I2C_SLAVE 1
2be2c6cc DB	117	#define CONFIG_DRIVER_OMAP34XX_I2C 1
2be2c6cc DB	118
2c155130 TR	119	/*
	120	* TWL4030
	121	*/
	122	#define CONFIG_TWL4030_POWER 1
	123	#define CONFIG_TWL4030_LED 1
	124
2be2c6cc DB	125	/*
	126	* Board NAND Info.
	127	*/
	128	#define CONFIG_NAND_OMAP_GPMC
	129	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	130	/* to access nand */
	131	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	132	/* to access nand */
	133	/* at CS0 */
	134	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	135
	136	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	137	/* devices */
73225245 GI	138
	139	#ifdef CONFIG_CMD_NAND
	140	#define CONFIG_CMD_MTDPARTS
	141	#define CONFIG_MTD_PARTITIONS
	142	#define CONFIG_MTD_DEVICE
	143	#define CONFIG_CMD_UBI
	144	#define CONFIG_CMD_UBIFS
	145	#define CONFIG_RBTREE
	146	#define CONFIG_LZO
	147
	148	#define MTDIDS_DEFAULT "nand0=nand"
	149	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\
	150	"1920k(uboot),128k(uboot-env),"\
	151	"10m(boot),-(rootfs)"
	152	#else
	153	#define MTDPARTS_DEFAULT
	154	#endif
2be2c6cc DB	155
	156	/* Environment information */
	157	#define CONFIG_BOOTDELAY 1
	158
	159	#define CONFIG_EXTRA_ENV_SETTINGS \
73225245	160	"usbtty=cdc_acm\0" \
2be2c6cc	161	"loadaddr=0x82000000\0" \
73225245	162	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
9baa37b1	163	"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
73225245	164	"mtdparts=" MTDPARTS_DEFAULT "\0" \
2be2c6cc DB	165
2be2c6cc DB	166	#define CONFIG_BOOTCOMMAND \
86c5c544	167	"if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr \|\| " \
73225245 GI	168	"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
	169	"source ${loadaddr}; " \
	170	"fi; " \
949a7710 JH	171	"ubi part boot && ubifsmount ubi:boot && " \
949a7710 JH	172	"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
2be2c6cc DB	173
	174	#define CONFIG_AUTO_COMPLETE 1
	175	/*
	176	* Miscellaneous configurable options
	177	*/
2be2c6cc DB	178	#define CONFIG_SYS_LONGHELP /* undef to save memory */
2be2c6cc DB	179	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
1270ec13	180	#define CONFIG_SYS_PROMPT "Pandora # "
f62b1257	181	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
2be2c6cc DB	182	/* Print Buffer Size */
	183	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	184	sizeof(CONFIG_SYS_PROMPT) + 16)
	185	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	186	/* args */
	187	/* Boot Argument Buffer Size */
	188	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	189	/* memtest works on */
	190	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	191	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	192	0x01F00000) /* 31MB */
	193
2be2c6cc DB	194	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	195	/* address */
	196
	197	/*
d3a513c2 MP	198	* OMAP3 has 12 GP timers, they can be driven by the system clock
	199	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	200	* This rate is divided by a local divisor.
2be2c6cc	201	*/
d3a513c2 MP	202	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	203	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	204	#define CONFIG_SYS_HZ 1000
2be2c6cc	205
2be2c6cc DB	206	/*-----------------------------------------------------------------------
	207	* Physical Memory Map
	208	*/
	209	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	210	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
2be2c6cc DB	211	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
2be2c6cc DB	212
23df4f69 GI	213	#define CONFIG_SYS_TEXT_BASE 0x80008000
	214	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	215	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	216	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	217	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	218	CONFIG_SYS_INIT_RAM_SIZE - \
	219	GENERATED_GBL_DATA_SIZE)
	220
2be2c6cc DB	221	/*-----------------------------------------------------------------------
	222	* FLASH and environment organization
	223	*/
	224
	225	/* ** PISMO SUPPORT * */
	226
	227	/* Configure the PISMO */
	228	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	229	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	230
9c44ddcc	231	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
2be2c6cc	232
6cbec7b3 LC	233	#if defined(CONFIG_CMD_NAND)
	234	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	235	#endif
2be2c6cc DB	236
	237	/* Monitor at start of flash */
	238	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
2be2c6cc DB	239
2be2c6cc DB	240	#define CONFIG_ENV_IS_IN_NAND 1
73225245	241	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
2be2c6cc	242
6cbec7b3 LC	243	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	244	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
2be2c6cc DB	245	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
2be2c6cc DB	246
8e40852f A	247	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	248
2be2c6cc	249	#endif /* __CONFIG_H */