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931a1d2a AA |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the phytec PCM-052 SoM. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include <asm/arch/imx-regs.h> | |
13 | ||
14 | #define CONFIG_VF610 | |
15 | ||
931a1d2a AA |
16 | #define CONFIG_DISPLAY_CPUINFO |
17 | #define CONFIG_DISPLAY_BOARDINFO | |
18 | #define CONFIG_SYS_THUMB_BUILD | |
19 | ||
20 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
21 | ||
22 | /* Enable passing of ATAGs */ | |
23 | #define CONFIG_CMDLINE_TAG | |
24 | ||
25 | /* Size of malloc() pool */ | |
26 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
27 | ||
28 | #define CONFIG_BOARD_EARLY_INIT_F | |
29 | ||
931a1d2a AA |
30 | /* Allow to overwrite serial and ethaddr */ |
31 | #define CONFIG_ENV_OVERWRITE | |
931a1d2a AA |
32 | #define CONFIG_BAUDRATE 115200 |
33 | ||
931a1d2a AA |
34 | /* NAND support */ |
35 | #define CONFIG_CMD_NAND | |
36 | #define CONFIG_CMD_NAND_TRIMFFS | |
37 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
38 | ||
39 | #ifdef CONFIG_CMD_NAND | |
40 | #define CONFIG_USE_ARCH_MEMCPY | |
41 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
42 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
43 | ||
44 | #define CONFIG_JFFS2_NAND | |
45 | ||
46 | /* UBI */ | |
931a1d2a AA |
47 | #define CONFIG_CMD_UBIFS |
48 | #define CONFIG_RBTREE | |
49 | #define CONFIG_LZO | |
50 | ||
51 | /* Dynamic MTD partition support */ | |
52 | #define CONFIG_CMD_MTDPARTS | |
53 | #define CONFIG_MTD_PARTITIONS | |
54 | #define CONFIG_MTD_DEVICE | |
040ef8f5 | 55 | #define MTDIDS_DEFAULT "nand0=NAND" |
931a1d2a AA |
56 | #define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ |
57 | ",384k(bootloader)"\ | |
58 | ",128k(env1)"\ | |
59 | ",128k(env2)"\ | |
040ef8f5 AA |
60 | ",128k(dtb)"\ |
61 | ",6144k(kernel)"\ | |
62 | ",65536k(ramdisk)"\ | |
63 | ",450944k(root)" | |
931a1d2a AA |
64 | #endif |
65 | ||
66 | #define CONFIG_MMC | |
67 | #define CONFIG_FSL_ESDHC | |
68 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
69 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
70 | ||
71 | /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ | |
72 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
73 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
74 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 | |
75 | ||
931a1d2a | 76 | #define CONFIG_GENERIC_MMC |
931a1d2a AA |
77 | #define CONFIG_DOS_PARTITION |
78 | ||
931a1d2a AA |
79 | #define CONFIG_FEC_MXC |
80 | #define CONFIG_MII | |
81 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
82 | #define CONFIG_FEC_XCV_TYPE RMII | |
83 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
84 | #define CONFIG_PHYLIB | |
85 | #define CONFIG_PHY_MICREL | |
86 | ||
87 | /* QSPI Configs*/ | |
931a1d2a AA |
88 | |
89 | #ifdef CONFIG_FSL_QSPI | |
931a1d2a | 90 | #define CONFIG_SPI_FLASH |
931a1d2a AA |
91 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
92 | #define FSL_QSPI_FLASH_NUM 2 | |
93 | #define CONFIG_SYS_FSL_QSPI_LE | |
94 | #endif | |
95 | ||
96 | /* I2C Configs */ | |
931a1d2a AA |
97 | #define CONFIG_SYS_I2C |
98 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
99 | #define CONFIG_SYS_I2C_MXC | |
100 | ||
101 | /* RTC (actually an RV-4162 but M41T62-compatible) */ | |
102 | #define CONFIG_CMD_DATE | |
103 | #define CONFIG_RTC_M41T62 | |
104 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
105 | #define CONFIG_SYS_RTC_BUS_NUM 2 | |
106 | ||
107 | /* EEPROM (24FC256) */ | |
108 | #define CONFIG_CMD_EEPROM | |
109 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
110 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
111 | #define CONFIG_SYS_I2C_EEPROM_BUS 2 | |
112 | ||
931a1d2a AA |
113 | |
114 | #define CONFIG_LOADADDR 0x82000000 | |
115 | ||
116 | /* We boot from the gfxRAM area of the OCRAM. */ | |
117 | #define CONFIG_SYS_TEXT_BASE 0x3f408000 | |
118 | #define CONFIG_BOARD_SIZE_LIMIT 524288 | |
119 | ||
120 | #define CONFIG_BOOTCOMMAND "run bootcmd_sd" | |
040ef8f5 AA |
121 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
122 | "fdt_high=0xffffffff\0" \ | |
123 | "initrd_high=0xffffffff\0" \ | |
124 | "blimg_file=u-boot.imx\0" \ | |
125 | "blsec_addr=0x81000000\0" \ | |
126 | "blimg_addr=0x81000400\0" \ | |
127 | "kernel_file=zImage\0" \ | |
128 | "kernel_addr=0x82000000\0" \ | |
129 | "fdt_file=vf610-pcm052.dtb\0" \ | |
130 | "fdt_addr=0x81000000\0" \ | |
131 | "ram_file=uRamdisk\0" \ | |
132 | "ram_addr=0x83000000\0" \ | |
133 | "filesys=rootfs.ubifs\0" \ | |
134 | "sys_addr=0x81000000\0" \ | |
135 | "tftploc=/path/to/tftp/directory/\0" \ | |
136 | "nfs_root=/path/to/nfs/root\0" \ | |
137 | "tftptimeout=1000\0" \ | |
138 | "tftptimeoutcountmax=1000000\0" \ | |
139 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
140 | "bootargs_base=setenv bootargs rw mem=256M " \ | |
141 | "console=ttyLP1,115200n8\0" \ | |
142 | "bootargs_sd=setenv bootargs ${bootargs} " \ | |
143 | "root=/dev/mmcblk0p2 rootwait\0" \ | |
931a1d2a | 144 | "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ |
040ef8f5 AA |
145 | "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ |
146 | "bootargs_nand=setenv bootargs ${bootargs} " \ | |
147 | "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ | |
148 | "bootargs_ram=setenv bootargs ${bootargs} " \ | |
149 | "root=/dev/ram rw initrd=${ram_addr}\0" \ | |
150 | "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
151 | "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ | |
152 | "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ | |
153 | "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ | |
154 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
155 | "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ | |
156 | "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ | |
157 | "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ | |
158 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
159 | "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ | |
160 | "nand read ${fdt_addr} dtb; " \ | |
161 | "nand read ${kernel_addr} kernel; " \ | |
162 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
163 | "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ | |
164 | "nand read ${fdt_addr} dtb; " \ | |
165 | "nand read ${kernel_addr} kernel; " \ | |
166 | "nand read ${ram_addr} ramdisk; " \ | |
167 | "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ | |
168 | "update_bootloader_from_tftp=mtdparts default; " \ | |
169 | "nand read ${blsec_addr} bootloader; " \ | |
170 | "mw.b ${blimg_addr} 0xff 0x5FC00; " \ | |
171 | "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ | |
172 | "nand erase.part bootloader; " \ | |
173 | "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ | |
174 | "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ | |
175 | "${kernel_file}; " \ | |
176 | "then mtdparts default; " \ | |
177 | "nand erase.part kernel; " \ | |
178 | "nand write ${kernel_addr} kernel ${filesize}; " \ | |
179 | "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ | |
180 | "nand erase.part dtb; " \ | |
181 | "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ | |
182 | "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ | |
183 | "then setenv fdtsize ${filesize}; " \ | |
184 | "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ | |
185 | "mtdparts default; " \ | |
186 | "nand erase.part dtb; " \ | |
187 | "nand write ${fdt_addr} dtb ${fdtsize}; " \ | |
188 | "nand erase.part kernel; " \ | |
189 | "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ | |
190 | "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ | |
191 | "then mtdparts default; " \ | |
192 | "nand erase.part root; " \ | |
193 | "ubi part root; " \ | |
194 | "ubi create rootfs; " \ | |
195 | "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ | |
196 | "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ | |
197 | "then mtdparts default; " \ | |
198 | "nand erase.part ramdisk; " \ | |
199 | "nand write ${ram_addr} ramdisk ${filesize}; fi\0" | |
931a1d2a | 200 | |
931a1d2a AA |
201 | /* Miscellaneous configurable options */ |
202 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
931a1d2a AA |
203 | #define CONFIG_AUTO_COMPLETE |
204 | #define CONFIG_CMDLINE_EDITING | |
205 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
206 | #define CONFIG_SYS_PBSIZE \ | |
207 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
208 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
209 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
210 | ||
931a1d2a AA |
211 | #define CONFIG_SYS_MEMTEST_START 0x80010000 |
212 | #define CONFIG_SYS_MEMTEST_END 0x87C00000 | |
213 | ||
214 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
215 | ||
216 | /* | |
217 | * Stack sizes | |
218 | * The stack sizes are set up in start.S using the settings below | |
219 | */ | |
220 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
221 | ||
222 | /* Physical memory map */ | |
223 | #define CONFIG_NR_DRAM_BANKS 1 | |
224 | #define PHYS_SDRAM (0x80000000) | |
225 | #define PHYS_SDRAM_SIZE (256 * 1024 * 1024) | |
226 | ||
227 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
228 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
229 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
230 | ||
231 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
232 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
233 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
234 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
235 | ||
236 | /* FLASH and environment organization */ | |
237 | #define CONFIG_SYS_NO_FLASH | |
238 | ||
239 | #ifdef CONFIG_ENV_IS_IN_MMC | |
240 | #define CONFIG_ENV_SIZE (8 * 1024) | |
241 | ||
242 | #define CONFIG_ENV_OFFSET (12 * 64 * 1024) | |
243 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
244 | #endif | |
245 | ||
246 | #ifdef CONFIG_ENV_IS_IN_NAND | |
247 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
248 | #define CONFIG_ENV_SIZE (8 * 1024) | |
040ef8f5 | 249 | #define CONFIG_ENV_OFFSET 0xA0000 |
931a1d2a | 250 | #define CONFIG_ENV_SIZE_REDUND (8 * 1024) |
040ef8f5 | 251 | #define CONFIG_ENV_OFFSET_REDUND 0xC0000 |
931a1d2a AA |
252 | #endif |
253 | ||
931a1d2a | 254 | #endif |