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f0a2c7b4 II |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
f0a2c7b4 II |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
7 | * Configuation settings for the RONETIX PM9263 board. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f0a2c7b4 II |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
684a567a AD |
15 | /* |
16 | * SoC must be defined first, before hardware.h is included. | |
17 | * In this case SoC is defined in boards.cfg. | |
18 | */ | |
19 | #include <asm/hardware.h> | |
20 | ||
f0a2c7b4 | 21 | /* ARM asynchronous clock */ |
f0a2c7b4 | 22 | |
01550a2b JCPV |
23 | #define MASTER_PLL_DIV 6 |
24 | #define MASTER_PLL_MUL 65 | |
f0a2c7b4 | 25 | #define MAIN_PLL_DIV 2 /* 2 or 4 */ |
7c966a8b | 26 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
684a567a | 27 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
f0a2c7b4 | 28 | |
684a567a | 29 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" |
f0a2c7b4 II |
30 | #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ |
31 | #define CONFIG_ARCH_CPU_INIT | |
f0a2c7b4 | 32 | |
a3e09cc2 AD |
33 | #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 |
34 | ||
f0a2c7b4 | 35 | /* clocks */ |
01550a2b | 36 | #define CONFIG_SYS_MOR_VAL \ |
20d98c2c | 37 | (AT91_PMC_MOR_MOSCEN | \ |
01550a2b JCPV |
38 | (255 << 8)) /* Main Oscillator Start-up Time */ |
39 | #define CONFIG_SYS_PLLAR_VAL \ | |
20d98c2c AD |
40 | (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ |
41 | AT91_PMC_PLLXR_OUT(3) | \ | |
42 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ | |
01550a2b JCPV |
43 | (2 << 28) | /* PLL Clock Frequency Range */ \ |
44 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) | |
f0a2c7b4 II |
45 | |
46 | #if (MAIN_PLL_DIV == 2) | |
47 | /* PCK/2 = MCK Master Clock from PLLA */ | |
01550a2b | 48 | #define CONFIG_SYS_MCKR1_VAL \ |
20d98c2c AD |
49 | (AT91_PMC_MCKR_CSS_SLOW | \ |
50 | AT91_PMC_MCKR_PRES_1 | \ | |
51 | AT91_PMC_MCKR_MDIV_2) | |
f0a2c7b4 | 52 | /* PCK/2 = MCK Master Clock from PLLA */ |
01550a2b | 53 | #define CONFIG_SYS_MCKR2_VAL \ |
20d98c2c AD |
54 | (AT91_PMC_MCKR_CSS_PLLA | \ |
55 | AT91_PMC_MCKR_PRES_1 | \ | |
56 | AT91_PMC_MCKR_MDIV_2) | |
f0a2c7b4 II |
57 | #else |
58 | /* PCK/4 = MCK Master Clock from PLLA */ | |
01550a2b | 59 | #define CONFIG_SYS_MCKR1_VAL \ |
20d98c2c AD |
60 | (AT91_PMC_MCKR_CSS_SLOW | \ |
61 | AT91_PMC_MCKR_PRES_1 | \ | |
62 | AT91_PMC_MCKR_MDIV_4) | |
f0a2c7b4 | 63 | /* PCK/4 = MCK Master Clock from PLLA */ |
01550a2b | 64 | #define CONFIG_SYS_MCKR2_VAL \ |
20d98c2c AD |
65 | (AT91_PMC_MCKR_CSS_PLLA | \ |
66 | AT91_PMC_MCKR_PRES_1 | \ | |
67 | AT91_PMC_MCKR_MDIV_4) | |
f0a2c7b4 II |
68 | #endif |
69 | /* define PDC[31:16] as DATA[31:16] */ | |
70 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | |
71 | /* no pull-up for D[31:16] */ | |
72 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | |
73 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | |
01550a2b | 74 | #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ |
20d98c2c AD |
75 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
76 | AT91_MATRIX_CSA_EBI_CS1A) | |
f0a2c7b4 II |
77 | |
78 | /* SDRAM */ | |
79 | /* SDRAMC_MR Mode register */ | |
80 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | |
81 | /* SDRAMC_TR - Refresh Timer register */ | |
01550a2b JCPV |
82 | #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA |
83 | /* SDRAMC_CR - Configuration register*/ | |
84 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
85 | (AT91_SDRAMC_NC_9 | \ | |
86 | AT91_SDRAMC_NR_13 | \ | |
87 | AT91_SDRAMC_NB_4 | \ | |
88 | AT91_SDRAMC_CAS_2 | \ | |
89 | AT91_SDRAMC_DBW_32 | \ | |
90 | (2 << 8) | /* tWR - Write Recovery Delay */ \ | |
91 | (7 << 12) | /* tRC - Row Cycle Delay */ \ | |
92 | (2 << 16) | /* tRP - Row Precharge Delay */ \ | |
93 | (2 << 20) | /* tRCD - Row to Column Delay */ \ | |
94 | (5 << 24) | /* tRAS - Active to Precharge Delay */ \ | |
95 | (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ | |
96 | ||
f0a2c7b4 | 97 | /* Memory Device Register -> SDRAM */ |
01550a2b JCPV |
98 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
99 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
f0a2c7b4 | 100 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
01550a2b | 101 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
f0a2c7b4 II |
102 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
103 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
104 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
105 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
106 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
107 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
108 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
109 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
01550a2b | 110 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
f0a2c7b4 | 111 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
01550a2b | 112 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
f0a2c7b4 II |
113 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
114 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
115 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
116 | ||
117 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
01550a2b | 118 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
20d98c2c AD |
119 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
120 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
01550a2b | 121 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
20d98c2c AD |
122 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
123 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
01550a2b | 124 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
20d98c2c | 125 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
01550a2b | 126 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
20d98c2c AD |
127 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
128 | AT91_SMC_MODE_DBW_16 | \ | |
129 | AT91_SMC_MODE_TDF | \ | |
130 | AT91_SMC_MODE_TDF_CYCLE(6)) | |
f0a2c7b4 | 131 | |
01550a2b JCPV |
132 | /* user reset enable */ |
133 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
134 | (AT91_RSTC_KEY | \ | |
20d98c2c AD |
135 | AT91_RSTC_CR_PROCRST | \ |
136 | AT91_RSTC_MR_ERSTL(1) | \ | |
137 | AT91_RSTC_MR_ERSTL(2)) | |
f0a2c7b4 | 138 | |
01550a2b JCPV |
139 | /* Disable Watchdog */ |
140 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
20d98c2c AD |
141 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
142 | AT91_WDT_MR_WDV(0xfff) | \ | |
143 | AT91_WDT_MR_WDDIS | \ | |
144 | AT91_WDT_MR_WDD(0xfff)) | |
f0a2c7b4 II |
145 | |
146 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
147 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
148 | #define CONFIG_INITRD_TAG 1 | |
149 | ||
150 | #undef CONFIG_SKIP_LOWLEVEL_INIT | |
f0a2c7b4 II |
151 | #define CONFIG_USER_LOWLEVEL_INIT 1 |
152 | ||
153 | /* | |
154 | * Hardware drivers | |
155 | */ | |
f0a2c7b4 | 156 | /* LCD */ |
f0a2c7b4 II |
157 | #define LCD_BPP LCD_COLOR8 |
158 | #define CONFIG_LCD_LOGO 1 | |
159 | #undef LCD_TEST_PATTERN | |
160 | #define CONFIG_LCD_INFO 1 | |
161 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
f0a2c7b4 II |
162 | #define CONFIG_ATMEL_LCD 1 |
163 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
f0a2c7b4 II |
164 | |
165 | #define CONFIG_LCD_IN_PSRAM 1 | |
166 | ||
f0a2c7b4 II |
167 | /* |
168 | * BOOTP options | |
169 | */ | |
170 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
171 | #define CONFIG_BOOTP_BOOTPATH 1 | |
172 | #define CONFIG_BOOTP_GATEWAY 1 | |
173 | #define CONFIG_BOOTP_HOSTNAME 1 | |
174 | ||
f0a2c7b4 II |
175 | /* SDRAM */ |
176 | #define CONFIG_NR_DRAM_BANKS 1 | |
177 | #define PHYS_SDRAM 0x20000000 | |
178 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
179 | ||
f0a2c7b4 II |
180 | /* NOR flash, if populated */ |
181 | #define CONFIG_SYS_FLASH_CFI 1 | |
182 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
183 | #define PHYS_FLASH_1 0x10000000 | |
184 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
185 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
186 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
187 | ||
188 | /* NAND flash */ | |
189 | #ifdef CONFIG_CMD_NAND | |
190 | #define CONFIG_NAND_ATMEL | |
f0a2c7b4 II |
191 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
192 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
193 | #define CONFIG_SYS_NAND_DBW_8 1 | |
194 | /* our ALE is AD21 */ | |
195 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
196 | /* our CLE is AD22 */ | |
197 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
ac45bb16 AB |
198 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) |
199 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) | |
2eb99ca8 | 200 | |
f0a2c7b4 II |
201 | #endif |
202 | ||
f0a2c7b4 II |
203 | #define CONFIG_JFFS2_CMDLINE 1 |
204 | #define CONFIG_JFFS2_NAND 1 | |
205 | #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ | |
206 | #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ | |
207 | #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ | |
208 | ||
209 | /* PSRAM */ | |
210 | #define PHYS_PSRAM 0x70000000 | |
211 | #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ | |
20d98c2c AD |
212 | /* Slave EBI1, PSRAM connected */ |
213 | #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ | |
214 | AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ | |
215 | AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ | |
216 | AT91_MATRIX_SCFG_SLOT_CYCLE(255)) | |
f0a2c7b4 II |
217 | |
218 | /* Ethernet */ | |
219 | #define CONFIG_MACB 1 | |
220 | #define CONFIG_RMII 1 | |
f0a2c7b4 II |
221 | #define CONFIG_NET_RETRY_COUNT 20 |
222 | #define CONFIG_RESET_PHY_R 1 | |
223 | ||
224 | /* USB */ | |
225 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 226 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
f0a2c7b4 | 227 | #define CONFIG_USB_OHCI_NEW 1 |
f0a2c7b4 II |
228 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
229 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
230 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | |
231 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
f0a2c7b4 II |
232 | |
233 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | |
234 | ||
235 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
236 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
237 | ||
238 | #define CONFIG_SYS_USE_FLASH 1 | |
239 | #undef CONFIG_SYS_USE_DATAFLASH | |
240 | #undef CONFIG_SYS_USE_NANDFLASH | |
241 | ||
242 | #ifdef CONFIG_SYS_USE_DATAFLASH | |
243 | ||
244 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
f0a2c7b4 | 245 | #define CONFIG_ENV_OFFSET 0x4200 |
f0a2c7b4 | 246 | #define CONFIG_ENV_SIZE 0x4200 |
0dfe3ffe WY |
247 | #define CONFIG_ENV_SECT_SIZE 0x210 |
248 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 | |
249 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ | |
250 | "sf read 0x22000000 0x84000 0x294000; " \ | |
251 | "bootm 0x22000000" | |
f0a2c7b4 II |
252 | |
253 | #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ | |
254 | ||
255 | /* bootstrap + u-boot + env + linux in nandflash */ | |
f0a2c7b4 II |
256 | #define CONFIG_ENV_OFFSET 0x60000 |
257 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
258 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
259 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" | |
f0a2c7b4 II |
260 | |
261 | #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ | |
262 | ||
f0a2c7b4 II |
263 | #define CONFIG_ENV_OFFSET 0x40000 |
264 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
265 | #define CONFIG_ENV_SIZE 0x10000 | |
266 | #define CONFIG_ENV_OVERWRITE 1 | |
267 | ||
268 | /* JFFS Partition offset set */ | |
269 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 | |
270 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
271 | ||
272 | /* 512k reserved for u-boot */ | |
273 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 | |
274 | ||
275 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
8b3637c6 | 276 | #define CONFIG_ROOTPATH "/ronetix/rootfs" |
f0a2c7b4 II |
277 | |
278 | #define CONFIG_CON_ROT "fbcon=rotate:3 " | |
f0a2c7b4 | 279 | |
f0a2c7b4 | 280 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
43ede0bc TR |
281 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
282 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ | |
f0a2c7b4 II |
283 | "partition=nand0,0\0" \ |
284 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
285 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
286 | CONFIG_CON_ROT \ | |
287 | "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ | |
288 | "addip=setenv bootargs $(bootargs) " \ | |
289 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ | |
290 | ":$(hostname):eth0:off\0" \ | |
291 | "ramboot=tftpboot 0x22000000 vmImage;" \ | |
292 | "run ramargs;run addip;bootm 22000000\0" \ | |
293 | "nfsboot=tftpboot 0x22000000 vmImage;" \ | |
294 | "run nfsargs;run addip;bootm 22000000\0" \ | |
295 | "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ | |
296 | "" | |
297 | ||
298 | #else | |
299 | #error "Undefined memory device" | |
300 | #endif | |
301 | ||
f0a2c7b4 II |
302 | #define CONFIG_SYS_LONGHELP 1 |
303 | #define CONFIG_CMDLINE_EDITING 1 | |
304 | ||
f0a2c7b4 II |
305 | /* |
306 | * Size of malloc() pool | |
307 | */ | |
308 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) | |
f0a2c7b4 | 309 | |
9a2a05a4 | 310 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
0dfe3ffe | 311 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ |
9a2a05a4 AD |
312 | GENERATED_GBL_DATA_SIZE) |
313 | ||
f0a2c7b4 | 314 | #endif |