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f0a2c7b4 II |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
f0a2c7b4 II |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
7 | * Configuation settings for the RONETIX PM9263 board. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f0a2c7b4 II |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
684a567a AD |
15 | /* |
16 | * SoC must be defined first, before hardware.h is included. | |
17 | * In this case SoC is defined in boards.cfg. | |
18 | */ | |
19 | #include <asm/hardware.h> | |
20 | ||
efe62a66 GB |
21 | #define CONFIG_SYS_GENERIC_BOARD |
22 | ||
f0a2c7b4 | 23 | /* ARM asynchronous clock */ |
b2403589 | 24 | #define CONFIG_DISPLAY_CPUINFO |
f0a2c7b4 II |
25 | #define CONFIG_DISPLAY_BOARDINFO |
26 | ||
01550a2b JCPV |
27 | #define MASTER_PLL_DIV 6 |
28 | #define MASTER_PLL_MUL 65 | |
f0a2c7b4 | 29 | #define MAIN_PLL_DIV 2 /* 2 or 4 */ |
7c966a8b | 30 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
684a567a | 31 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
f0a2c7b4 | 32 | |
684a567a | 33 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" |
f0a2c7b4 II |
34 | #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ |
35 | #define CONFIG_ARCH_CPU_INIT | |
9a2a05a4 | 36 | #define CONFIG_SYS_TEXT_BASE 0 |
f0a2c7b4 | 37 | |
a3e09cc2 AD |
38 | #define MACH_TYPE_PM9263 1475 |
39 | #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 | |
40 | ||
f0a2c7b4 | 41 | /* clocks */ |
01550a2b | 42 | #define CONFIG_SYS_MOR_VAL \ |
20d98c2c | 43 | (AT91_PMC_MOR_MOSCEN | \ |
01550a2b JCPV |
44 | (255 << 8)) /* Main Oscillator Start-up Time */ |
45 | #define CONFIG_SYS_PLLAR_VAL \ | |
20d98c2c AD |
46 | (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ |
47 | AT91_PMC_PLLXR_OUT(3) | \ | |
48 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ | |
01550a2b JCPV |
49 | (2 << 28) | /* PLL Clock Frequency Range */ \ |
50 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) | |
f0a2c7b4 II |
51 | |
52 | #if (MAIN_PLL_DIV == 2) | |
53 | /* PCK/2 = MCK Master Clock from PLLA */ | |
01550a2b | 54 | #define CONFIG_SYS_MCKR1_VAL \ |
20d98c2c AD |
55 | (AT91_PMC_MCKR_CSS_SLOW | \ |
56 | AT91_PMC_MCKR_PRES_1 | \ | |
57 | AT91_PMC_MCKR_MDIV_2) | |
f0a2c7b4 | 58 | /* PCK/2 = MCK Master Clock from PLLA */ |
01550a2b | 59 | #define CONFIG_SYS_MCKR2_VAL \ |
20d98c2c AD |
60 | (AT91_PMC_MCKR_CSS_PLLA | \ |
61 | AT91_PMC_MCKR_PRES_1 | \ | |
62 | AT91_PMC_MCKR_MDIV_2) | |
f0a2c7b4 II |
63 | #else |
64 | /* PCK/4 = MCK Master Clock from PLLA */ | |
01550a2b | 65 | #define CONFIG_SYS_MCKR1_VAL \ |
20d98c2c AD |
66 | (AT91_PMC_MCKR_CSS_SLOW | \ |
67 | AT91_PMC_MCKR_PRES_1 | \ | |
68 | AT91_PMC_MCKR_MDIV_4) | |
f0a2c7b4 | 69 | /* PCK/4 = MCK Master Clock from PLLA */ |
01550a2b | 70 | #define CONFIG_SYS_MCKR2_VAL \ |
20d98c2c AD |
71 | (AT91_PMC_MCKR_CSS_PLLA | \ |
72 | AT91_PMC_MCKR_PRES_1 | \ | |
73 | AT91_PMC_MCKR_MDIV_4) | |
f0a2c7b4 II |
74 | #endif |
75 | /* define PDC[31:16] as DATA[31:16] */ | |
76 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | |
77 | /* no pull-up for D[31:16] */ | |
78 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | |
79 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | |
01550a2b | 80 | #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ |
20d98c2c AD |
81 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
82 | AT91_MATRIX_CSA_EBI_CS1A) | |
f0a2c7b4 II |
83 | |
84 | /* SDRAM */ | |
85 | /* SDRAMC_MR Mode register */ | |
86 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | |
87 | /* SDRAMC_TR - Refresh Timer register */ | |
01550a2b JCPV |
88 | #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA |
89 | /* SDRAMC_CR - Configuration register*/ | |
90 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
91 | (AT91_SDRAMC_NC_9 | \ | |
92 | AT91_SDRAMC_NR_13 | \ | |
93 | AT91_SDRAMC_NB_4 | \ | |
94 | AT91_SDRAMC_CAS_2 | \ | |
95 | AT91_SDRAMC_DBW_32 | \ | |
96 | (2 << 8) | /* tWR - Write Recovery Delay */ \ | |
97 | (7 << 12) | /* tRC - Row Cycle Delay */ \ | |
98 | (2 << 16) | /* tRP - Row Precharge Delay */ \ | |
99 | (2 << 20) | /* tRCD - Row to Column Delay */ \ | |
100 | (5 << 24) | /* tRAS - Active to Precharge Delay */ \ | |
101 | (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ | |
102 | ||
f0a2c7b4 | 103 | /* Memory Device Register -> SDRAM */ |
01550a2b JCPV |
104 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
105 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
f0a2c7b4 | 106 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
01550a2b | 107 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
f0a2c7b4 II |
108 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
109 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
110 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
111 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
112 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
113 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
114 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
115 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
01550a2b | 116 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
f0a2c7b4 | 117 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
01550a2b | 118 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
f0a2c7b4 II |
119 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
120 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
121 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
122 | ||
123 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
01550a2b | 124 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
20d98c2c AD |
125 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
126 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
01550a2b | 127 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
20d98c2c AD |
128 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
129 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
01550a2b | 130 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
20d98c2c | 131 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
01550a2b | 132 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
20d98c2c AD |
133 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
134 | AT91_SMC_MODE_DBW_16 | \ | |
135 | AT91_SMC_MODE_TDF | \ | |
136 | AT91_SMC_MODE_TDF_CYCLE(6)) | |
f0a2c7b4 | 137 | |
01550a2b JCPV |
138 | /* user reset enable */ |
139 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
140 | (AT91_RSTC_KEY | \ | |
20d98c2c AD |
141 | AT91_RSTC_CR_PROCRST | \ |
142 | AT91_RSTC_MR_ERSTL(1) | \ | |
143 | AT91_RSTC_MR_ERSTL(2)) | |
f0a2c7b4 | 144 | |
01550a2b JCPV |
145 | /* Disable Watchdog */ |
146 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
20d98c2c AD |
147 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
148 | AT91_WDT_MR_WDV(0xfff) | \ | |
149 | AT91_WDT_MR_WDDIS | \ | |
150 | AT91_WDT_MR_WDD(0xfff)) | |
f0a2c7b4 II |
151 | |
152 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
153 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
154 | #define CONFIG_INITRD_TAG 1 | |
155 | ||
156 | #undef CONFIG_SKIP_LOWLEVEL_INIT | |
f0a2c7b4 | 157 | #define CONFIG_USER_LOWLEVEL_INIT 1 |
52b26016 | 158 | #define CONFIG_BOARD_EARLY_INIT_F |
f0a2c7b4 II |
159 | |
160 | /* | |
161 | * Hardware drivers | |
162 | */ | |
ea8fbba7 | 163 | #define CONFIG_AT91_GPIO 1 |
f0a2c7b4 | 164 | #define CONFIG_ATMEL_USART 1 |
684a567a AD |
165 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
166 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
f0a2c7b4 II |
167 | |
168 | /* LCD */ | |
169 | #define CONFIG_LCD 1 | |
170 | #define LCD_BPP LCD_COLOR8 | |
171 | #define CONFIG_LCD_LOGO 1 | |
172 | #undef LCD_TEST_PATTERN | |
173 | #define CONFIG_LCD_INFO 1 | |
174 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
175 | #define CONFIG_SYS_WHITE_ON_BLACK 1 | |
176 | #define CONFIG_ATMEL_LCD 1 | |
177 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
178 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
179 | ||
180 | #define CONFIG_LCD_IN_PSRAM 1 | |
181 | ||
182 | /* LED */ | |
183 | #define CONFIG_AT91_LED | |
bcf9fe37 AB |
184 | #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ |
185 | #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ | |
f0a2c7b4 II |
186 | |
187 | #define CONFIG_BOOTDELAY 3 | |
188 | ||
189 | /* | |
190 | * BOOTP options | |
191 | */ | |
192 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
193 | #define CONFIG_BOOTP_BOOTPATH 1 | |
194 | #define CONFIG_BOOTP_GATEWAY 1 | |
195 | #define CONFIG_BOOTP_HOSTNAME 1 | |
196 | ||
197 | /* | |
198 | * Command line configuration. | |
199 | */ | |
200 | #include <config_cmd_default.h> | |
201 | #undef CONFIG_CMD_BDI | |
202 | #undef CONFIG_CMD_IMI | |
f0a2c7b4 II |
203 | #undef CONFIG_CMD_FPGA |
204 | #undef CONFIG_CMD_LOADS | |
205 | #undef CONFIG_CMD_IMLS | |
206 | ||
6e110d29 | 207 | #define CONFIG_CMD_CACHE |
f0a2c7b4 II |
208 | #define CONFIG_CMD_PING 1 |
209 | #define CONFIG_CMD_DHCP 1 | |
210 | #define CONFIG_CMD_NAND 1 | |
211 | #define CONFIG_CMD_USB 1 | |
212 | ||
213 | /* SDRAM */ | |
214 | #define CONFIG_NR_DRAM_BANKS 1 | |
215 | #define PHYS_SDRAM 0x20000000 | |
216 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
217 | ||
218 | /* DataFlash */ | |
219 | #define CONFIG_ATMEL_DATAFLASH_SPI | |
220 | #define CONFIG_HAS_DATAFLASH 1 | |
f0a2c7b4 II |
221 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
222 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
223 | #define AT91_SPI_CLK 15000000 | |
224 | #define DATAFLASH_TCSS (0x1a << 16) | |
225 | #define DATAFLASH_TCHS (0x1 << 24) | |
226 | ||
227 | /* NOR flash, if populated */ | |
228 | #define CONFIG_SYS_FLASH_CFI 1 | |
229 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
230 | #define PHYS_FLASH_1 0x10000000 | |
231 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
232 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
233 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
234 | ||
235 | /* NAND flash */ | |
236 | #ifdef CONFIG_CMD_NAND | |
237 | #define CONFIG_NAND_ATMEL | |
f0a2c7b4 II |
238 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
239 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
240 | #define CONFIG_SYS_NAND_DBW_8 1 | |
241 | /* our ALE is AD21 */ | |
242 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
243 | /* our CLE is AD22 */ | |
244 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
ac45bb16 AB |
245 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) |
246 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) | |
2eb99ca8 | 247 | |
f0a2c7b4 II |
248 | #endif |
249 | ||
250 | #define CONFIG_CMD_JFFS2 1 | |
251 | #define CONFIG_JFFS2_CMDLINE 1 | |
252 | #define CONFIG_JFFS2_NAND 1 | |
253 | #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ | |
254 | #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ | |
255 | #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ | |
256 | ||
257 | /* PSRAM */ | |
258 | #define PHYS_PSRAM 0x70000000 | |
259 | #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ | |
20d98c2c AD |
260 | /* Slave EBI1, PSRAM connected */ |
261 | #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ | |
262 | AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ | |
263 | AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ | |
264 | AT91_MATRIX_SCFG_SLOT_CYCLE(255)) | |
f0a2c7b4 II |
265 | |
266 | /* Ethernet */ | |
267 | #define CONFIG_MACB 1 | |
268 | #define CONFIG_RMII 1 | |
f0a2c7b4 II |
269 | #define CONFIG_NET_RETRY_COUNT 20 |
270 | #define CONFIG_RESET_PHY_R 1 | |
271 | ||
272 | /* USB */ | |
273 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 274 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
f0a2c7b4 II |
275 | #define CONFIG_USB_OHCI_NEW 1 |
276 | #define CONFIG_DOS_PARTITION 1 | |
277 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
278 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
279 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | |
280 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
281 | #define CONFIG_USB_STORAGE 1 | |
282 | ||
283 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | |
284 | ||
285 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
286 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
287 | ||
288 | #define CONFIG_SYS_USE_FLASH 1 | |
289 | #undef CONFIG_SYS_USE_DATAFLASH | |
290 | #undef CONFIG_SYS_USE_NANDFLASH | |
291 | ||
292 | #ifdef CONFIG_SYS_USE_DATAFLASH | |
293 | ||
294 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
295 | #define CONFIG_ENV_IS_IN_DATAFLASH | |
296 | #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) | |
297 | #define CONFIG_ENV_OFFSET 0x4200 | |
298 | #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) | |
299 | #define CONFIG_ENV_SIZE 0x4200 | |
300 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" | |
301 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
302 | "root=/dev/mtdblock0 " \ | |
918319c7 | 303 | "mtdparts=atmel_nand:-(root) "\ |
f0a2c7b4 II |
304 | "rw rootfstype=jffs2" |
305 | ||
306 | #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ | |
307 | ||
308 | /* bootstrap + u-boot + env + linux in nandflash */ | |
309 | #define CONFIG_ENV_IS_IN_NAND | |
310 | #define CONFIG_ENV_OFFSET 0x60000 | |
311 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
312 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
313 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" | |
314 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
315 | "root=/dev/mtdblock5 " \ | |
918319c7 | 316 | "mtdparts=atmel_nand:" \ |
f0a2c7b4 II |
317 | "128k(bootstrap)ro," \ |
318 | "256k(uboot)ro," \ | |
319 | "128k(env1)ro," \ | |
320 | "128k(env2)ro," \ | |
321 | "2M(linux)," \ | |
322 | "-(root) " \ | |
323 | "rw rootfstype=jffs2" | |
324 | ||
325 | #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ | |
326 | ||
327 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
328 | #define CONFIG_ENV_OFFSET 0x40000 | |
329 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
330 | #define CONFIG_ENV_SIZE 0x10000 | |
331 | #define CONFIG_ENV_OVERWRITE 1 | |
332 | ||
333 | /* JFFS Partition offset set */ | |
334 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 | |
335 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
336 | ||
337 | /* 512k reserved for u-boot */ | |
338 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 | |
339 | ||
340 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
8b3637c6 | 341 | #define CONFIG_ROOTPATH "/ronetix/rootfs" |
6236fd75 | 342 | #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay |
f0a2c7b4 II |
343 | |
344 | #define CONFIG_CON_ROT "fbcon=rotate:3 " | |
345 | #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ | |
346 | CONFIG_CON_ROT | |
347 | ||
348 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" | |
349 | #define MTDPARTS_DEFAULT \ | |
350 | "mtdparts=physmap-flash.0:" \ | |
351 | "256k(u-boot)ro," \ | |
352 | "64k(u-boot-env)ro," \ | |
353 | "1408k(kernel)," \ | |
354 | "-(rootfs);" \ | |
355 | "nand:-(nand)" | |
356 | ||
357 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
358 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
359 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
360 | "partition=nand0,0\0" \ | |
361 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
362 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
363 | CONFIG_CON_ROT \ | |
364 | "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ | |
365 | "addip=setenv bootargs $(bootargs) " \ | |
366 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ | |
367 | ":$(hostname):eth0:off\0" \ | |
368 | "ramboot=tftpboot 0x22000000 vmImage;" \ | |
369 | "run ramargs;run addip;bootm 22000000\0" \ | |
370 | "nfsboot=tftpboot 0x22000000 vmImage;" \ | |
371 | "run nfsargs;run addip;bootm 22000000\0" \ | |
372 | "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ | |
373 | "" | |
374 | ||
375 | #else | |
376 | #error "Undefined memory device" | |
377 | #endif | |
378 | ||
379 | #define CONFIG_BAUDRATE 115200 | |
f0a2c7b4 II |
380 | |
381 | #define CONFIG_SYS_PROMPT "u-boot-pm9263> " | |
382 | #define CONFIG_SYS_CBSIZE 256 | |
383 | #define CONFIG_SYS_MAXARGS 16 | |
384 | #define CONFIG_SYS_PBSIZE \ | |
385 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
386 | #define CONFIG_SYS_LONGHELP 1 | |
387 | #define CONFIG_CMDLINE_EDITING 1 | |
388 | ||
f0a2c7b4 II |
389 | /* |
390 | * Size of malloc() pool | |
391 | */ | |
392 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) | |
f0a2c7b4 | 393 | |
9a2a05a4 AD |
394 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
395 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
396 | GENERATED_GBL_DATA_SIZE) | |
397 | ||
f0a2c7b4 | 398 | #endif |