[people/ms/u-boot.git] / include / configs / pm9263.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuation settings for the RONETIX PM9263 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define MASTER_PLL_DIV		6
#define MASTER_PLL_MUL		65
#define MAIN_PLL_DIV		2	/* 2 or 4 */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000

#define CONFIG_SYS_HZ		1000

#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define CONFIG_AT91SAM9263	1	/* It's an Atmel AT91SAM9263 SoC*/
#define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

/* clocks */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_PLLXR_OUT(3) |				\
		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
		 (2 << 28) |		/* PLL Clock Frequency Range */	\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_MCKR_CSS_SLOW |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_MCKR_CSS_PLLA |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL			\
		(AT91_PMC_MCKR_CSS_SLOW |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL			\
		(AT91_PMC_MCKR_CSS_PLLA |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_2 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |					\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_USER_LOWLEVEL_INIT	1

/*
 * Hardware drivers
 */
#define CONFIG_AT91_GPIO	1
#define CONFIG_ATMEL_USART	1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3		1	/* USART 3 is DBGU */

/* LCD */
#define CONFIG_LCD			1
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_SYS_WHITE_ON_BLACK	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

#define CONFIG_LCD_IN_PSRAM		1

/* LED */
#define CONFIG_AT91_LED
#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* this is the power led */
#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* this is the user1 led */

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_PING		1
#define CONFIG_CMD_DHCP		1
#define CONFIG_CMD_NAND		1
#define CONFIG_CMD_USB		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH			1
#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define AT91_SPI_CLK				15000000
#define DATAFLASH_TCSS				(0x1a << 16)
#define DATAFLASH_TCHS				(0x1 << 24)

/* NOR flash, if populated */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define PHYS_FLASH_1			0x10000000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 30

#endif

#define CONFIG_CMD_JFFS2		1
#define CONFIG_JFFS2_CMDLINE		1
#define CONFIG_JFFS2_NAND		1
#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/

/* PSRAM */
#define	PHYS_PSRAM			0x70000000
#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
/* Slave EBI1, PSRAM connected */
#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))

/* Ethernet */
#define CONFIG_MACB			1
#define CONFIG_RMII			1
#define CONFIG_NET_MULTI		1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW			1
#define CONFIG_DOS_PARTITION			1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE			1

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#define CONFIG_SYS_USE_FLASH	1
#undef CONFIG_SYS_USE_DATAFLASH
#undef CONFIG_SYS_USE_NANDFLASH

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH
#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
				"root=/dev/mtdblock0 " \
				"mtdparts=atmel_nand:-(root) "\
				"rw rootfstype=jffs2"

#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
				"root=/dev/mtdblock5 "		\
				"mtdparts=atmel_nand:"		\
					"128k(bootstrap)ro,"	\
					"256k(uboot)ro,"	\
					"128k(env1)ro,"		\
					"128k(env2)ro,"		\
					"2M(linux),"		\
					"-(root) "		\
				"rw rootfstype=jffs2"

#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define	CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_OVERWRITE	1

/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11

#define CONFIG_BOOTCOMMAND		"run flashboot"
#define CONFIG_ROOTPATH			/ronetix/rootfs
#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"

#define CONFIG_CON_ROT			"fbcon=rotate:3 "
#define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
					CONFIG_CON_ROT

#define MTDIDS_DEFAULT			"nor0=physmap-flash.0,nand0=nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"256k(u-boot)ro,"	\
		"64k(u-boot-env)ro,"	\
		"1408k(kernel),"	\
		"-(rootfs);"		\
	"nand:-(nand)"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		CONFIG_CON_ROT					\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""

#else
#error "Undefined memory device"
#endif

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"u-boot-pm9263> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
f0a2c7b4 II	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Ilko Iliev <www.ronetix.at>
	6	*
	7	* Configuation settings for the RONETIX PM9263 board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/* ARM asynchronous clock */
b2403589	32	#define CONFIG_DISPLAY_CPUINFO
f0a2c7b4 II	33	#define CONFIG_DISPLAY_BOARDINFO
f0a2c7b4 II	34
01550a2b JCPV	35	#define MASTER_PLL_DIV 6
01550a2b JCPV	36	#define MASTER_PLL_MUL 65
f0a2c7b4	37	#define MAIN_PLL_DIV 2 /* 2 or 4 */
7c966a8b	38	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
f0a2c7b4	39
6ebff365	40	#define CONFIG_SYS_HZ 1000
f0a2c7b4 II	41
	42	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	43	#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
	44	#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
	45	#define CONFIG_ARCH_CPU_INIT
	46	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	47
	48	/* clocks */
01550a2b	49	#define CONFIG_SYS_MOR_VAL \
20d98c2c	50	(AT91_PMC_MOR_MOSCEN \| \
01550a2b JCPV	51	(255 << 8)) /* Main Oscillator Start-up Time */
01550a2b JCPV	52	#define CONFIG_SYS_PLLAR_VAL \
20d98c2c AD	53	(AT91_PMC_PLLAR_29 \| /* Bit 29 must be 1 when prog */ \
	54	AT91_PMC_PLLXR_OUT(3) \| \
	55	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \| /* PLL Counter */\
01550a2b JCPV	56	(2 << 28) \| /* PLL Clock Frequency Range */ \
01550a2b JCPV	57	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
f0a2c7b4 II	58
	59	#if (MAIN_PLL_DIV == 2)
	60	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	61	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	62	(AT91_PMC_MCKR_CSS_SLOW \| \
	63	AT91_PMC_MCKR_PRES_1 \| \
	64	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4	65	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	66	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	67	(AT91_PMC_MCKR_CSS_PLLA \| \
	68	AT91_PMC_MCKR_PRES_1 \| \
	69	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4 II	70	#else
f0a2c7b4 II	71	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	72	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	73	(AT91_PMC_MCKR_CSS_SLOW \| \
	74	AT91_PMC_MCKR_PRES_1 \| \
	75	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4	76	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	77	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	78	(AT91_PMC_MCKR_CSS_PLLA \| \
	79	AT91_PMC_MCKR_PRES_1 \| \
	80	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4 II	81	#endif
	82	/* define PDC[31:16] as DATA[31:16] */
	83	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	84	/* no pull-up for D[31:16] */
	85	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	86	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
01550a2b	87	#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
20d98c2c AD	88	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
20d98c2c AD	89	AT91_MATRIX_CSA_EBI_CS1A)
f0a2c7b4 II	90
	91	/* SDRAM */
	92	/* SDRAMC_MR Mode register */
	93	#define CONFIG_SYS_SDRC_MR_VAL1 0
	94	/* SDRAMC_TR - Refresh Timer register */
01550a2b JCPV	95	#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
	96	/* SDRAMC_CR - Configuration register*/
	97	#define CONFIG_SYS_SDRC_CR_VAL \
	98	(AT91_SDRAMC_NC_9 \| \
	99	AT91_SDRAMC_NR_13 \| \
	100	AT91_SDRAMC_NB_4 \| \
	101	AT91_SDRAMC_CAS_2 \| \
	102	AT91_SDRAMC_DBW_32 \| \
	103	(2 << 8) \| /* tWR - Write Recovery Delay */ \
	104	(7 << 12) \| /* tRC - Row Cycle Delay */ \
	105	(2 << 16) \| /* tRP - Row Precharge Delay */ \
	106	(2 << 20) \| /* tRCD - Row to Column Delay */ \
	107	(5 << 24) \| /* tRAS - Active to Precharge Delay */ \
	108	(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
	109
f0a2c7b4	110	/* Memory Device Register -> SDRAM */
01550a2b JCPV	111	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
01550a2b JCPV	112	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
f0a2c7b4	113	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
01550a2b	114	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
f0a2c7b4 II	115	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	116	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	117	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	118	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	119	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	120	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	121	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	122	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
01550a2b	123	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
f0a2c7b4	124	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
01550a2b	125	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
f0a2c7b4 II	126	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	127	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	128	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	129
	130	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
01550a2b	131	#define CONFIG_SYS_SMC0_SETUP0_VAL \
20d98c2c AD	132	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
20d98c2c AD	133	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
01550a2b	134	#define CONFIG_SYS_SMC0_PULSE0_VAL \
20d98c2c AD	135	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
20d98c2c AD	136	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
01550a2b	137	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
20d98c2c	138	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
01550a2b	139	#define CONFIG_SYS_SMC0_MODE0_VAL \
20d98c2c AD	140	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	141	AT91_SMC_MODE_DBW_16 \| \
	142	AT91_SMC_MODE_TDF \| \
	143	AT91_SMC_MODE_TDF_CYCLE(6))
f0a2c7b4	144
01550a2b JCPV	145	/* user reset enable */
	146	#define CONFIG_SYS_RSTC_RMR_VAL \
	147	(AT91_RSTC_KEY \| \
20d98c2c AD	148	AT91_RSTC_CR_PROCRST \| \
	149	AT91_RSTC_MR_ERSTL(1) \| \
	150	AT91_RSTC_MR_ERSTL(2))
f0a2c7b4	151
01550a2b JCPV	152	/* Disable Watchdog */
01550a2b JCPV	153	#define CONFIG_SYS_WDTC_WDMR_VAL \
20d98c2c AD	154	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	155	AT91_WDT_MR_WDV(0xfff) \| \
	156	AT91_WDT_MR_WDDIS \| \
	157	AT91_WDT_MR_WDD(0xfff))
f0a2c7b4 II	158
	159	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	160	#define CONFIG_SETUP_MEMORY_TAGS 1
	161	#define CONFIG_INITRD_TAG 1
	162
	163	#undef CONFIG_SKIP_LOWLEVEL_INIT
f0a2c7b4 II	164	#define CONFIG_USER_LOWLEVEL_INIT 1
	165
	166	/*
	167	* Hardware drivers
	168	*/
ea8fbba7	169	#define CONFIG_AT91_GPIO 1
f0a2c7b4 II	170	#define CONFIG_ATMEL_USART 1
	171	#undef CONFIG_USART0
	172	#undef CONFIG_USART1
	173	#undef CONFIG_USART2
	174	#define CONFIG_USART3 1 /* USART 3 is DBGU */
	175
	176	/* LCD */
	177	#define CONFIG_LCD 1
	178	#define LCD_BPP LCD_COLOR8
	179	#define CONFIG_LCD_LOGO 1
	180	#undef LCD_TEST_PATTERN
	181	#define CONFIG_LCD_INFO 1
	182	#define CONFIG_LCD_INFO_BELOW_LOGO 1
	183	#define CONFIG_SYS_WHITE_ON_BLACK 1
	184	#define CONFIG_ATMEL_LCD 1
	185	#define CONFIG_ATMEL_LCD_BGR555 1
	186	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	187
	188	#define CONFIG_LCD_IN_PSRAM 1
	189
	190	/* LED */
	191	#define CONFIG_AT91_LED
20d98c2c AD	192	#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
20d98c2c AD	193	#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
f0a2c7b4 II	194
	195	#define CONFIG_BOOTDELAY 3
	196
	197	/*
	198	* BOOTP options
	199	*/
	200	#define CONFIG_BOOTP_BOOTFILESIZE 1
	201	#define CONFIG_BOOTP_BOOTPATH 1
	202	#define CONFIG_BOOTP_GATEWAY 1
	203	#define CONFIG_BOOTP_HOSTNAME 1
	204
	205	/*
	206	* Command line configuration.
	207	*/
	208	#include <config_cmd_default.h>
	209	#undef CONFIG_CMD_BDI
	210	#undef CONFIG_CMD_IMI
f0a2c7b4 II	211	#undef CONFIG_CMD_FPGA
	212	#undef CONFIG_CMD_LOADS
	213	#undef CONFIG_CMD_IMLS
	214
	215	#define CONFIG_CMD_PING 1
	216	#define CONFIG_CMD_DHCP 1
	217	#define CONFIG_CMD_NAND 1
	218	#define CONFIG_CMD_USB 1
	219
	220	/* SDRAM */
	221	#define CONFIG_NR_DRAM_BANKS 1
	222	#define PHYS_SDRAM 0x20000000
	223	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	224
	225	/* DataFlash */
	226	#define CONFIG_ATMEL_DATAFLASH_SPI
	227	#define CONFIG_HAS_DATAFLASH 1
	228	#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
	229	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
	230	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
	231	#define AT91_SPI_CLK 15000000
	232	#define DATAFLASH_TCSS (0x1a << 16)
	233	#define DATAFLASH_TCHS (0x1 << 24)
	234
	235	/* NOR flash, if populated */
	236	#define CONFIG_SYS_FLASH_CFI 1
	237	#define CONFIG_FLASH_CFI_DRIVER 1
	238	#define PHYS_FLASH_1 0x10000000
	239	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	240	#define CONFIG_SYS_MAX_FLASH_SECT 256
	241	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	242
	243	/* NAND flash */
	244	#ifdef CONFIG_CMD_NAND
	245	#define CONFIG_NAND_ATMEL
	246	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	247	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	248	#define CONFIG_SYS_NAND_BASE 0x40000000
	249	#define CONFIG_SYS_NAND_DBW_8 1
	250	/* our ALE is AD21 */
	251	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	252	/* our CLE is AD22 */
	253	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
20d98c2c AD	254	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
20d98c2c AD	255	#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
2eb99ca8	256
f0a2c7b4 II	257	#endif
	258
	259	#define CONFIG_CMD_JFFS2 1
	260	#define CONFIG_JFFS2_CMDLINE 1
	261	#define CONFIG_JFFS2_NAND 1
	262	#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
	263	#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
	264	#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
	265
	266	/* PSRAM */
	267	#define PHYS_PSRAM 0x70000000
	268	#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
20d98c2c AD	269	/* Slave EBI1, PSRAM connected */
	270	#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY \| \
	271	AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) \| \
	272	AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED \| \
	273	AT91_MATRIX_SCFG_SLOT_CYCLE(255))
f0a2c7b4 II	274
	275	/* Ethernet */
	276	#define CONFIG_MACB 1
	277	#define CONFIG_RMII 1
	278	#define CONFIG_NET_MULTI 1
	279	#define CONFIG_NET_RETRY_COUNT 20
	280	#define CONFIG_RESET_PHY_R 1
	281
	282	/* USB */
	283	#define CONFIG_USB_ATMEL
	284	#define CONFIG_USB_OHCI_NEW 1
	285	#define CONFIG_DOS_PARTITION 1
	286	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	287	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
	288	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	289	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
	290	#define CONFIG_USB_STORAGE 1
	291
	292	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	293
	294	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	295	#define CONFIG_SYS_MEMTEST_END 0x23e00000
	296
	297	#define CONFIG_SYS_USE_FLASH 1
	298	#undef CONFIG_SYS_USE_DATAFLASH
	299	#undef CONFIG_SYS_USE_NANDFLASH
	300
	301	#ifdef CONFIG_SYS_USE_DATAFLASH
	302
	303	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
	304	#define CONFIG_ENV_IS_IN_DATAFLASH
	305	#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
	306	#define CONFIG_ENV_OFFSET 0x4200
	307	#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
	308	#define CONFIG_ENV_SIZE 0x4200
	309	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
	310	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	311	"root=/dev/mtdblock0 " \
918319c7	312	"mtdparts=atmel_nand:-(root) "\
f0a2c7b4 II	313	"rw rootfstype=jffs2"
	314
	315	#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
	316
	317	/* bootstrap + u-boot + env + linux in nandflash */
	318	#define CONFIG_ENV_IS_IN_NAND
	319	#define CONFIG_ENV_OFFSET 0x60000
	320	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	321	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	322	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
	323	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	324	"root=/dev/mtdblock5 " \
918319c7	325	"mtdparts=atmel_nand:" \
f0a2c7b4 II	326	"128k(bootstrap)ro," \
	327	"256k(uboot)ro," \
	328	"128k(env1)ro," \
	329	"128k(env2)ro," \
	330	"2M(linux)," \
	331	"-(root) " \
	332	"rw rootfstype=jffs2"
	333
	334	#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
	335
	336	#define CONFIG_ENV_IS_IN_FLASH 1
	337	#define CONFIG_ENV_OFFSET 0x40000
	338	#define CONFIG_ENV_SECT_SIZE 0x10000
	339	#define CONFIG_ENV_SIZE 0x10000
	340	#define CONFIG_ENV_OVERWRITE 1
	341
	342	/* JFFS Partition offset set */
	343	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	344	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	345
	346	/* 512k reserved for u-boot */
	347	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
	348
	349	#define CONFIG_BOOTCOMMAND "run flashboot"
	350	#define CONFIG_ROOTPATH /ronetix/rootfs
	351	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
	352
	353	#define CONFIG_CON_ROT "fbcon=rotate:3 "
	354	#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
	355	CONFIG_CON_ROT
	356
	357	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
	358	#define MTDPARTS_DEFAULT \
	359	"mtdparts=physmap-flash.0:" \
	360	"256k(u-boot)ro," \
	361	"64k(u-boot-env)ro," \
	362	"1408k(kernel)," \
	363	"-(rootfs);" \
	364	"nand:-(nand)"
	365
	366	#define CONFIG_EXTRA_ENV_SETTINGS \
	367	"mtdids=" MTDIDS_DEFAULT "\0" \
	368	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	369	"partition=nand0,0\0" \
	370	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	371	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	372	CONFIG_CON_ROT \
	373	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	374	"addip=setenv bootargs $(bootargs) " \
	375	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	376	":$(hostname):eth0:off\0" \
	377	"ramboot=tftpboot 0x22000000 vmImage;" \
	378	"run ramargs;run addip;bootm 22000000\0" \
	379	"nfsboot=tftpboot 0x22000000 vmImage;" \
	380	"run nfsargs;run addip;bootm 22000000\0" \
	381	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	382	""
	383
	384	#else
	385	#error "Undefined memory device"
	386	#endif
	387
	388	#define CONFIG_BAUDRATE 115200
	389	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
390
391	#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
392	#define CONFIG_SYS_CBSIZE 256
393	#define CONFIG_SYS_MAXARGS 16
394	#define CONFIG_SYS_PBSIZE \
395	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
396	#define CONFIG_SYS_LONGHELP 1
397	#define CONFIG_CMDLINE_EDITING 1
398
f0a2c7b4 II	399	/*
	400	* Size of malloc() pool
	401	*/
	402	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
f0a2c7b4 II	403
	404	#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
	405
	406	#ifdef CONFIG_USE_IRQ
	407	#error CONFIG_USE_IRQ not supported
	408	#endif
	409
	410	#endif