projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c646bba6 JH |
1 | /* |
| 2 | * Copyright 2007 Wind River Systems <www.windriver.com> | |
| 3 | * Copyright 2007 Embedded Specialties, Inc. | |
| 4 | * Joe Hamman <joe.hamman@embeddedspecialties.com> | |
| 5 | * | |
| 6 | * Copyright 2006 Freescale Semiconductor. | |
| 7 | * | |
| 8 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) | |
| 9 | * | |
| 10 | * See file CREDITS for list of people who contributed to this | |
| 11 | * project. | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or | |
| 14 | * modify it under the terms of the GNU General Public License as | |
| 15 | * published by the Free Software Foundation; either version 2 of | |
| 16 | * the License, or (at your option) any later version. | |
| 17 | * | |
| 18 | * This program is distributed in the hope that it will be useful, | |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 21 | * GNU General Public License for more details. | |
| 22 | * | |
| 23 | * You should have received a copy of the GNU General Public License | |
| 24 | * along with this program; if not, write to the Free Software | |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 26 | * MA 02111-1307 USA | |
| 27 | */ | |
| 28 | ||
| 29 | /* | |
| 30 | * SBC8641D board configuration file | |
| 31 | * | |
| 32 | * Make sure you change the MAC address and other network params first, | |
| 33 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
| 34 | */ | |
| 35 | ||
| 36 | #ifndef __CONFIG_H | |
| 37 | #define __CONFIG_H | |
| 38 | ||
| 39 | /* High Level Configuration Options */ | |
| 40 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 41 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 42 | #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ | |
| 7649a590 | 43 | #define CONFIG_MP 1 /* support multiple processors */ |
| c646bba6 JH |
44 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| 45 | ||
| 46 | #ifdef RUN_DIAG | |
| 6d0f6bcf | 47 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
| c646bba6 JH |
48 | #endif |
| 49 | ||
| 6d0f6bcf | 50 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
| c646bba6 | 51 | |
| 1266df88 BB |
52 | /* |
| 53 | * virtual address to be used for temporary mappings. There | |
| 54 | * should be 128k free at this VA. | |
| 55 | */ | |
| 56 | #define CONFIG_SYS_SCRATCH_VA 0xe8000000 | |
| 57 | ||
| cca34967 JH |
58 | #define CONFIG_PCI 1 /* Enable PCIE */ |
| 59 | #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ | |
| 60 | #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ | |
| 61 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 713d8186 | 62 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| c646bba6 | 63 | |
| 53677ef1 | 64 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| c646bba6 JH |
65 | #define CONFIG_ENV_OVERWRITE |
| 66 | ||
| 23f935c0 BB |
67 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| 68 | ||
| c646bba6 | 69 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ |
| 53677ef1 | 70 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| c646bba6 JH |
71 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 72 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 73 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 74 | #define CACHE_LINE_INTERLEAVING 0x20000000 | |
| 75 | #define PAGE_INTERLEAVING 0x21000000 | |
| 76 | #define BANK_INTERLEAVING 0x22000000 | |
| 77 | #define SUPER_BANK_INTERLEAVING 0x23000000 | |
| 78 | ||
| 79 | ||
| 80 | #define CONFIG_ALTIVEC 1 | |
| 81 | ||
| 82 | /* | |
| 83 | * L2CR setup -- make sure this is right for your board! | |
| 84 | */ | |
| 6d0f6bcf | 85 | #define CONFIG_SYS_L2 |
| c646bba6 JH |
86 | #define L2_INIT 0 |
| 87 | #define L2_ENABLE (L2CR_L2E) | |
| 88 | ||
| 89 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 90 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
| 91 | #endif | |
| 92 | ||
| 93 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 94 | ||
| 6d0f6bcf JCPV |
95 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 96 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
| 97 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| c646bba6 JH |
98 | |
| 99 | /* | |
| 100 | * Base addresses -- Note these are effective addresses where the | |
| 101 | * actual resources get mapped (not physical addresses) | |
| 102 | */ | |
| 6d0f6bcf JCPV |
103 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 104 | #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ | |
| 105 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
| c646bba6 | 106 | |
| f698738e JL |
107 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 108 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
| ad19e7a5 | 109 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
| f698738e | 110 | |
| 6d0f6bcf JCPV |
111 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
| 112 | #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
| cca34967 | 113 | |
| c646bba6 JH |
114 | /* |
| 115 | * DDR Setup | |
| 116 | */ | |
| 6d0f6bcf JCPV |
117 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
| 118 | #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ | |
| 119 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 120 | #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 | |
| 1266df88 | 121 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| c646bba6 JH |
122 | #define CONFIG_VERY_BIG_RAM |
| 123 | ||
| 9bd4e591 KG |
124 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 125 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 126 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 127 | ||
| c646bba6 JH |
128 | #if defined(CONFIG_SPD_EEPROM) |
| 129 | /* | |
| 130 | * Determine DDR configuration from I2C interface. | |
| 131 | */ | |
| 132 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ | |
| 133 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ | |
| 134 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ | |
| 135 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ | |
| 136 | ||
| 137 | #else | |
| 138 | /* | |
| 139 | * Manually set up DDR1 & DDR2 parameters | |
| 140 | */ | |
| 141 | ||
| 6d0f6bcf JCPV |
142 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 143 | ||
| 144 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 145 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
| 146 | #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 | |
| 147 | #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 | |
| 148 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 | |
| 149 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
| 150 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 | |
| 151 | #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 | |
| 152 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 153 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 | |
| 154 | #define CONFIG_SYS_DDR_TIMING_1 0x38377322 | |
| 155 | #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 | |
| 156 | #define CONFIG_SYS_DDR_CFG_1A 0x43008008 | |
| 157 | #define CONFIG_SYS_DDR_CFG_2 0x24401000 | |
| 158 | #define CONFIG_SYS_DDR_MODE_1 0x23c00542 | |
| 159 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 160 | #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 | |
| 161 | #define CONFIG_SYS_DDR_INTERVAL 0x05080100 | |
| 162 | #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 | |
| 163 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 164 | #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 | |
| 165 | ||
| 166 | #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F | |
| 167 | #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 | |
| 168 | #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 | |
| 169 | #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 | |
| 170 | #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 | |
| 171 | #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 | |
| 172 | #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 | |
| 173 | #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 | |
| 174 | #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 | |
| 176 | #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 | |
| 177 | #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 | |
| 178 | #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 | |
| 179 | #define CONFIG_SYS_DDR2_CFG_2 0x24401000 | |
| 180 | #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 | |
| 181 | #define CONFIG_SYS_DDR2_MODE_2 0x00000000 | |
| 182 | #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 | |
| 183 | #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 | |
| 184 | #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 | |
| 185 | #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 | |
| 186 | #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 | |
| c646bba6 JH |
187 | |
| 188 | ||
| 189 | #endif | |
| 190 | ||
| 32628c50 | 191 | /* #define CONFIG_ID_EEPROM 1 |
| c646bba6 JH |
192 | #define ID_EEPROM_ADDR 0x57 */ |
| 193 | ||
| 194 | /* | |
| 195 | * The SBC8641D contains 16MB flash space at ff000000. | |
| 196 | */ | |
| 6d0f6bcf | 197 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| c646bba6 JH |
198 | |
| 199 | /* Flash */ | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ |
| 201 | #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ | |
| c646bba6 JH |
202 | |
| 203 | /* 64KB EEPROM */ | |
| 6d0f6bcf JCPV |
204 | #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ |
| 205 | #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ | |
| c646bba6 JH |
206 | |
| 207 | /* EPLD - User switches, board id, LEDs */ | |
| 6d0f6bcf JCPV |
208 | #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ |
| 209 | #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ | |
| c646bba6 JH |
210 | |
| 211 | /* Local bus SDRAM 128MB */ | |
| 6d0f6bcf JCPV |
212 | #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ |
| 213 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ | |
| 214 | #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ | |
| 215 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
216 | |
| 217 | /* Disk on Chip (DOC) 128MB */ | |
| 6d0f6bcf JCPV |
218 | #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ |
| 219 | #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
220 | |
| 221 | /* LCD */ | |
| 6d0f6bcf JCPV |
222 | #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ |
| 223 | #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
224 | |
| 225 | /* Control logic & misc peripherals */ | |
| 6d0f6bcf JCPV |
226 | #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ |
| 227 | #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 | 228 | |
| 6d0f6bcf JCPV |
229 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 230 | #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ | |
| c646bba6 | 231 | |
| 6d0f6bcf JCPV |
232 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 233 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 234 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 235 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| bf9a8c34 | 236 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
| c646bba6 | 237 | |
| 00b1883a | 238 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
239 | #define CONFIG_SYS_FLASH_CFI |
| 240 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
| 241 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 242 | #define CONFIG_SYS_FLASH_PROTECTION | |
| c646bba6 JH |
243 | |
| 244 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 245 | ||
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 247 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 248 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| c646bba6 | 249 | #else |
| 6d0f6bcf | 250 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| c646bba6 | 251 | #endif |
| 6d0f6bcf | 252 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
| c646bba6 | 253 | |
| 6d0f6bcf JCPV |
254 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 255 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 256 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| c646bba6 | 257 | |
| 6d0f6bcf JCPV |
258 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 259 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| c646bba6 JH |
260 | |
| 261 | /* Serial Port */ | |
| 262 | #define CONFIG_CONS_INDEX 1 | |
| 263 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
264 | #define CONFIG_SYS_NS16550 |
| 265 | #define CONFIG_SYS_NS16550_SERIAL | |
| 266 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 267 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| c646bba6 | 268 | |
| 6d0f6bcf | 269 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| c646bba6 JH |
270 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 271 | ||
| 6d0f6bcf JCPV |
272 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 273 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| c646bba6 JH |
274 | |
| 275 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
276 | #define CONFIG_SYS_HUSH_PARSER |
| 277 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 278 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| c646bba6 JH |
279 | #endif |
| 280 | ||
| 281 | /* | |
| 282 | * Pass open firmware flat tree to kernel | |
| 283 | */ | |
| 13f5433f JL |
284 | #define CONFIG_OF_LIBFDT 1 |
| 285 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 286 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| c646bba6 | 287 | |
| c646bba6 JH |
288 | /* |
| 289 | * I2C | |
| 290 | */ | |
| 291 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 292 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 293 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
294 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 295 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 296 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 297 | #define CONFIG_SYS_I2C_OFFSET 0x3100 | |
| c646bba6 JH |
298 | |
| 299 | /* | |
| 300 | * RapidIO MMU | |
| 301 | */ | |
| 6d0f6bcf JCPV |
302 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ |
| 303 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE | |
| 304 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
| c646bba6 JH |
305 | |
| 306 | /* | |
| 307 | * General PCI | |
| 308 | * Addresses are mapped 1-1. | |
| 309 | */ | |
| 79e436ca BB |
310 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 311 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
| 312 | #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS | |
| 6d0f6bcf | 313 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 79e436ca BB |
314 | #define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 |
| 315 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS | |
| 316 | #define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS | |
| 6d0f6bcf | 317 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ |
| c646bba6 | 318 | |
| 79e436ca BB |
319 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
| 320 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS | |
| 321 | #define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS | |
| 6d0f6bcf | 322 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
| 79e436ca BB |
323 | #define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 |
| 324 | #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS | |
| 325 | #define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS | |
| 6d0f6bcf | 326 | #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ |
| c646bba6 JH |
327 | |
| 328 | #if defined(CONFIG_PCI) | |
| 329 | ||
| 330 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 331 | ||
| 6d0f6bcf | 332 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
| c646bba6 JH |
333 | |
| 334 | #define CONFIG_NET_MULTI | |
| 53677ef1 | 335 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| c646bba6 JH |
336 | |
| 337 | #undef CONFIG_EEPRO100 | |
| 338 | #undef CONFIG_TULIP | |
| 339 | ||
| 340 | #if !defined(CONFIG_PCI_PNP) | |
| 341 | #define PCI_ENET0_IOADDR 0xe0000000 | |
| 342 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
| 53677ef1 | 343 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| c646bba6 JH |
344 | #endif |
| 345 | ||
| 346 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 347 | ||
| 348 | #define CONFIG_DOS_PARTITION | |
| 349 | #undef CONFIG_SCSI_AHCI | |
| 350 | ||
| 351 | #ifdef CONFIG_SCSI_AHCI | |
| 352 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
353 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 354 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 355 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 356 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| c646bba6 JH |
357 | #endif |
| 358 | ||
| 359 | #endif /* CONFIG_PCI */ | |
| 360 | ||
| 361 | #if defined(CONFIG_TSEC_ENET) | |
| 362 | ||
| 363 | #ifndef CONFIG_NET_MULTI | |
| 53677ef1 | 364 | #define CONFIG_NET_MULTI 1 |
| c646bba6 JH |
365 | #endif |
| 366 | ||
| 367 | /* #define CONFIG_MII 1 */ /* MII PHY management */ | |
| 368 | ||
| 369 | #define CONFIG_TSEC1 1 | |
| 370 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 371 | #define CONFIG_TSEC2 1 | |
| 372 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 373 | #define CONFIG_TSEC3 1 | |
| 374 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 375 | #define CONFIG_TSEC4 1 | |
| 376 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 377 | ||
| 378 | #define TSEC1_PHY_ADDR 0x1F | |
| 379 | #define TSEC2_PHY_ADDR 0x00 | |
| 380 | #define TSEC3_PHY_ADDR 0x01 | |
| 381 | #define TSEC4_PHY_ADDR 0x02 | |
| 382 | #define TSEC1_PHYIDX 0 | |
| 383 | #define TSEC2_PHYIDX 0 | |
| 384 | #define TSEC3_PHYIDX 0 | |
| 385 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
386 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 387 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 388 | #define TSEC3_FLAGS TSEC_GIGABIT | |
| 389 | #define TSEC4_FLAGS TSEC_GIGABIT | |
| c646bba6 | 390 | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ |
| c646bba6 JH |
392 | |
| 393 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 394 | ||
| 395 | #endif /* CONFIG_TSEC_ENET */ | |
| 396 | ||
| 397 | /* | |
| 398 | * BAT0 2G Cacheable, non-guarded | |
| 399 | * 0x0000_0000 2G DDR | |
| 400 | */ | |
| 6d0f6bcf JCPV |
401 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 402 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 403 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
| 404 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
| c646bba6 JH |
405 | |
| 406 | /* | |
| 407 | * BAT1 1G Cache-inhibited, guarded | |
| 408 | * 0x8000_0000 512M PCI-Express 1 Memory | |
| 409 | * 0xa000_0000 512M PCI-Express 2 Memory | |
| 410 | * Changed it for operating from 0xd0000000 | |
| 411 | */ | |
| 79e436ca | 412 | #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ |
| c646bba6 | 413 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 79e436ca BB |
414 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) |
| 415 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 416 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| c646bba6 JH |
417 | |
| 418 | /* | |
| 419 | * BAT2 512M Cache-inhibited, guarded | |
| 420 | * 0xc000_0000 512M RapidIO Memory | |
| 421 | */ | |
| 6d0f6bcf | 422 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ |
| c646bba6 | 423 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
424 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
| 425 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 426 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| c646bba6 JH |
427 | |
| 428 | /* | |
| 429 | * BAT3 4M Cache-inhibited, guarded | |
| 430 | * 0xf800_0000 4M CCSR | |
| 431 | */ | |
| 6d0f6bcf | 432 | #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ |
| c646bba6 | 433 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
434 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 435 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 436 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
| c646bba6 | 437 | |
| f698738e JL |
438 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 439 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 440 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 441 | | BATL_GUARDEDSTORAGE) | |
| 442 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 443 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 444 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 445 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 446 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 447 | #endif | |
| 448 | ||
| c646bba6 JH |
449 | /* |
| 450 | * BAT4 32M Cache-inhibited, guarded | |
| 451 | * 0xe200_0000 16M PCI-Express 1 I/O | |
| 452 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
| 453 | * Note that this is at 0xe0000000 | |
| 454 | */ | |
| 79e436ca | 455 | #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ |
| c646bba6 | 456 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 79e436ca BB |
457 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) |
| 458 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 459 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| c646bba6 JH |
460 | |
| 461 | /* | |
| 462 | * BAT5 128K Cacheable, non-guarded | |
| 463 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 464 | */ | |
| 6d0f6bcf JCPV |
465 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 466 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 467 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 468 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| c646bba6 JH |
469 | |
| 470 | /* | |
| 471 | * BAT6 32M Cache-inhibited, guarded | |
| 472 | * 0xfe00_0000 32M FLASH | |
| 473 | */ | |
| 6d0f6bcf | 474 | #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
| c646bba6 | 475 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
476 | #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
| 477 | #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 478 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
| c646bba6 | 479 | |
| bf9a8c34 BB |
480 | /* Map the last 1M of flash where we're running from reset */ |
| 481 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 482 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 483 | #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 484 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 485 | | BATL_MEMCOHERENCE) | |
| 486 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 487 | ||
| 6d0f6bcf JCPV |
488 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 489 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 490 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 491 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| c646bba6 JH |
492 | |
| 493 | /* | |
| 494 | * Environment | |
| 495 | */ | |
| 5a1aceb0 | 496 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 497 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 0e8d1586 JCPV |
498 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| 499 | #define CONFIG_ENV_SIZE 0x2000 | |
| c646bba6 JH |
500 | |
| 501 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 502 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| c646bba6 JH |
503 | |
| 504 | #include <config_cmd_default.h> | |
| 505 | #define CONFIG_CMD_PING | |
| 506 | #define CONFIG_CMD_I2C | |
| 4f93f8b1 | 507 | #define CONFIG_CMD_REGINFO |
| c646bba6 JH |
508 | |
| 509 | #if defined(CONFIG_PCI) | |
| 510 | #define CONFIG_CMD_PCI | |
| 511 | #endif | |
| 512 | ||
| 513 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 514 | ||
| 515 | /* | |
| 516 | * Miscellaneous configurable options | |
| 517 | */ | |
| 6d0f6bcf JCPV |
518 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 519 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 520 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| c646bba6 | 521 | |
| 30b52df9 | 522 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 523 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| c646bba6 | 524 | #else |
| 6d0f6bcf | 525 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| c646bba6 JH |
526 | #endif |
| 527 | ||
| 6d0f6bcf JCPV |
528 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 529 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 530 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 531 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| c646bba6 JH |
532 | |
| 533 | /* | |
| 534 | * For booting Linux, the board info and command line data | |
| 535 | * have to be in the first 8 MB of memory, since this is | |
| 536 | * the maximum mapped by the Linux kernel during initialization. | |
| 537 | */ | |
| 6d0f6bcf | 538 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| c646bba6 JH |
539 | |
| 540 | /* Cache Configuration */ | |
| 6d0f6bcf JCPV |
541 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 542 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 30b52df9 | 543 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 544 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| c646bba6 JH |
545 | #endif |
| 546 | ||
| 547 | /* | |
| 548 | * Internal Definitions | |
| 549 | * | |
| 550 | * Boot Flags | |
| 551 | */ | |
| 552 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 553 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 554 | ||
| 30b52df9 | 555 | #if defined(CONFIG_CMD_KGDB) |
| c646bba6 JH |
556 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 557 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 558 | #endif | |
| 559 | ||
| 560 | /* | |
| 561 | * Environment Configuration | |
| 562 | */ | |
| 563 | ||
| 564 | /* The mac addresses for all ethernet interface */ | |
| 565 | #if defined(CONFIG_TSEC_ENET) | |
| 566 | #define CONFIG_ETHADDR 02:E0:0C:00:00:01 | |
| 567 | #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD | |
| 568 | #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD | |
| 569 | #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD | |
| 570 | #endif | |
| 571 | ||
| 10327dc5 | 572 | #define CONFIG_HAS_ETH0 1 |
| c646bba6 JH |
573 | #define CONFIG_HAS_ETH1 1 |
| 574 | #define CONFIG_HAS_ETH2 1 | |
| 575 | #define CONFIG_HAS_ETH3 1 | |
| 576 | ||
| 577 | #define CONFIG_IPADDR 192.168.0.50 | |
| 578 | ||
| 579 | #define CONFIG_HOSTNAME sbc8641d | |
| 580 | #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx | |
| 581 | #define CONFIG_BOOTFILE uImage | |
| 582 | ||
| 583 | #define CONFIG_SERVERIP 192.168.0.2 | |
| 584 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 585 | #define CONFIG_NETMASK 255.255.255.0 | |
| 586 | ||
| 587 | /* default location for tftp and bootm */ | |
| 588 | #define CONFIG_LOADADDR 1000000 | |
| 589 | ||
| 590 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 591 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 592 | ||
| 593 | #define CONFIG_BAUDRATE 115200 | |
| 594 | ||
| 595 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 596 | "netdev=eth0\0" \ | |
| 597 | "consoledev=ttyS0\0" \ | |
| 598 | "ramdiskaddr=2000000\0" \ | |
| 599 | "ramdiskfile=uRamdisk\0" \ | |
| 600 | "dtbaddr=400000\0" \ | |
| 601 | "dtbfile=sbc8641d.dtb\0" \ | |
| 602 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
| 603 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
| 604 | "maxcpus=1" | |
| 605 | ||
| 606 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 607 | "setenv bootargs root=/dev/nfs rw " \ | |
| 608 | "nfsroot=$serverip:$rootpath " \ | |
| 609 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 610 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 611 | "tftp $loadaddr $bootfile;" \ | |
| 612 | "tftp $dtbaddr $dtbfile;" \ | |
| 613 | "bootm $loadaddr - $dtbaddr" | |
| 614 | ||
| 615 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 616 | "setenv bootargs root=/dev/ram rw " \ | |
| 617 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 618 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 619 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 620 | "tftp $loadaddr $bootfile;" \ | |
| 621 | "tftp $dtbaddr $dtbfile;" \ | |
| 622 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 623 | ||
| 624 | #define CONFIG_FLASHBOOTCOMMAND \ | |
| 625 | "setenv bootargs root=/dev/ram rw " \ | |
| 626 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 627 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 628 | "bootm ffd00000 ffb00000 ffa00000" | |
| 629 | ||
| 630 | #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND | |
| 631 | ||
| 632 | #endif /* __CONFIG_H */ |