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887e2ec9 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /************************************************************************ | |
26 | * sequoia.h - configuration for Sequoia board (PowerPC440EPx) | |
27 | ***********************************************************************/ | |
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /*----------------------------------------------------------------------- | |
32 | * High Level Configuration Options | |
33 | *----------------------------------------------------------------------*/ | |
854bc8da SR |
34 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
35 | #ifndef CONFIG_RAINIER | |
887e2ec9 SR |
36 | #define CONFIG_SEQUOIA 1 /* Board is Sequoia */ |
37 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
854bc8da SR |
38 | #else |
39 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ | |
40 | #endif | |
887e2ec9 SR |
41 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
43 | ||
44 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
45 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
46 | ||
47 | /*----------------------------------------------------------------------- | |
48 | * Base addresses -- Note these are effective addresses where the | |
49 | * actual resources get mapped (not physical addresses) | |
50 | *----------------------------------------------------------------------*/ | |
51 | #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ | |
52 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
53 | ||
54 | #define CFG_BOOT_BASE_ADDR 0xf0000000 | |
55 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
4ef62514 | 56 | #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ |
887e2ec9 SR |
57 | #define CFG_MONITOR_BASE TEXT_BASE |
58 | #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ | |
59 | #define CFG_OCM_BASE 0xe0010000 /* ocm */ | |
60 | #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
61 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
62 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
63 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
64 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
65 | ||
66 | /* Don't change either of these */ | |
67 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ | |
68 | ||
69 | #define CFG_USB2D0_BASE 0xe0000100 | |
70 | #define CFG_USB_DEVICE 0xe0000000 | |
71 | #define CFG_USB_HOST 0xe0000400 | |
72 | #define CFG_BCSR_BASE 0xc0000000 | |
73 | ||
74 | /*----------------------------------------------------------------------- | |
75 | * Initial RAM & stack pointer | |
76 | *----------------------------------------------------------------------*/ | |
887e2ec9 | 77 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
887e2ec9 SR |
78 | #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ |
79 | #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ | |
887e2ec9 SR |
80 | |
81 | #define CFG_INIT_RAM_END (4 << 10) | |
82 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
83 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
84 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
85 | ||
86 | /*----------------------------------------------------------------------- | |
87 | * Serial Port | |
88 | *----------------------------------------------------------------------*/ | |
89 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ | |
90 | #define CONFIG_BAUDRATE 115200 | |
91 | #define CONFIG_SERIAL_MULTI 1 | |
92 | /* define this if you want console on UART1 */ | |
93 | #undef CONFIG_UART1_CONSOLE | |
94 | ||
95 | #define CFG_BAUDRATE_TABLE \ | |
96 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
97 | ||
98 | /*----------------------------------------------------------------------- | |
99 | * Environment | |
100 | *----------------------------------------------------------------------*/ | |
d12ae808 | 101 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
887e2ec9 SR |
102 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
103 | #else | |
104 | #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ | |
d1a72545 | 105 | #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
887e2ec9 | 106 | #endif |
887e2ec9 SR |
107 | |
108 | /*----------------------------------------------------------------------- | |
109 | * FLASH related | |
110 | *----------------------------------------------------------------------*/ | |
111 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
112 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
113 | ||
114 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
115 | ||
116 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
117 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
118 | ||
119 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
120 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
121 | ||
122 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
123 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
124 | ||
125 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
126 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
127 | ||
128 | #ifdef CFG_ENV_IS_IN_FLASH | |
129 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
130 | #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) | |
131 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
132 | ||
133 | /* Address and size of Redundant Environment Sector */ | |
134 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
135 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
136 | #endif | |
137 | ||
887e2ec9 SR |
138 | /* |
139 | * IPL (Initial Program Loader, integrated inside CPU) | |
140 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
141 | * | |
142 | * SPL (Secondary Program Loader) | |
143 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
144 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
145 | * controller and the NAND controller so that the special U-Boot image can be | |
146 | * loaded from NAND to SDRAM. | |
147 | * | |
148 | * NUB (NAND U-Boot) | |
149 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
150 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
151 | * | |
152 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
153 | * set up. While still running from cache, I experienced problems accessing | |
154 | * the NAND controller. sr - 2006-08-25 | |
155 | */ | |
156 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ | |
157 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
158 | #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
159 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
160 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
161 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) | |
162 | ||
163 | /* | |
164 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
165 | */ | |
166 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ | |
167 | #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
168 | ||
169 | /* | |
170 | * Now the NAND chip has to be defined (no autodetection used!) | |
171 | */ | |
172 | #define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ | |
173 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
174 | #define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ | |
175 | #define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ | |
176 | #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
177 | ||
178 | #ifdef CFG_ENV_IS_IN_NAND | |
d12ae808 SR |
179 | /* |
180 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
181 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
182 | */ | |
183 | #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE | |
184 | #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) | |
887e2ec9 SR |
185 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) |
186 | #endif | |
187 | ||
188 | /*----------------------------------------------------------------------- | |
189 | * DDR SDRAM | |
190 | *----------------------------------------------------------------------*/ | |
02388983 SR |
191 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ |
192 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
193 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ | |
194 | #endif | |
887e2ec9 SR |
195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * I2C | |
198 | *----------------------------------------------------------------------*/ | |
199 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
200 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
201 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
202 | #define CFG_I2C_SLAVE 0x7F | |
203 | ||
204 | #define CFG_I2C_MULTI_EEPROMS | |
205 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) | |
206 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
207 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
208 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
209 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
210 | ||
887e2ec9 SR |
211 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
212 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
213 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
214 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
215 | #define CFG_DTT_MAX_TEMP 70 | |
216 | #define CFG_DTT_LOW_TEMP -30 | |
217 | #define CFG_DTT_HYSTERESIS 3 | |
218 | ||
219 | #define CONFIG_PREBOOT "echo;" \ | |
220 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
221 | "echo" | |
222 | ||
223 | #undef CONFIG_BOOTARGS | |
224 | ||
225 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
226 | "netdev=eth0\0" \ | |
227 | "hostname=sequoia\0" \ | |
228 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
229 | "nfsroot=${serverip}:${rootpath}\0" \ | |
230 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
231 | "addip=setenv bootargs ${bootargs} " \ | |
232 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
233 | ":${hostname}:${netdev}:off panic=1\0" \ | |
234 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
235 | "flash_nfs=run nfsargs addip addtty;" \ | |
236 | "bootm ${kernel_addr}\0" \ | |
237 | "flash_self=run ramargs addip addtty;" \ | |
238 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
239 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
240 | "bootm\0" \ | |
4ef62514 | 241 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ |
887e2ec9 | 242 | "bootfile=/tftpboot/sequoia/uImage\0" \ |
4ef62514 SR |
243 | "kernel_addr=FC000000\0" \ |
244 | "ramdisk_addr=FC180000\0" \ | |
887e2ec9 SR |
245 | "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ |
246 | "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ | |
247 | "cp.b 100000 FFFA0000 60000\0" \ | |
248 | "upd=run load;run update\0" \ | |
249 | "" | |
250 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
251 | ||
252 | #if 0 | |
253 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
254 | #else | |
255 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
256 | #endif | |
257 | ||
258 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
259 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
260 | ||
261 | #define CONFIG_M88E1111_PHY 1 | |
262 | #define CONFIG_IBM_EMAC4_V4 1 | |
263 | #define CONFIG_MII 1 /* MII PHY management */ | |
264 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ | |
265 | ||
266 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
267 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
268 | ||
269 | #define CONFIG_HAS_ETH0 | |
270 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
271 | ||
272 | #define CONFIG_NET_MULTI 1 | |
273 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
274 | #define CONFIG_PHY1_ADDR 1 | |
275 | ||
276 | /* USB */ | |
854bc8da | 277 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
278 | #define CONFIG_USB_OHCI |
279 | #define CONFIG_USB_STORAGE | |
280 | ||
281 | /* Comment this out to enable USB 1.1 device */ | |
282 | #define USB_2_0_DEVICE | |
283 | ||
854bc8da SR |
284 | #define CMD_USB CFG_CMD_USB |
285 | #else | |
286 | #define CMD_USB 0 /* no USB on 440GRx */ | |
287 | #endif /* CONFIG_440EPX */ | |
288 | ||
887e2ec9 SR |
289 | /* Partitions */ |
290 | #define CONFIG_MAC_PARTITION | |
291 | #define CONFIG_DOS_PARTITION | |
292 | #define CONFIG_ISO_PARTITION | |
293 | ||
294 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
295 | CFG_CMD_ASKENV | \ | |
296 | CFG_CMD_DHCP | \ | |
297 | CFG_CMD_DTT | \ | |
298 | CFG_CMD_DIAG | \ | |
299 | CFG_CMD_EEPROM | \ | |
300 | CFG_CMD_ELF | \ | |
301 | CFG_CMD_FAT | \ | |
302 | CFG_CMD_I2C | \ | |
303 | CFG_CMD_IRQ | \ | |
304 | CFG_CMD_MII | \ | |
305 | CFG_CMD_NAND | \ | |
306 | CFG_CMD_NET | \ | |
307 | CFG_CMD_NFS | \ | |
308 | CFG_CMD_PCI | \ | |
309 | CFG_CMD_PING | \ | |
310 | CFG_CMD_REGINFO | \ | |
311 | CFG_CMD_SDRAM | \ | |
854bc8da | 312 | CMD_USB) |
887e2ec9 SR |
313 | |
314 | #define CONFIG_SUPPORT_VFAT | |
315 | ||
316 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
317 | #include <cmd_confdefs.h> | |
318 | ||
319 | /*----------------------------------------------------------------------- | |
320 | * Miscellaneous configurable options | |
321 | *----------------------------------------------------------------------*/ | |
322 | #define CFG_LONGHELP /* undef to save memory */ | |
323 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
324 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
325 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
326 | #else | |
327 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
328 | #endif | |
329 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
330 | #define CFG_MAXARGS 16 /* max number of command args */ | |
331 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
332 | ||
333 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
334 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
335 | ||
336 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
337 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
338 | ||
339 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
340 | ||
341 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
342 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
343 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
344 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
345 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
346 | ||
347 | /*----------------------------------------------------------------------- | |
348 | * PCI stuff | |
349 | *----------------------------------------------------------------------*/ | |
350 | /* General PCI */ | |
351 | #define CONFIG_PCI /* include pci support */ | |
352 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
353 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
354 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ | |
355 | ||
356 | /* Board-specific PCI */ | |
357 | #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ | |
358 | #define CFG_PCI_TARGET_INIT | |
359 | #define CFG_PCI_MASTER_INIT | |
360 | ||
361 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
362 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
363 | ||
364 | /* | |
365 | * For booting Linux, the board info and command line data | |
366 | * have to be in the first 8 MB of memory, since this is | |
367 | * the maximum mapped by the Linux kernel during initialization. | |
368 | */ | |
369 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
370 | ||
371 | /*----------------------------------------------------------------------- | |
372 | * External Bus Controller (EBC) Setup | |
373 | *----------------------------------------------------------------------*/ | |
374 | #define CFG_FLASH CFG_FLASH_BASE | |
375 | #define CFG_NAND 0xD0000000 | |
376 | #define CFG_CPLD 0xC0000000 | |
377 | ||
378 | /* | |
379 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
380 | */ | |
381 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
382 | #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ | |
383 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
384 | #define CFG_EBC_PB0AP 0x03017300 | |
4ef62514 | 385 | #define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) |
887e2ec9 SR |
386 | |
387 | /* Memory Bank 3 (NAND-FLASH) initialization */ | |
388 | #define CFG_EBC_PB3AP 0x018003c0 | |
389 | #define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) | |
390 | #else | |
391 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ | |
392 | /* Memory Bank 3 (NOR-FLASH) initialization */ | |
393 | #define CFG_EBC_PB3AP 0x03017300 | |
4ef62514 | 394 | #define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) |
887e2ec9 SR |
395 | |
396 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
397 | #define CFG_EBC_PB0AP 0x018003c0 | |
398 | #define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) | |
399 | #endif | |
400 | ||
401 | /* Memory Bank 2 (CPLD) initialization */ | |
402 | #define CFG_EBC_PB2AP 0x24814580 | |
403 | #define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) | |
404 | ||
43a2b0e7 SR |
405 | /*----------------------------------------------------------------------- |
406 | * NAND FLASH | |
407 | *----------------------------------------------------------------------*/ | |
408 | #define CFG_MAX_NAND_DEVICE 1 | |
409 | #define NAND_MAX_CHIPS 1 | |
410 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) | |
411 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
412 | ||
887e2ec9 SR |
413 | /*----------------------------------------------------------------------- |
414 | * Cache Configuration | |
415 | *----------------------------------------------------------------------*/ | |
416 | #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ | |
417 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
418 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
419 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
420 | #endif | |
421 | ||
422 | /* | |
423 | * Internal Definitions | |
424 | * | |
425 | * Boot Flags | |
426 | */ | |
427 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
428 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
429 | ||
430 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
431 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
432 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
433 | #endif | |
434 | #endif /* __CONFIG_H */ |