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7faddaec NI |
1 | /* |
2 | * Configuation settings for the Renesas SH7763RDP board | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __SH7763RDP_H | |
27 | #define __SH7763RDP_H | |
28 | ||
29 | #define CONFIG_SH 1 | |
30 | #define CONFIG_SH4 1 | |
31 | #define CONFIG_CPU_SH7763 1 | |
32 | #define CONFIG_SH7763RDP 1 | |
33 | #define __LITTLE_ENDIAN 1 | |
34 | ||
35 | /* | |
36 | * Command line configuration. | |
37 | */ | |
38 | #define CONFIG_CMD_SDRAM | |
39 | #define CONFIG_CMD_FLASH | |
40 | #define CONFIG_CMD_MEMORY | |
ba932445 NI |
41 | #define CONFIG_CMD_NET |
42 | #define CONFIG_CMD_PING | |
bdab39d3 | 43 | #define CONFIG_CMD_SAVEENV |
ba932445 NI |
44 | #define CONFIG_CMD_NFS |
45 | #define CONFIG_CMD_JFFS2 | |
7faddaec NI |
46 | |
47 | #define CONFIG_BOOTDELAY -1 | |
48 | #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" | |
49 | #define CONFIG_ENV_OVERWRITE 1 | |
50 | ||
51 | #define CONFIG_VERSION_VARIABLE | |
52 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
53 | ||
54 | /* SCIF */ | |
6c58a030 | 55 | #define CONFIG_SCIF_CONSOLE 1 |
7faddaec NI |
56 | #define CONFIG_BAUDRATE 115200 |
57 | #define CONFIG_CONS_SCIF2 1 | |
58 | ||
00cb2e32 | 59 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
61 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
62 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ | |
63 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
64 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
65 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments | |
7faddaec | 66 | passed to kernel */ |
6d0f6bcf | 67 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate |
7faddaec NI |
68 | settings for this board */ |
69 | ||
7faddaec | 70 | /* SDRAM */ |
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
72 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
73 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
74 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
7faddaec NI |
75 | |
76 | /* Flash(NOR) */ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
78 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) | |
79 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
80 | #define CONFIG_SYS_MAX_FLASH_SECT (520) | |
7faddaec NI |
81 | |
82 | /* U-boot setting */ | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
84 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
85 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
7faddaec | 86 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 87 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 88 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
7faddaec | 89 | |
6d0f6bcf | 90 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 91 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
92 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
93 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
7faddaec | 94 | /* Timeout for Flash erase operations (in ms) */ |
6d0f6bcf | 95 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
7faddaec | 96 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 97 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
7faddaec | 98 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 99 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
7faddaec | 100 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 101 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
7faddaec | 102 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
6d0f6bcf JCPV |
103 | #undef CONFIG_SYS_FLASH_PROTECTION |
104 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
5a1aceb0 | 105 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
106 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
107 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
108 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
109 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
110 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 111 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6d0f6bcf | 112 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
7faddaec NI |
113 | |
114 | /* Clock */ | |
115 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
be45c632 | 116 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
8dd29c87 | 117 | #define CONFIG_SYS_HZ 1000 |
7faddaec | 118 | |
ba932445 NI |
119 | /* Ether */ |
120 | #define CONFIG_SH_ETHER 1 | |
121 | #define CONFIG_SH_ETHER_USE_PORT (1) | |
122 | #define CONFIG_SH_ETHER_PHY_ADDR (0x01) | |
123 | ||
7faddaec | 124 | #endif /* __SH7763RDP_H */ |