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Commit | Line | Data |
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7faddaec NI |
1 | /* |
2 | * Configuation settings for the Renesas SH7763RDP board | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
7faddaec NI |
8 | */ |
9 | ||
10 | #ifndef __SH7763RDP_H | |
11 | #define __SH7763RDP_H | |
12 | ||
7faddaec | 13 | #define CONFIG_CPU_SH7763 1 |
7faddaec NI |
14 | #define __LITTLE_ENDIAN 1 |
15 | ||
7faddaec NI |
16 | #define CONFIG_ENV_OVERWRITE 1 |
17 | ||
18a40e84 | 18 | #define CONFIG_DISPLAY_BOARDINFO |
7faddaec NI |
19 | #undef CONFIG_SHOW_BOOT_PROGRESS |
20 | ||
21 | /* SCIF */ | |
7faddaec NI |
22 | #define CONFIG_CONS_SCIF2 1 |
23 | ||
00cb2e32 | 24 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 25 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf | 26 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
6d0f6bcf | 27 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate |
7faddaec NI |
28 | settings for this board */ |
29 | ||
7faddaec | 30 | /* SDRAM */ |
6d0f6bcf JCPV |
31 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
32 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
33 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
34 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
7faddaec NI |
35 | |
36 | /* Flash(NOR) */ | |
6d0f6bcf JCPV |
37 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
38 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) | |
39 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
40 | #define CONFIG_SYS_MAX_FLASH_SECT (520) | |
7faddaec | 41 | |
a187559e | 42 | /* U-Boot setting */ |
6d0f6bcf JCPV |
43 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
44 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
45 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
7faddaec | 46 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 47 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 48 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
7faddaec | 49 | |
6d0f6bcf | 50 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 51 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
52 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
53 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
7faddaec | 54 | /* Timeout for Flash erase operations (in ms) */ |
6d0f6bcf | 55 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
7faddaec | 56 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 57 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
7faddaec | 58 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 59 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
7faddaec | 60 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 61 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
7faddaec | 62 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
6d0f6bcf JCPV |
63 | #undef CONFIG_SYS_FLASH_PROTECTION |
64 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
0e8d1586 JCPV |
65 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
66 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
67 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
68 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
69 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 70 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6d0f6bcf | 71 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
7faddaec NI |
72 | |
73 | /* Clock */ | |
74 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
684a501e NI |
75 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
76 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 77 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
7faddaec | 78 | |
ba932445 | 79 | /* Ether */ |
ba932445 NI |
80 | #define CONFIG_SH_ETHER_USE_PORT (1) |
81 | #define CONFIG_SH_ETHER_PHY_ADDR (0x01) | |
c8ceca95 YS |
82 | #define CONFIG_BITBANGMII |
83 | #define CONFIG_BITBANGMII_MULTI | |
a80a6619 | 84 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
ba932445 | 85 | |
7faddaec | 86 | #endif /* __SH7763RDP_H */ |