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5d108ac8 SP |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
4 | * | |
5 | * Wolfgang Denk <wd@denx.de> | |
6 | * Copyright 2004 Freescale Semiconductor. | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * Socrates | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
e99b607a | 36 | /* new uImage format support */ |
37 | #define CONFIG_FIT 1 | |
38 | #define CONFIG_OF_LIBFDT 1 | |
39 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
40 | ||
5d108ac8 SP |
41 | /* High Level Configuration Options */ |
42 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
43 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
44 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
45 | #define CONFIG_MPC8544 1 | |
46 | #define CONFIG_SOCRATES 1 | |
47 | ||
48 | #define CONFIG_PCI | |
49 | ||
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
51 | ||
52 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
3e79b588 | 53 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ |
5d108ac8 SP |
54 | |
55 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
56 | ||
57 | /* | |
58 | * Only possible on E500 Version 2 or newer cores. | |
59 | */ | |
60 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
61 | ||
62 | /* | |
63 | * sysclk for MPC85xx | |
64 | * | |
65 | * Two valid values are: | |
66 | * 33000000 | |
67 | * 66000000 | |
68 | * | |
69 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
70 | * is likely the desired value here, so that is now the default. | |
71 | * The board, however, can run at 66MHz. In any event, this value | |
72 | * must match the settings of some switches. Details can be found | |
73 | * in the README.mpc85xxads. | |
74 | */ | |
75 | ||
76 | #ifndef CONFIG_SYS_CLK_FREQ | |
77 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
78 | #endif | |
79 | ||
80 | /* | |
81 | * These can be toggled for performance analysis, otherwise use default. | |
82 | */ | |
83 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
84 | #define CONFIG_BTB /* toggle branch predition */ | |
5d108ac8 | 85 | |
6d0f6bcf | 86 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
5d108ac8 | 87 | |
6d0f6bcf JCPV |
88 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
89 | #define CONFIG_SYS_MEMTEST_START 0x00400000 | |
90 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 | |
5d108ac8 SP |
91 | |
92 | /* | |
93 | * Base addresses -- Note these are effective addresses where the | |
94 | * actual resources get mapped (not physical addresses) | |
95 | */ | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ |
97 | #define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ | |
98 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
99 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
5d108ac8 | 100 | |
be0bd823 KG |
101 | /* DDR Setup */ |
102 | #define CONFIG_FSL_DDR2 | |
103 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
104 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
105 | #define CONFIG_DDR_SPD | |
106 | ||
107 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
108 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
109 | ||
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
111 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
be0bd823 KG |
112 | #define CONFIG_VERY_BIG_RAM |
113 | ||
114 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
115 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
116 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
117 | ||
118 | /* I2C addresses of SPD EEPROMs */ | |
562788b0 | 119 | #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ |
5d108ac8 SP |
120 | |
121 | #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ | |
122 | ||
123 | /* Hardcoded values, to use instead of SPD */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
125 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 | |
126 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
127 | #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 | |
128 | #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 | |
129 | #define CONFIG_SYS_DDR_MODE 0x00480432 | |
130 | #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 | |
131 | #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 | |
132 | #define CONFIG_SYS_DDR_CONFIG 0xC3008000 | |
133 | #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 | |
134 | #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ | |
5d108ac8 | 135 | |
5d108ac8 SP |
136 | /* |
137 | * Flash on the LocalBus | |
138 | */ | |
6d0f6bcf | 139 | #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
5d108ac8 | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_FLASH0 0xFE000000 |
142 | #define CONFIG_SYS_FLASH1 0xFC000000 | |
143 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
5d108ac8 | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ |
146 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ | |
5d108ac8 | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ |
149 | #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ | |
150 | #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ | |
151 | #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ | |
5d108ac8 | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
00b1883a | 154 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
5d108ac8 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
157 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
158 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
159 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
160 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5d108ac8 | 161 | |
6d0f6bcf | 162 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
5d108ac8 | 163 | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
165 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
166 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
167 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ | |
5d108ac8 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
170 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
171 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ | |
5d108ac8 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/ |
174 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
175 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
5d108ac8 | 176 | |
47106ce1 | 177 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ |
6d0f6bcf | 178 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ |
3e79b588 DZ |
179 | |
180 | /* FPGA and NAND */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_FPGA_BASE 0xc0000000 |
182 | #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ | |
183 | #define CONFIG_SYS_HMI_BASE 0xc0010000 | |
184 | #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ | |
185 | #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ | |
186 | ||
187 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) | |
188 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
3e79b588 | 189 | #define CONFIG_CMD_NAND |
5d108ac8 | 190 | |
e64987a8 | 191 | /* LIME GDC */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_LIME_BASE 0xc8000000 |
193 | #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ | |
194 | #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ | |
195 | #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ | |
e64987a8 AG |
196 | |
197 | #define CONFIG_VIDEO | |
198 | #define CONFIG_VIDEO_MB862xx | |
5d16ca87 | 199 | #define CONFIG_VIDEO_MB862xx_ACCEL |
e64987a8 AG |
200 | #define CONFIG_CFB_CONSOLE |
201 | #define CONFIG_VIDEO_LOGO | |
202 | #define CONFIG_VIDEO_BMP_LOGO | |
203 | #define CONFIG_CONSOLE_EXTRA_INFO | |
204 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
229b6dce | 205 | #define VIDEO_FB_16BPP_WORD_SWAP |
e64987a8 | 206 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
6d0f6bcf | 207 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
e64987a8 AG |
208 | #define CONFIG_VIDEO_SW_CURSOR |
209 | #define CONFIG_SPLASH_SCREEN | |
210 | #define CONFIG_VIDEO_BMP_GZIP | |
6d0f6bcf | 211 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ |
e64987a8 | 212 | |
c28d3bbe WG |
213 | /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ |
214 | #define CONFIG_SYS_MB862xx_CCF 0x10000 | |
215 | /* SDRAM parameter */ | |
216 | #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 | |
217 | ||
5d108ac8 SP |
218 | /* Serial Port */ |
219 | ||
220 | #define CONFIG_CONS_INDEX 1 | |
221 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_NS16550 |
223 | #define CONFIG_SYS_NS16550_SERIAL | |
224 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
225 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5d108ac8 | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
228 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
5d108ac8 SP |
229 | |
230 | #define CONFIG_BAUDRATE 115200 | |
231 | ||
6d0f6bcf | 232 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5d108ac8 SP |
233 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
234 | ||
235 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5be58f5f | 236 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
238 | #ifdef CONFIG_SYS_HUSH_PARSER | |
239 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
5d108ac8 SP |
240 | #endif |
241 | ||
242 | ||
243 | /* | |
244 | * I2C | |
245 | */ | |
246 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
247 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
248 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */ |
250 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
251 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
5d108ac8 | 252 | |
3e79b588 | 253 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf | 254 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
3e79b588 | 255 | |
5d108ac8 | 256 | /* I2C RTC */ |
e18575d5 | 257 | #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ |
6d0f6bcf | 258 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ |
5d108ac8 | 259 | |
e64987a8 | 260 | /* I2C W83782G HW-Monitoring IC */ |
6d0f6bcf | 261 | #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ |
e64987a8 | 262 | |
2f7468ae SP |
263 | /* I2C temp sensor */ |
264 | /* Socrates uses Maxim's DS75, which is compatible with LM75 */ | |
265 | #define CONFIG_DTT_LM75 1 | |
266 | #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ | |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_DTT_MAX_TEMP 125 |
268 | #define CONFIG_SYS_DTT_LOW_TEMP -55 | |
269 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
270 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
2f7468ae | 271 | |
5d108ac8 SP |
272 | /* |
273 | * General PCI | |
274 | * Memory space is mapped 1-1. | |
275 | */ | |
6d0f6bcf | 276 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
5d108ac8 | 277 | |
5e1882df SP |
278 | /* PCI is clocked by the external source at 33 MHz */ |
279 | #define CONFIG_PCI_CLK_FREQ 33000000 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
281 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
282 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
283 | #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 | |
284 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
285 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
5d108ac8 SP |
286 | |
287 | #if defined(CONFIG_PCI) | |
5d108ac8 | 288 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d39e6851 | 289 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
5d108ac8 SP |
290 | #endif /* CONFIG_PCI */ |
291 | ||
292 | ||
293 | #define CONFIG_NET_MULTI 1 | |
294 | #define CONFIG_MII 1 /* MII PHY management */ | |
295 | #define CONFIG_TSEC1 1 | |
296 | #define CONFIG_TSEC1_NAME "TSEC0" | |
2f845dc2 SP |
297 | #define CONFIG_TSEC3 1 |
298 | #define CONFIG_TSEC3_NAME "TSEC1" | |
5d108ac8 SP |
299 | #undef CONFIG_MPC85XX_FEC |
300 | ||
301 | #define TSEC1_PHY_ADDR 0 | |
2f845dc2 | 302 | #define TSEC3_PHY_ADDR 1 |
5d108ac8 SP |
303 | |
304 | #define TSEC1_PHYIDX 0 | |
2f845dc2 | 305 | #define TSEC3_PHYIDX 0 |
5d108ac8 | 306 | #define TSEC1_FLAGS TSEC_GIGABIT |
2f845dc2 | 307 | #define TSEC3_FLAGS TSEC_GIGABIT |
5d108ac8 | 308 | |
2f845dc2 | 309 | /* Options are: TSEC[0,1] */ |
5d108ac8 SP |
310 | #define CONFIG_ETHPRIME "TSEC0" |
311 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
312 | ||
e18575d5 SP |
313 | #define CONFIG_HAS_ETH0 |
314 | #define CONFIG_HAS_ETH1 | |
315 | ||
5d108ac8 SP |
316 | /* |
317 | * Environment | |
318 | */ | |
5a1aceb0 | 319 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 320 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
6d0f6bcf | 321 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
322 | #define CONFIG_ENV_SIZE 0x4000 |
323 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
324 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5d108ac8 SP |
325 | |
326 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 327 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5d108ac8 SP |
328 | |
329 | #define CONFIG_TIMESTAMP /* Print image info with ts */ | |
330 | ||
331 | ||
332 | /* | |
333 | * BOOTP options | |
334 | */ | |
335 | #define CONFIG_BOOTP_BOOTFILESIZE | |
336 | #define CONFIG_BOOTP_BOOTPATH | |
337 | #define CONFIG_BOOTP_GATEWAY | |
338 | #define CONFIG_BOOTP_HOSTNAME | |
339 | ||
340 | ||
341 | /* | |
342 | * Command line configuration. | |
343 | */ | |
344 | #include <config_cmd_default.h> | |
345 | ||
47106ce1 | 346 | #define CONFIG_CMD_BMP |
5d108ac8 SP |
347 | #define CONFIG_CMD_DATE |
348 | #define CONFIG_CMD_DHCP | |
2f7468ae | 349 | #define CONFIG_CMD_DTT |
5d108ac8 | 350 | #undef CONFIG_CMD_EEPROM |
47106ce1 | 351 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
5d108ac8 | 352 | #define CONFIG_CMD_I2C |
3e79b588 | 353 | #define CONFIG_CMD_SDRAM |
5d108ac8 | 354 | #define CONFIG_CMD_MII |
47106ce1 | 355 | #undef CONFIG_CMD_NFS |
5d108ac8 | 356 | #define CONFIG_CMD_PING |
5d108ac8 | 357 | #define CONFIG_CMD_SNTP |
791e1dba | 358 | #define CONFIG_CMD_USB |
199e262e | 359 | #define CONFIG_CMD_REGINFO |
5d108ac8 SP |
360 | |
361 | #if defined(CONFIG_PCI) | |
362 | #define CONFIG_CMD_PCI | |
363 | #endif | |
364 | ||
5d108ac8 SP |
365 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
366 | ||
367 | /* | |
368 | * Miscellaneous configurable options | |
369 | */ | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
371 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
372 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5d108ac8 SP |
373 | |
374 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 375 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5d108ac8 | 376 | #else |
6d0f6bcf | 377 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5d108ac8 SP |
378 | #endif |
379 | ||
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ |
381 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
382 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
383 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
5d108ac8 SP |
384 | |
385 | /* | |
386 | * For booting Linux, the board info and command line data | |
387 | * have to be in the first 8 MB of memory, since this is | |
388 | * the maximum mapped by the Linux kernel during initialization. | |
389 | */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5d108ac8 SP |
391 | |
392 | /* | |
393 | * Internal Definitions | |
394 | * | |
395 | * Boot Flags | |
396 | */ | |
397 | #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ | |
398 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
399 | ||
400 | #if defined(CONFIG_CMD_KGDB) | |
401 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ | |
402 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
403 | #endif | |
404 | ||
405 | ||
406 | #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ | |
407 | ||
3e79b588 | 408 | #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ |
5d108ac8 SP |
409 | |
410 | #define CONFIG_PREBOOT "echo;" \ | |
3e79b588 | 411 | "echo Welcome on the ABB Socrates Board;" \ |
5d108ac8 SP |
412 | "echo" |
413 | ||
414 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
415 | ||
416 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5d108ac8 SP |
417 | "netdev=eth0\0" \ |
418 | "consdev=ttyS0\0" \ | |
3e79b588 DZ |
419 | "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ |
420 | "bootfile=/home/tftp/syscon3/uImage\0" \ | |
421 | "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ | |
422 | "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ | |
423 | "uboot_addr=FFFA0000\0" \ | |
424 | "kernel_addr=FE000000\0" \ | |
425 | "fdt_addr=FE1E0000\0" \ | |
426 | "ramdisk_addr=FE200000\0" \ | |
427 | "fdt_addr_r=B00000\0" \ | |
428 | "kernel_addr_r=200000\0" \ | |
429 | "ramdisk_addr_r=400000\0" \ | |
430 | "rootpath=/opt/eldk/ppc_85xxDP\0" \ | |
431 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
5d108ac8 SP |
432 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
433 | "nfsroot=$serverip:$rootpath\0" \ | |
3e79b588 DZ |
434 | "addcons=setenv bootargs $bootargs " \ |
435 | "console=$consdev,$baudrate\0" \ | |
5d108ac8 SP |
436 | "addip=setenv bootargs $bootargs " \ |
437 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
438 | ":$hostname:$netdev:off panic=1\0" \ | |
3e79b588 | 439 | "boot_nor=run ramargs addcons;" \ |
e18575d5 | 440 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
e18575d5 SP |
441 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ |
442 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
443 | "run nfsargs addip addcons;" \ | |
444 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
3e79b588 DZ |
445 | "update_uboot=tftp 100000 ${uboot_file};" \ |
446 | "protect off fffa0000 ffffffff;" \ | |
447 | "era fffa0000 ffffffff;" \ | |
448 | "cp.b 100000 fffa0000 ${filesize};" \ | |
449 | "setenv filesize;saveenv\0" \ | |
450 | "update_kernel=tftp 100000 ${bootfile};" \ | |
451 | "era fe000000 fe1dffff;" \ | |
452 | "cp.b 100000 fe000000 ${filesize};" \ | |
5d108ac8 | 453 | "setenv filesize;saveenv\0" \ |
3e79b588 DZ |
454 | "update_fdt=tftp 100000 ${fdt_file};" \ |
455 | "era fe1e0000 fe1fffff;" \ | |
456 | "cp.b 100000 fe1e0000 ${filesize};" \ | |
457 | "setenv filesize;saveenv\0" \ | |
458 | "update_initrd=tftp 100000 ${initrd_file};" \ | |
459 | "era fe200000 fe9fffff;" \ | |
460 | "cp.b 100000 fe200000 ${filesize};" \ | |
461 | "setenv filesize;saveenv\0" \ | |
462 | "clean_data=era fea00000 fff5ffff\0" \ | |
463 | "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ | |
464 | "load_usb=usb start;" \ | |
465 | "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ | |
466 | "boot_usb=run load_usb usbargs addcons;" \ | |
467 | "bootm ${kernel_addr_r} - ${fdt_addr};" \ | |
468 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
5d108ac8 | 469 | "" |
3e79b588 | 470 | #define CONFIG_BOOTCOMMAND "run boot_nor" |
5d108ac8 | 471 | |
e18575d5 SP |
472 | /* pass open firmware flat tree */ |
473 | #define CONFIG_OF_LIBFDT 1 | |
474 | #define CONFIG_OF_BOARD_SETUP 1 | |
475 | ||
791e1dba SP |
476 | /* USB support */ |
477 | #define CONFIG_USB_OHCI_NEW 1 | |
478 | #define CONFIG_PCI_OHCI 1 | |
479 | #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ | |
e90fb6af | 480 | #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
482 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
483 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
791e1dba SP |
484 | #define CONFIG_DOS_PARTITION 1 |
485 | #define CONFIG_USB_STORAGE 1 | |
486 | ||
5d108ac8 | 487 | #endif /* __CONFIG_H */ |