]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/sunxi-common.h
MIPS: add BMIPS Netgear CG3100D board
[people/ms/u-boot.git] / include / configs / sunxi-common.h
CommitLineData
cba69eee
IC
1/*
2 * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Configuration settings for the Allwinner sunxi series of boards.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef _SUNXI_COMMON_CONFIG_H
14#define _SUNXI_COMMON_CONFIG_H
15
daf6d399 16#include <asm/arch/cpu.h>
e049fe28
HG
17#include <linux/stringify.h>
18
77ef1369
SS
19#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
20/*
21 * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
22 * expense of restricting some features, so the regular machine id values can
23 * be used.
24 */
25# define CONFIG_MACH_TYPE_COMPAT_REV 0
26#else
27/*
28 * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
29 * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
30 * beyond the machine id check.
31 */
32# define CONFIG_MACH_TYPE_COMPAT_REV 1
33#endif
34
d29adf8e
AP
35#ifdef CONFIG_ARM64
36#define CONFIG_BUILD_TARGET "u-boot.itb"
37#endif
38
cba69eee 39/* Serial & console */
cba69eee
IC
40#define CONFIG_SYS_NS16550_SERIAL
41/* ns16550 reg in the low bits of cpu reg */
cba69eee 42#define CONFIG_SYS_NS16550_CLK 24000000
4fb60552 43#ifndef CONFIG_DM_SERIAL
1a81cf83
SG
44# define CONFIG_SYS_NS16550_REG_SIZE -4
45# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
46# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
47# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
48# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
49# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
50#endif
cba69eee 51
8a65f69c 52/* CPU */
e4916e85 53#define COUNTER_FREQUENCY 24000000
8a65f69c 54
e049fe28
HG
55/*
56 * The DRAM Base differs between some models. We cannot use macros for the
57 * CONFIG_FOO defines which contain the DRAM base address since they end
58 * up unexpanded in include/autoconf.mk .
59 *
60 * So we have to have this #ifdef #else #endif block for these.
61 */
62#ifdef CONFIG_MACH_SUN9I
63#define SDRAM_OFFSET(x) 0x2##x
64#define CONFIG_SYS_SDRAM_BASE 0x20000000
65#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
66#define CONFIG_SYS_TEXT_BASE 0x2a000000
ff42d107
HG
67/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
68 * since it needs to fit in with the other values. By also #defining it
69 * we get warnings if the Kconfig value mismatches. */
70#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
e049fe28
HG
71#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
72#else
73#define SDRAM_OFFSET(x) 0x4##x
cba69eee 74#define CONFIG_SYS_SDRAM_BASE 0x40000000
e049fe28 75#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
c199489f
IZ
76/* V3s do not have enough memory to place code at 0x4a000000 */
77#ifndef CONFIG_MACH_SUN8I_V3S
e049fe28 78#define CONFIG_SYS_TEXT_BASE 0x4a000000
c199489f
IZ
79#else
80#define CONFIG_SYS_TEXT_BASE 0x42e00000
81#endif
ff42d107
HG
82/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
83 * since it needs to fit in with the other values. By also #defining it
84 * we get warnings if the Kconfig value mismatches. */
85#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
e049fe28
HG
86#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
87#endif
88
89#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
e049fe28 90
bc613d85 91#ifdef CONFIG_SUNXI_HIGH_SRAM
77fe9887
HG
92/*
93 * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
94 * slightly bigger. Note that it is possible to map the first 32 KiB of the
95 * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
96 * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
97 * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
98 */
99#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
eb504fa1 100#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
77fe9887 101#else
cba69eee
IC
102#define CONFIG_SYS_INIT_RAM_ADDR 0x0
103#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
77fe9887 104#endif
cba69eee
IC
105
106#define CONFIG_SYS_INIT_SP_OFFSET \
107 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
108#define CONFIG_SYS_INIT_SP_ADDR \
109 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
110
111#define CONFIG_NR_DRAM_BANKS 1
112#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
113#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
114
a6e50a88
IC
115#ifdef CONFIG_AHCI
116#define CONFIG_LIBATA
117#define CONFIG_SCSI_AHCI
118#define CONFIG_SCSI_AHCI_PLAT
119#define CONFIG_SUNXI_AHCI
0751b138 120#define CONFIG_SYS_64BIT_LBA
a6e50a88
IC
121#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
122#define CONFIG_SYS_SCSI_MAX_LUN 1
123#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
124 CONFIG_SYS_SCSI_MAX_LUN)
c649e3c9 125#define CONFIG_SCSI
a6e50a88
IC
126#endif
127
cba69eee
IC
128#define CONFIG_SETUP_MEMORY_TAGS
129#define CONFIG_CMDLINE_TAG
130#define CONFIG_INITRD_TAG
9f852211 131#define CONFIG_SERIAL_TAG
cba69eee 132
e5268616 133#ifdef CONFIG_NAND_SUNXI
a0dfa88b 134#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
4ccae81c
BB
135#define CONFIG_SYS_NAND_ONFI_DETECTION
136#define CONFIG_SYS_MAX_NAND_DEVICE 8
d482a8df
HG
137
138#define CONFIG_MTD_DEVICE
139#define CONFIG_MTD_PARTITIONS
960caeba
PZ
140#endif
141
19e99fb4 142#ifdef CONFIG_SPL_SPI_SUNXI
19e99fb4
SS
143#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
144#endif
145
e24ea55c 146/* mmc config */
44c79879 147#ifdef CONFIG_MMC
e24ea55c 148#define CONFIG_MMC_SUNXI_SLOT 0
fb1c43cc
MR
149#endif
150
151#if defined(CONFIG_ENV_IS_IN_MMC)
e24ea55c 152#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
ae042beb 153#define CONFIG_SYS_MMC_MAX_DEVICE 4
d6a7e0cb
MR
154#elif defined(CONFIG_ENV_IS_NOWHERE)
155#define CONFIG_ENV_SIZE (128 << 10)
ff2b47f6 156#endif
e24ea55c 157
c199489f 158#ifndef CONFIG_MACH_SUN8I_V3S
5c965ed9
HG
159/* 64MB of malloc() pool */
160#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
c199489f
IZ
161#else
162/* 2MB of malloc() pool */
163#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
164#endif
cba69eee
IC
165
166/*
167 * Miscellaneous configurable options
168 */
06beadb0
IC
169#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
170#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
cba69eee 171#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
cba69eee
IC
172
173/* Boot Argument Buffer Size */
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
175
cba69eee 176/* standalone support */
e049fe28 177#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
cba69eee 178
cba69eee
IC
179/* FLASH and environment organization */
180
fa5e1020 181#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
cba69eee 182
cba69eee
IC
183#define CONFIG_FAT_WRITE /* enable write access */
184
185#define CONFIG_SPL_FRAMEWORK
cba69eee 186
eb77f5c9 187#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */
942cb0b6 188#define CONFIG_SPL_BOARD_LOAD_IMAGE
eb77f5c9 189#endif
942cb0b6 190
bc613d85 191#ifdef CONFIG_SUNXI_HIGH_SRAM
7f0ef5a9
SS
192#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
193#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
54522c92
AP
194#ifdef CONFIG_ARM64
195/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */
196#define LOW_LEVEL_SRAM_STACK 0x00054000
197#else
bc613d85 198#define LOW_LEVEL_SRAM_STACK 0x00018000
54522c92 199#endif /* !CONFIG_ARM64 */
d96ebc46 200#else
7f0ef5a9
SS
201#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
202#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
bc613d85 203#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
d96ebc46 204#endif
50827a59 205
bc613d85
AP
206#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
207
d96ebc46 208#ifndef CONFIG_ARM64
50827a59 209#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
d96ebc46 210#endif
50827a59 211
50827a59
IC
212#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
213
cba69eee 214
6620377e 215/* I2C */
0d8382ae
JW
216#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
217 defined CONFIG_SY8106A_POWER
ad40610b
HG
218#endif
219
6c739c5d
PK
220#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
221 defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
9d082687 222 defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
6620377e 223#define CONFIG_SYS_I2C_MVTWSI
a8f01ccf
JS
224#ifndef CONFIG_DM_I2C
225#define CONFIG_SYS_I2C
6620377e
HG
226#define CONFIG_SYS_I2C_SPEED 400000
227#define CONFIG_SYS_I2C_SLAVE 0x7f
8b2db32a 228#endif
a8f01ccf 229#endif
55410089
HG
230
231#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
232#define CONFIG_SYS_I2C_SOFT
233#define CONFIG_SYS_I2C_SOFT_SPEED 50000
234#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
55410089
HG
235/* We use pin names in Kconfig and sunxi_name_to_gpio() */
236#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
237#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
238#ifndef __ASSEMBLY__
239extern int soft_i2c_gpio_sda;
240extern int soft_i2c_gpio_scl;
241#endif
1fc42018
HG
242#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
243#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
244#else
245#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
246#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
55410089
HG
247#endif
248
14bc66bd 249/* PMU */
95ab8fee 250#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
0d8382ae
JW
251 defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
252 defined CONFIG_SY8106A_POWER
14bc66bd
HN
253#endif
254
a5da3c83 255#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
f3133962
HG
256#if CONFIG_CONS_INDEX == 1
257#ifdef CONFIG_MACH_SUN9I
258#define OF_STDOUT_PATH "/soc/serial@07000000:115200"
259#else
260#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200"
261#endif
262#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
263#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
5cd83b11
LI
264#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
265#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
f3133962
HG
266#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
267#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200"
268#else
269#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
270#endif
a5da3c83 271#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */
f3133962 272
abce2c62
IC
273/* GPIO */
274#define CONFIG_SUNXI_GPIO
abce2c62 275
7f2c521f
LV
276#ifdef CONFIG_VIDEO
277/*
5633a296
HG
278 * The amount of RAM to keep free at the top of RAM when relocating u-boot,
279 * to use as framebuffer. This must be a multiple of 4096.
7f2c521f 280 */
5c965ed9 281#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
7f2c521f 282
2d7a084b
LV
283/* Do we want to initialize a simple FB? */
284#define CONFIG_VIDEO_DT_SIMPLEFB
285
7f2c521f
LV
286#define CONFIG_VIDEO_SUNXI
287
7f2c521f 288#define CONFIG_VIDEO_LOGO
be8ec633 289#define CONFIG_VIDEO_STD_TIMINGS
75481607 290#define CONFIG_I2C_EDID
58332f89 291#define VIDEO_LINE_LEN (pGD->plnSizeX)
7f2c521f
LV
292
293/* allow both serial and cfb console. */
7f2c521f 294/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
7f2c521f 295
7f2c521f
LV
296#endif /* CONFIG_VIDEO */
297
c26fb9db
HG
298/* Ethernet support */
299#ifdef CONFIG_SUNXI_EMAC
8145dea4 300#define CONFIG_PHY_ADDR 1
c26fb9db 301#define CONFIG_MII /* MII PHY management */
8145dea4 302#define CONFIG_PHYLIB
c26fb9db
HG
303#endif
304
5835823d 305#ifdef CONFIG_SUNXI_GMAC
5835823d
IC
306#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
307#define CONFIG_PHY_ADDR 1
308#define CONFIG_MII /* MII PHY management */
1eae8f66 309#define CONFIG_PHY_REALTEK
5835823d
IC
310#endif
311
2582ca0d 312#ifdef CONFIG_USB_EHCI_HCD
6a72e804
HG
313#define CONFIG_USB_OHCI_NEW
314#define CONFIG_USB_OHCI_SUNXI
315#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
3584f30c 316#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
1a800f7a
HG
317#endif
318
319#ifdef CONFIG_USB_MUSB_SUNXI
95de1e2f 320#define CONFIG_USB_MUSB_PIO_ONLY
1a800f7a
HG
321#endif
322
b21144eb 323#ifdef CONFIG_USB_MUSB_GADGET
aaa4a9e3
SP
324#define CONFIG_USB_FUNCTION_FASTBOOT
325#define CONFIG_USB_FUNCTION_MASS_STORAGE
b21144eb
PK
326#endif
327
328#ifdef CONFIG_USB_FUNCTION_FASTBOOT
329#define CONFIG_CMD_FASTBOOT
330#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
331#define CONFIG_FASTBOOT_BUF_SIZE 0x2000000
bac83fb0 332#define CONFIG_ANDROID_BOOT_IMAGE
b21144eb
PK
333
334#define CONFIG_FASTBOOT_FLASH
44c79879
MR
335
336#ifdef CONFIG_MMC
b21144eb 337#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
b21144eb 338#endif
44c79879 339#endif
b21144eb
PK
340
341#ifdef CONFIG_USB_FUNCTION_MASS_STORAGE
b21144eb
PK
342#endif
343
86b49093 344#ifdef CONFIG_USB_KEYBOARD
86b49093 345#define CONFIG_PREBOOT
eab9433a 346#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
86b49093
HG
347#endif
348
b41d7d05
JL
349#define CONFIG_MISC_INIT_R
350
cba69eee
IC
351#ifndef CONFIG_SPL_BUILD
352#include <config_distro_defaults.h>
2ec3a612 353
671f9ad8
AP
354#ifdef CONFIG_ARM64
355/*
356 * Boards seem to come with at least 512MB of DRAM.
357 * The kernel should go at 512K, which is the default text offset (that will
358 * be adjusted at runtime if needed).
359 * There is no compression for arm64 kernels (yet), so leave some space
360 * for really big kernels, say 256MB for now.
361 * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
362 * Align the initrd to a 2MB page.
363 */
c199489f 364#define BOOTM_SIZE __stringify(0xa000000)
671f9ad8
AP
365#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000))
366#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000))
367#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000))
368#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000))
369#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000))
370
371#else
8c95c556 372/*
5c965ed9 373 * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
8c95c556
HG
374 * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
375 * 1M script, 1M pxe and the ramdisk at the end.
376 */
c199489f
IZ
377#ifndef CONFIG_MACH_SUN8I_V3S
378#define BOOTM_SIZE __stringify(0xa000000)
2a909c5f
SS
379#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
380#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
381#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
382#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
383#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
c199489f
IZ
384#else
385/*
386 * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
387 * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
388 * 1M script, 1M pxe and the ramdisk at the end.
389 */
390#define BOOTM_SIZE __stringify(0x2e00000)
391#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
392#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
393#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
394#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
395#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
396#endif
671f9ad8 397#endif
2a909c5f 398
846e3254 399#define MEM_LAYOUT_ENV_SETTINGS \
c199489f 400 "bootm_size=" BOOTM_SIZE "\0" \
2a909c5f
SS
401 "kernel_addr_r=" KERNEL_ADDR_R "\0" \
402 "fdt_addr_r=" FDT_ADDR_R "\0" \
403 "scriptaddr=" SCRIPT_ADDR_R "\0" \
404 "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
405 "ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
406
407#define DFU_ALT_INFO_RAM \
408 "dfu_alt_info_ram=" \
409 "kernel ram " KERNEL_ADDR_R " 0x1000000;" \
410 "fdt ram " FDT_ADDR_R " 0x100000;" \
411 "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
846e3254 412
41f8e9f5
CYT
413#ifdef CONFIG_MMC
414#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
5a37a400
KM
415#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
416#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1)
417#else
418#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
419#endif
41f8e9f5
CYT
420#else
421#define BOOT_TARGET_DEVICES_MMC(func)
5a37a400 422#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
41f8e9f5
CYT
423#endif
424
2ec3a612
HG
425#ifdef CONFIG_AHCI
426#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
427#else
428#define BOOT_TARGET_DEVICES_SCSI(func)
429#endif
430
2582ca0d 431#ifdef CONFIG_USB_STORAGE
859b3f14
CYT
432#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
433#else
434#define BOOT_TARGET_DEVICES_USB(func)
435#endif
436
f3b589c0
BN
437/* FEL boot support, auto-execute boot.scr if a script address was provided */
438#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
439 "bootcmd_fel=" \
440 "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \
441 "echo '(FEL boot)'; " \
442 "source ${fel_scriptaddr}; " \
443 "fi\0"
444#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \
445 "fel "
446
2ec3a612 447#define BOOT_TARGET_DEVICES(func) \
f3b589c0 448 func(FEL, fel, na) \
41f8e9f5 449 BOOT_TARGET_DEVICES_MMC(func) \
5a37a400 450 BOOT_TARGET_DEVICES_MMC_EXTRA(func) \
2ec3a612 451 BOOT_TARGET_DEVICES_SCSI(func) \
859b3f14 452 BOOT_TARGET_DEVICES_USB(func) \
2ec3a612
HG
453 func(PXE, pxe, na) \
454 func(DHCP, dhcp, na)
455
3b824025
HG
456#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
457#define BOOTCMD_SUNXI_COMPAT \
458 "bootcmd_sunxi_compat=" \
459 "setenv root /dev/mmcblk0p3 rootwait; " \
460 "if ext2load mmc 0 0x44000000 uEnv.txt; then " \
461 "echo Loaded environment from uEnv.txt; " \
462 "env import -t 0x44000000 ${filesize}; " \
463 "fi; " \
464 "setenv bootargs console=${console} root=${root} ${extraargs}; " \
465 "ext2load mmc 0 0x43000000 script.bin && " \
466 "ext2load mmc 0 0x48000000 uImage && " \
467 "bootm 0x48000000\0"
468#else
469#define BOOTCMD_SUNXI_COMPAT
470#endif
471
2ec3a612
HG
472#include <config_distro_bootcmd.h>
473
86b49093
HG
474#ifdef CONFIG_USB_KEYBOARD
475#define CONSOLE_STDIN_SETTINGS \
476 "preboot=usb start\0" \
477 "stdin=serial,usbkbd\0"
478#else
7f2c521f
LV
479#define CONSOLE_STDIN_SETTINGS \
480 "stdin=serial\0"
86b49093 481#endif
7f2c521f
LV
482
483#ifdef CONFIG_VIDEO
484#define CONSOLE_STDOUT_SETTINGS \
485 "stdout=serial,vga\0" \
486 "stderr=serial,vga\0"
56009451
JS
487#elif CONFIG_DM_VIDEO
488#define CONFIG_SYS_WHITE_ON_BLACK
489#define CONSOLE_STDOUT_SETTINGS \
490 "stdout=serial,vidconsole\0" \
491 "stderr=serial,vidconsole\0"
7f2c521f
LV
492#else
493#define CONSOLE_STDOUT_SETTINGS \
494 "stdout=serial\0" \
495 "stderr=serial\0"
496#endif
497
c8564b24
MR
498#ifdef CONFIG_MTDIDS_DEFAULT
499#define SUNXI_MTDIDS_DEFAULT \
500 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"
501#else
502#define SUNXI_MTDIDS_DEFAULT
503#endif
504
505#ifdef CONFIG_MTDPARTS_DEFAULT
506#define SUNXI_MTDPARTS_DEFAULT \
507 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
508#else
509#define SUNXI_MTDPARTS_DEFAULT
510#endif
511
7f2c521f
LV
512#define CONSOLE_ENV_SETTINGS \
513 CONSOLE_STDIN_SETTINGS \
514 CONSOLE_STDOUT_SETTINGS
515
2eff3b71
AF
516#ifdef CONFIG_ARM64
517#define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
518#else
519#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
520#endif
521
2ec3a612 522#define CONFIG_EXTRA_ENV_SETTINGS \
7f2c521f 523 CONSOLE_ENV_SETTINGS \
846e3254 524 MEM_LAYOUT_ENV_SETTINGS \
2a909c5f 525 DFU_ALT_INFO_RAM \
2eff3b71 526 "fdtfile=" FDTFILE "\0" \
846e3254 527 "console=ttyS0,115200\0" \
c8564b24
MR
528 SUNXI_MTDIDS_DEFAULT \
529 SUNXI_MTDPARTS_DEFAULT \
3b824025 530 BOOTCMD_SUNXI_COMPAT \
2ec3a612
HG
531 BOOTENV
532
533#else /* ifndef CONFIG_SPL_BUILD */
534#define CONFIG_EXTRA_ENV_SETTINGS
cba69eee
IC
535#endif
536
537#endif /* _SUNXI_COMMON_CONFIG_H */