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cba69eee IC |
1 | /* |
2 | * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * | |
4 | * (C) Copyright 2007-2011 | |
5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
6 | * Tom Cubie <tangliang@allwinnertech.com> | |
7 | * | |
8 | * Configuration settings for the Allwinner sunxi series of boards. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef _SUNXI_COMMON_CONFIG_H | |
14 | #define _SUNXI_COMMON_CONFIG_H | |
15 | ||
daf6d399 | 16 | #include <asm/arch/cpu.h> |
e049fe28 HG |
17 | #include <linux/stringify.h> |
18 | ||
77ef1369 SS |
19 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
20 | /* | |
21 | * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the | |
22 | * expense of restricting some features, so the regular machine id values can | |
23 | * be used. | |
24 | */ | |
25 | # define CONFIG_MACH_TYPE_COMPAT_REV 0 | |
26 | #else | |
27 | /* | |
28 | * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. | |
29 | * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass | |
30 | * beyond the machine id check. | |
31 | */ | |
32 | # define CONFIG_MACH_TYPE_COMPAT_REV 1 | |
33 | #endif | |
34 | ||
cba69eee | 35 | /* Serial & console */ |
cba69eee IC |
36 | #define CONFIG_SYS_NS16550_SERIAL |
37 | /* ns16550 reg in the low bits of cpu reg */ | |
cba69eee | 38 | #define CONFIG_SYS_NS16550_CLK 24000000 |
4fb60552 | 39 | #ifndef CONFIG_DM_SERIAL |
1a81cf83 SG |
40 | # define CONFIG_SYS_NS16550_REG_SIZE -4 |
41 | # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE | |
42 | # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE | |
43 | # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE | |
44 | # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE | |
45 | # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE | |
46 | #endif | |
cba69eee | 47 | |
8a65f69c | 48 | /* CPU */ |
e4916e85 | 49 | #define COUNTER_FREQUENCY 24000000 |
8a65f69c | 50 | |
e049fe28 HG |
51 | /* |
52 | * The DRAM Base differs between some models. We cannot use macros for the | |
53 | * CONFIG_FOO defines which contain the DRAM base address since they end | |
54 | * up unexpanded in include/autoconf.mk . | |
55 | * | |
56 | * So we have to have this #ifdef #else #endif block for these. | |
57 | */ | |
58 | #ifdef CONFIG_MACH_SUN9I | |
59 | #define SDRAM_OFFSET(x) 0x2##x | |
60 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
61 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ | |
62 | #define CONFIG_SYS_TEXT_BASE 0x2a000000 | |
ff42d107 HG |
63 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
64 | * since it needs to fit in with the other values. By also #defining it | |
65 | * we get warnings if the Kconfig value mismatches. */ | |
66 | #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 | |
e049fe28 HG |
67 | #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 |
68 | #else | |
69 | #define SDRAM_OFFSET(x) 0x4##x | |
cba69eee | 70 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
e049fe28 HG |
71 | #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ |
72 | #define CONFIG_SYS_TEXT_BASE 0x4a000000 | |
ff42d107 HG |
73 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
74 | * since it needs to fit in with the other values. By also #defining it | |
75 | * we get warnings if the Kconfig value mismatches. */ | |
76 | #define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 | |
e049fe28 HG |
77 | #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 |
78 | #endif | |
79 | ||
80 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ | |
e049fe28 | 81 | |
bc613d85 | 82 | #ifdef CONFIG_SUNXI_HIGH_SRAM |
77fe9887 HG |
83 | /* |
84 | * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is | |
85 | * slightly bigger. Note that it is possible to map the first 32 KiB of the | |
86 | * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the | |
87 | * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and | |
88 | * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. | |
89 | */ | |
90 | #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 | |
eb504fa1 | 91 | #define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ |
77fe9887 | 92 | #else |
cba69eee IC |
93 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 |
94 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ | |
77fe9887 | 95 | #endif |
cba69eee IC |
96 | |
97 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
98 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
99 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
100 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
101 | ||
102 | #define CONFIG_NR_DRAM_BANKS 1 | |
103 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE | |
104 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ | |
105 | ||
a6e50a88 IC |
106 | #ifdef CONFIG_AHCI |
107 | #define CONFIG_LIBATA | |
108 | #define CONFIG_SCSI_AHCI | |
109 | #define CONFIG_SCSI_AHCI_PLAT | |
110 | #define CONFIG_SUNXI_AHCI | |
0751b138 | 111 | #define CONFIG_SYS_64BIT_LBA |
a6e50a88 IC |
112 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
113 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
114 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
115 | CONFIG_SYS_SCSI_MAX_LUN) | |
c649e3c9 | 116 | #define CONFIG_SCSI |
a6e50a88 IC |
117 | #endif |
118 | ||
cba69eee IC |
119 | #define CONFIG_SETUP_MEMORY_TAGS |
120 | #define CONFIG_CMDLINE_TAG | |
121 | #define CONFIG_INITRD_TAG | |
9f852211 | 122 | #define CONFIG_SERIAL_TAG |
cba69eee | 123 | |
e5268616 | 124 | #ifdef CONFIG_NAND_SUNXI |
a0dfa88b | 125 | #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 |
4ccae81c BB |
126 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
127 | #define CONFIG_SYS_MAX_NAND_DEVICE 8 | |
960caeba PZ |
128 | #endif |
129 | ||
19e99fb4 | 130 | #ifdef CONFIG_SPL_SPI_SUNXI |
19e99fb4 SS |
131 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
132 | #endif | |
133 | ||
e24ea55c | 134 | /* mmc config */ |
44c79879 | 135 | #ifdef CONFIG_MMC |
e24ea55c | 136 | #define CONFIG_MMC_SUNXI_SLOT 0 |
e24ea55c IC |
137 | #define CONFIG_ENV_IS_IN_MMC |
138 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ | |
ae042beb | 139 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
ff2b47f6 | 140 | #endif |
e24ea55c | 141 | |
5c965ed9 HG |
142 | /* 64MB of malloc() pool */ |
143 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) | |
cba69eee IC |
144 | |
145 | /* | |
146 | * Miscellaneous configurable options | |
147 | */ | |
06beadb0 IC |
148 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
149 | #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ | |
cba69eee | 150 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
cba69eee IC |
151 | |
152 | /* Boot Argument Buffer Size */ | |
153 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
154 | ||
cba69eee | 155 | /* standalone support */ |
e049fe28 | 156 | #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR |
cba69eee | 157 | |
cba69eee | 158 | /* baudrate */ |
cba69eee IC |
159 | |
160 | /* The stack sizes are set up in start.S using the settings below */ | |
161 | #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ | |
162 | ||
163 | /* FLASH and environment organization */ | |
164 | ||
fa5e1020 | 165 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ |
cba69eee | 166 | |
e24ea55c | 167 | #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ |
cba69eee IC |
168 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
169 | ||
cba69eee IC |
170 | #define CONFIG_FAT_WRITE /* enable write access */ |
171 | ||
172 | #define CONFIG_SPL_FRAMEWORK | |
cba69eee | 173 | |
eb77f5c9 | 174 | #ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */ |
942cb0b6 | 175 | #define CONFIG_SPL_BOARD_LOAD_IMAGE |
eb77f5c9 | 176 | #endif |
942cb0b6 | 177 | |
bc613d85 | 178 | #ifdef CONFIG_SUNXI_HIGH_SRAM |
b19236fd | 179 | #define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ |
bc613d85 AP |
180 | #define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */ |
181 | #define LOW_LEVEL_SRAM_STACK 0x00018000 | |
d96ebc46 | 182 | #else |
b19236fd SS |
183 | #define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ |
184 | #define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ | |
bc613d85 | 185 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ |
d96ebc46 | 186 | #endif |
50827a59 | 187 | |
bc613d85 AP |
188 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
189 | ||
d96ebc46 | 190 | #ifndef CONFIG_ARM64 |
50827a59 | 191 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" |
d96ebc46 | 192 | #endif |
50827a59 | 193 | |
50827a59 IC |
194 | #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ |
195 | ||
cba69eee | 196 | |
6620377e | 197 | /* I2C */ |
0d8382ae JW |
198 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ |
199 | defined CONFIG_SY8106A_POWER | |
ad40610b HG |
200 | #endif |
201 | ||
6c739c5d PK |
202 | #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ |
203 | defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ | |
9d082687 | 204 | defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE |
8b2db32a | 205 | #define CONFIG_SYS_I2C |
6620377e HG |
206 | #define CONFIG_SYS_I2C_MVTWSI |
207 | #define CONFIG_SYS_I2C_SPEED 400000 | |
208 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
8b2db32a | 209 | #endif |
55410089 HG |
210 | |
211 | #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) | |
212 | #define CONFIG_SYS_I2C_SOFT | |
213 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
214 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 | |
55410089 HG |
215 | /* We use pin names in Kconfig and sunxi_name_to_gpio() */ |
216 | #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda | |
217 | #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl | |
218 | #ifndef __ASSEMBLY__ | |
219 | extern int soft_i2c_gpio_sda; | |
220 | extern int soft_i2c_gpio_scl; | |
221 | #endif | |
1fc42018 HG |
222 | #define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ |
223 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ | |
224 | #else | |
225 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ | |
226 | #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ | |
55410089 HG |
227 | #endif |
228 | ||
14bc66bd | 229 | /* PMU */ |
95ab8fee | 230 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ |
0d8382ae JW |
231 | defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ |
232 | defined CONFIG_SY8106A_POWER | |
14bc66bd HN |
233 | #endif |
234 | ||
f84269c5 | 235 | #ifndef CONFIG_CONS_INDEX |
cba69eee | 236 | #define CONFIG_CONS_INDEX 1 /* UART0 */ |
f84269c5 | 237 | #endif |
cba69eee | 238 | |
a5da3c83 | 239 | #ifdef CONFIG_REQUIRE_SERIAL_CONSOLE |
f3133962 HG |
240 | #if CONFIG_CONS_INDEX == 1 |
241 | #ifdef CONFIG_MACH_SUN9I | |
242 | #define OF_STDOUT_PATH "/soc/serial@07000000:115200" | |
243 | #else | |
244 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" | |
245 | #endif | |
246 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) | |
247 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" | |
5cd83b11 LI |
248 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
249 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" | |
f3133962 HG |
250 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
251 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" | |
252 | #else | |
253 | #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. | |
254 | #endif | |
a5da3c83 | 255 | #endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ |
f3133962 | 256 | |
abce2c62 IC |
257 | /* GPIO */ |
258 | #define CONFIG_SUNXI_GPIO | |
abce2c62 | 259 | |
7f2c521f LV |
260 | #ifdef CONFIG_VIDEO |
261 | /* | |
5633a296 HG |
262 | * The amount of RAM to keep free at the top of RAM when relocating u-boot, |
263 | * to use as framebuffer. This must be a multiple of 4096. | |
7f2c521f | 264 | */ |
5c965ed9 | 265 | #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) |
7f2c521f | 266 | |
2d7a084b LV |
267 | /* Do we want to initialize a simple FB? */ |
268 | #define CONFIG_VIDEO_DT_SIMPLEFB | |
269 | ||
7f2c521f LV |
270 | #define CONFIG_VIDEO_SUNXI |
271 | ||
7f2c521f | 272 | #define CONFIG_VIDEO_LOGO |
be8ec633 | 273 | #define CONFIG_VIDEO_STD_TIMINGS |
75481607 | 274 | #define CONFIG_I2C_EDID |
58332f89 | 275 | #define VIDEO_LINE_LEN (pGD->plnSizeX) |
7f2c521f LV |
276 | |
277 | /* allow both serial and cfb console. */ | |
7f2c521f | 278 | /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ |
7f2c521f | 279 | |
7f2c521f LV |
280 | #endif /* CONFIG_VIDEO */ |
281 | ||
c26fb9db HG |
282 | /* Ethernet support */ |
283 | #ifdef CONFIG_SUNXI_EMAC | |
8145dea4 | 284 | #define CONFIG_PHY_ADDR 1 |
c26fb9db | 285 | #define CONFIG_MII /* MII PHY management */ |
8145dea4 | 286 | #define CONFIG_PHYLIB |
c26fb9db HG |
287 | #endif |
288 | ||
5835823d | 289 | #ifdef CONFIG_SUNXI_GMAC |
5835823d IC |
290 | #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ |
291 | #define CONFIG_PHY_ADDR 1 | |
292 | #define CONFIG_MII /* MII PHY management */ | |
1eae8f66 | 293 | #define CONFIG_PHY_REALTEK |
5835823d IC |
294 | #endif |
295 | ||
2582ca0d | 296 | #ifdef CONFIG_USB_EHCI_HCD |
6a72e804 HG |
297 | #define CONFIG_USB_OHCI_NEW |
298 | #define CONFIG_USB_OHCI_SUNXI | |
299 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
3584f30c | 300 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 |
1a800f7a HG |
301 | #endif |
302 | ||
303 | #ifdef CONFIG_USB_MUSB_SUNXI | |
95de1e2f | 304 | #define CONFIG_USB_MUSB_PIO_ONLY |
1a800f7a HG |
305 | #endif |
306 | ||
b21144eb | 307 | #ifdef CONFIG_USB_MUSB_GADGET |
aaa4a9e3 SP |
308 | #define CONFIG_USB_FUNCTION_FASTBOOT |
309 | #define CONFIG_USB_FUNCTION_MASS_STORAGE | |
b21144eb PK |
310 | #endif |
311 | ||
312 | #ifdef CONFIG_USB_FUNCTION_FASTBOOT | |
313 | #define CONFIG_CMD_FASTBOOT | |
314 | #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR | |
315 | #define CONFIG_FASTBOOT_BUF_SIZE 0x2000000 | |
bac83fb0 | 316 | #define CONFIG_ANDROID_BOOT_IMAGE |
b21144eb PK |
317 | |
318 | #define CONFIG_FASTBOOT_FLASH | |
44c79879 MR |
319 | |
320 | #ifdef CONFIG_MMC | |
b21144eb | 321 | #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 |
b21144eb | 322 | #endif |
44c79879 | 323 | #endif |
b21144eb PK |
324 | |
325 | #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE | |
b21144eb PK |
326 | #endif |
327 | ||
86b49093 | 328 | #ifdef CONFIG_USB_KEYBOARD |
86b49093 | 329 | #define CONFIG_PREBOOT |
eab9433a | 330 | #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE |
86b49093 HG |
331 | #endif |
332 | ||
cba69eee IC |
333 | #if !defined CONFIG_ENV_IS_IN_MMC && \ |
334 | !defined CONFIG_ENV_IS_IN_NAND && \ | |
335 | !defined CONFIG_ENV_IS_IN_FAT && \ | |
336 | !defined CONFIG_ENV_IS_IN_SPI_FLASH | |
337 | #define CONFIG_ENV_IS_NOWHERE | |
338 | #endif | |
339 | ||
b41d7d05 JL |
340 | #define CONFIG_MISC_INIT_R |
341 | ||
cba69eee IC |
342 | #ifndef CONFIG_SPL_BUILD |
343 | #include <config_distro_defaults.h> | |
2ec3a612 | 344 | |
671f9ad8 AP |
345 | #ifdef CONFIG_ARM64 |
346 | /* | |
347 | * Boards seem to come with at least 512MB of DRAM. | |
348 | * The kernel should go at 512K, which is the default text offset (that will | |
349 | * be adjusted at runtime if needed). | |
350 | * There is no compression for arm64 kernels (yet), so leave some space | |
351 | * for really big kernels, say 256MB for now. | |
352 | * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. | |
353 | * Align the initrd to a 2MB page. | |
354 | */ | |
355 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) | |
356 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) | |
357 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) | |
358 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) | |
359 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) | |
360 | ||
361 | #else | |
8c95c556 | 362 | /* |
5c965ed9 | 363 | * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. |
8c95c556 HG |
364 | * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
365 | * 1M script, 1M pxe and the ramdisk at the end. | |
366 | */ | |
2a909c5f SS |
367 | |
368 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) | |
369 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) | |
370 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) | |
371 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) | |
372 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) | |
671f9ad8 | 373 | #endif |
2a909c5f | 374 | |
846e3254 | 375 | #define MEM_LAYOUT_ENV_SETTINGS \ |
5c965ed9 | 376 | "bootm_size=0xa000000\0" \ |
2a909c5f SS |
377 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
378 | "fdt_addr_r=" FDT_ADDR_R "\0" \ | |
379 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ | |
380 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ | |
381 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" | |
382 | ||
383 | #define DFU_ALT_INFO_RAM \ | |
384 | "dfu_alt_info_ram=" \ | |
385 | "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ | |
386 | "fdt ram " FDT_ADDR_R " 0x100000;" \ | |
387 | "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" | |
846e3254 | 388 | |
41f8e9f5 CYT |
389 | #ifdef CONFIG_MMC |
390 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) | |
5a37a400 KM |
391 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
392 | #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1) | |
393 | #else | |
394 | #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) | |
395 | #endif | |
41f8e9f5 CYT |
396 | #else |
397 | #define BOOT_TARGET_DEVICES_MMC(func) | |
5a37a400 | 398 | #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) |
41f8e9f5 CYT |
399 | #endif |
400 | ||
2ec3a612 HG |
401 | #ifdef CONFIG_AHCI |
402 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) | |
403 | #else | |
404 | #define BOOT_TARGET_DEVICES_SCSI(func) | |
405 | #endif | |
406 | ||
2582ca0d | 407 | #ifdef CONFIG_USB_STORAGE |
859b3f14 CYT |
408 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
409 | #else | |
410 | #define BOOT_TARGET_DEVICES_USB(func) | |
411 | #endif | |
412 | ||
f3b589c0 BN |
413 | /* FEL boot support, auto-execute boot.scr if a script address was provided */ |
414 | #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ | |
415 | "bootcmd_fel=" \ | |
416 | "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ | |
417 | "echo '(FEL boot)'; " \ | |
418 | "source ${fel_scriptaddr}; " \ | |
419 | "fi\0" | |
420 | #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ | |
421 | "fel " | |
422 | ||
2ec3a612 | 423 | #define BOOT_TARGET_DEVICES(func) \ |
f3b589c0 | 424 | func(FEL, fel, na) \ |
41f8e9f5 | 425 | BOOT_TARGET_DEVICES_MMC(func) \ |
5a37a400 | 426 | BOOT_TARGET_DEVICES_MMC_EXTRA(func) \ |
2ec3a612 | 427 | BOOT_TARGET_DEVICES_SCSI(func) \ |
859b3f14 | 428 | BOOT_TARGET_DEVICES_USB(func) \ |
2ec3a612 HG |
429 | func(PXE, pxe, na) \ |
430 | func(DHCP, dhcp, na) | |
431 | ||
3b824025 HG |
432 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
433 | #define BOOTCMD_SUNXI_COMPAT \ | |
434 | "bootcmd_sunxi_compat=" \ | |
435 | "setenv root /dev/mmcblk0p3 rootwait; " \ | |
436 | "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ | |
437 | "echo Loaded environment from uEnv.txt; " \ | |
438 | "env import -t 0x44000000 ${filesize}; " \ | |
439 | "fi; " \ | |
440 | "setenv bootargs console=${console} root=${root} ${extraargs}; " \ | |
441 | "ext2load mmc 0 0x43000000 script.bin && " \ | |
442 | "ext2load mmc 0 0x48000000 uImage && " \ | |
443 | "bootm 0x48000000\0" | |
444 | #else | |
445 | #define BOOTCMD_SUNXI_COMPAT | |
446 | #endif | |
447 | ||
2ec3a612 HG |
448 | #include <config_distro_bootcmd.h> |
449 | ||
86b49093 HG |
450 | #ifdef CONFIG_USB_KEYBOARD |
451 | #define CONSOLE_STDIN_SETTINGS \ | |
452 | "preboot=usb start\0" \ | |
453 | "stdin=serial,usbkbd\0" | |
454 | #else | |
7f2c521f LV |
455 | #define CONSOLE_STDIN_SETTINGS \ |
456 | "stdin=serial\0" | |
86b49093 | 457 | #endif |
7f2c521f LV |
458 | |
459 | #ifdef CONFIG_VIDEO | |
460 | #define CONSOLE_STDOUT_SETTINGS \ | |
461 | "stdout=serial,vga\0" \ | |
462 | "stderr=serial,vga\0" | |
463 | #else | |
464 | #define CONSOLE_STDOUT_SETTINGS \ | |
465 | "stdout=serial\0" \ | |
466 | "stderr=serial\0" | |
467 | #endif | |
468 | ||
469 | #define CONSOLE_ENV_SETTINGS \ | |
470 | CONSOLE_STDIN_SETTINGS \ | |
471 | CONSOLE_STDOUT_SETTINGS | |
472 | ||
2ec3a612 | 473 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
7f2c521f | 474 | CONSOLE_ENV_SETTINGS \ |
846e3254 | 475 | MEM_LAYOUT_ENV_SETTINGS \ |
2a909c5f | 476 | DFU_ALT_INFO_RAM \ |
25acd33f | 477 | "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
846e3254 | 478 | "console=ttyS0,115200\0" \ |
3b824025 | 479 | BOOTCMD_SUNXI_COMPAT \ |
2ec3a612 HG |
480 | BOOTENV |
481 | ||
482 | #else /* ifndef CONFIG_SPL_BUILD */ | |
483 | #define CONFIG_EXTRA_ENV_SETTINGS | |
cba69eee IC |
484 | #endif |
485 | ||
486 | #endif /* _SUNXI_COMMON_CONFIG_H */ |