[people/ms/u-boot.git] / include / configs / uc101.h

/*
 * (C) Copyright 2003-2009
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_UC101		1	/* UC101 board		*/
#define CONFIG_HOSTNAME		uc101

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"

#include "manroland/common.h"
#include "manroland/mpc5200-common.h"

/*
 * Serial console configuration
 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Flash configuration
 */
#define CONFIG_SYS_MAX_FLASH_SECT	140

/*
 * Environment settings
 */
#define CONFIG_ENV_SECT_SIZE	0x10000

/*
 * Memory map
 */
#define	CONFIG_SYS_IB_MASTER		0xc0510000	/* CS 6 */
#define CONFIG_SYS_IB_EPLD		0xc0500000	/* CS 7 */

/* SRAM */
#define CONFIG_SYS_SRAM_SIZE	0x200000

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x4d558044

#define CONFIG_SYS_MEMTEST_START	0x00300000
#define CONFIG_SYS_MEMTEST_END		0x00f00000

#define CONFIG_SYS_LOAD_ADDR		0x300000

#define CONFIG_SYS_BOOTCS_CFG		0x00045D00

/* 8Mbit SRAM @0x80100000 */
#define CONFIG_SYS_CS1_SIZE		0x00200000
#define CONFIG_SYS_CS1_CFG		0x21D00

/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
#define CONFIG_SYS_CS3_START		CONFIG_SYS_DISPLAY_BASE
#define CONFIG_SYS_CS3_SIZE		0x00000100
#define CONFIG_SYS_CS3_CFG		0x00081802

/* Interbus Master 16 Bit */
#define CONFIG_SYS_CS6_START		CONFIG_SYS_IB_MASTER
#define CONFIG_SYS_CS6_SIZE		0x00010000
#define CONFIG_SYS_CS6_CFG		0x00FF3500

/* Interbus EPLD 8 Bit */
#define CONFIG_SYS_CS7_START		CONFIG_SYS_IB_EPLD
#define CONFIG_SYS_CS7_SIZE		0x00010000
#define CONFIG_SYS_CS7_CFG		0x00081800

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus*/

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/
#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
6dedf3d4	1	/*
7f625fc6	2	* (C) Copyright 2003-2009
6dedf3d4 HS	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
6dedf3d4 HS	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
6dedf3d4 HS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
7f625fc6 HS	16	#define CONFIG_UC101 1 /* UC101 board */
7f625fc6 HS	17	#define CONFIG_HOSTNAME uc101
6dedf3d4	18
2ae18241 WD	19	#ifndef CONFIG_SYS_TEXT_BASE
	20	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	21	#endif
2ced53e1	22	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
2ae18241	23
7f625fc6 HS	24	#include "manroland/common.h"
7f625fc6 HS	25	#include "manroland/mpc5200-common.h"
31d82672	26
6dedf3d4 HS	27	/*
	28	* Serial console configuration
	29	*/
6dedf3d4	30	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6c18eb98	31
079a136c JL	32	/*
	33	* BOOTP options
	34	*/
	35	#define CONFIG_BOOTP_BOOTFILESIZE
	36	#define CONFIG_BOOTP_BOOTPATH
	37	#define CONFIG_BOOTP_GATEWAY
	38	#define CONFIG_BOOTP_HOSTNAME
	39
6dedf3d4 HS	40	/*
	41	* Flash configuration
	42	*/
7f625fc6	43	#define CONFIG_SYS_MAX_FLASH_SECT 140
6dedf3d4 HS	44
	45	/*
	46	* Environment settings
	47	*/
0e8d1586	48	#define CONFIG_ENV_SECT_SIZE 0x10000
6dedf3d4 HS	49
	50	/*
	51	* Memory map
	52	*/
6d0f6bcf JCPV	53	#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */
6d0f6bcf JCPV	54	#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */
6dedf3d4	55
6dedf3d4	56	/* SRAM */
d1831c5e	57	#define CONFIG_SYS_SRAM_SIZE 0x200000
6dedf3d4	58
6dedf3d4 HS	59	/*
	60	* GPIO configuration
	61	*/
6d0f6bcf	62	#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044
6dedf3d4	63
7f625fc6 HS	64	#define CONFIG_SYS_MEMTEST_START 0x00300000
7f625fc6 HS	65	#define CONFIG_SYS_MEMTEST_END 0x00f00000
6dedf3d4	66
7f625fc6	67	#define CONFIG_SYS_LOAD_ADDR 0x300000
6dedf3d4	68
6d0f6bcf	69	#define CONFIG_SYS_BOOTCS_CFG 0x00045D00
6dedf3d4 HS	70
6dedf3d4 HS	71	/* 8Mbit SRAM @0x80100000 */
6d0f6bcf JCPV	72	#define CONFIG_SYS_CS1_SIZE 0x00200000
6d0f6bcf JCPV	73	#define CONFIG_SYS_CS1_CFG 0x21D00
6dedf3d4 HS	74
6dedf3d4 HS	75	/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
6d0f6bcf JCPV	76	#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE
	77	#define CONFIG_SYS_CS3_SIZE 0x00000100
	78	#define CONFIG_SYS_CS3_CFG 0x00081802
6dedf3d4 HS	79
6dedf3d4 HS	80	/* Interbus Master 16 Bit */
6d0f6bcf JCPV	81	#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER
	82	#define CONFIG_SYS_CS6_SIZE 0x00010000
	83	#define CONFIG_SYS_CS6_CFG 0x00FF3500
6dedf3d4 HS	84
6dedf3d4 HS	85	/* Interbus EPLD 8 Bit */
6d0f6bcf JCPV	86	#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD
	87	#define CONFIG_SYS_CS7_SIZE 0x00010000
	88	#define CONFIG_SYS_CS7_CFG 0x00081800
6dedf3d4	89
6dedf3d4 HS	90	/*-----------------------------------------------------------------------
	91	* IDE/ATA stuff Supports IDE harddisk
	92	*-----------------------------------------------------------------------
	93	*/
	94
7f625fc6	95	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/
6dedf3d4 HS	96
	97	/---------------------------------------------------------------------/
	98	/* Display addresses */
	99	/---------------------------------------------------------------------/
6d0f6bcf JCPV	100	#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
6d0f6bcf JCPV	101	#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
6dedf3d4 HS	102
6dedf3d4 HS	103	#endif /* __CONFIG_H */