projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c00b5f85 WD |
1 | /*----------------------------------------------------------------------------+ |
| 2 | | | |
| ba56f625 WD |
3 | | This source code has been made available to you by IBM on an AS-IS |
| 4 | | basis. Anyone receiving this source is licensed under IBM | |
| 5 | | copyrights to use it in any way he or she deems fit, including | |
| 6 | | copying it, modifying it, compiling it, and redistributing it either | |
| 7 | | with or without modifications. No license under IBM patents or | |
| 8 | | patent applications is to be implied by the copyright license. | |
| c00b5f85 | 9 | | |
| ba56f625 WD |
10 | | Any user of this software should understand that IBM cannot provide |
| 11 | | technical support for this software and will not be responsible for | |
| 12 | | any consequences resulting from the use of this software. | |
| c00b5f85 | 13 | | |
| ba56f625 WD |
14 | | Any person who transfers this source code or any derivative work |
| 15 | | must include the IBM copyright notice, this paragraph, and the | |
| 16 | | preceding two paragraphs in the transferred software. | |
| c00b5f85 | 17 | | |
| ba56f625 WD |
18 | | COPYRIGHT I B M CORPORATION 1999 |
| 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
| c00b5f85 WD |
20 | +----------------------------------------------------------------------------*/ |
| 21 | ||
| c46f5333 LJ |
22 | /* |
| 23 | * (C) Copyright 2006 | |
| 24 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com | |
| 25 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
| 26 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com | |
| 27 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
| 28 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com | |
| 29 | * | |
| 30 | * This program is free software; you can redistribute it and/or | |
| 31 | * modify it under the terms of the GNU General Public License as | |
| 32 | * published by the Free Software Foundation; either version 2 of | |
| 33 | * the License, or (at your option) any later version. | |
| 34 | * | |
| 35 | * This program is distributed in the hope that it will be useful, | |
| 36 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 37 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 38 | * GNU General Public License for more details. | |
| 39 | * | |
| 40 | * You should have received a copy of the GNU General Public License | |
| 41 | * along with this program; if not, write to the Free Software | |
| 42 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 43 | * MA 02111-1307 USA | |
| 44 | */ | |
| 45 | ||
| ba56f625 | 46 | #ifndef __PPC440_H__ |
| c00b5f85 WD |
47 | #define __PPC440_H__ |
| 48 | ||
| 9b94ac61 SR |
49 | #define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ |
| 50 | ||
| c00b5f85 WD |
51 | /*--------------------------------------------------------------------- */ |
| 52 | /* Special Purpose Registers */ | |
| 53 | /*--------------------------------------------------------------------- */ | |
| 6c5879f3 MB |
54 | #define xer_reg 0x001 |
| 55 | #define lr_reg 0x008 | |
| ba56f625 WD |
56 | #define dec 0x016 /* decrementer */ |
| 57 | #define srr0 0x01a /* save/restore register 0 */ | |
| 58 | #define srr1 0x01b /* save/restore register 1 */ | |
| 59 | #define pid 0x030 /* process id */ | |
| 60 | #define decar 0x036 /* decrementer auto-reload */ | |
| 61 | #define csrr0 0x03a /* critical save/restore register 0 */ | |
| 62 | #define csrr1 0x03b /* critical save/restore register 1 */ | |
| 63 | #define dear 0x03d /* data exception address register */ | |
| 64 | #define esr 0x03e /* exception syndrome register */ | |
| 65 | #define ivpr 0x03f /* interrupt prefix register */ | |
| 66 | #define usprg0 0x100 /* user special purpose register general 0 */ | |
| 67 | #define usprg1 0x110 /* user special purpose register general 1 */ | |
| 6c5879f3 MB |
68 | #define tblr 0x10c /* time base lower, read only */ |
| 69 | #define tbur 0x10d /* time base upper, read only */ | |
| ba56f625 WD |
70 | #define sprg1 0x111 /* special purpose register general 1 */ |
| 71 | #define sprg2 0x112 /* special purpose register general 2 */ | |
| 72 | #define sprg3 0x113 /* special purpose register general 3 */ | |
| 73 | #define sprg4 0x114 /* special purpose register general 4 */ | |
| 74 | #define sprg5 0x115 /* special purpose register general 5 */ | |
| 75 | #define sprg6 0x116 /* special purpose register general 6 */ | |
| 76 | #define sprg7 0x117 /* special purpose register general 7 */ | |
| 77 | #define tbl 0x11c /* time base lower (supervisor)*/ | |
| 78 | #define tbu 0x11d /* time base upper (supervisor)*/ | |
| 79 | #define pir 0x11e /* processor id register */ | |
| ba56f625 WD |
80 | #define dbsr 0x130 /* debug status register */ |
| 81 | #define dbcr0 0x134 /* debug control register 0 */ | |
| 82 | #define dbcr1 0x135 /* debug control register 1 */ | |
| 83 | #define dbcr2 0x136 /* debug control register 2 */ | |
| 84 | #define iac1 0x138 /* instruction address compare 1 */ | |
| 85 | #define iac2 0x139 /* instruction address compare 2 */ | |
| 86 | #define iac3 0x13a /* instruction address compare 3 */ | |
| 87 | #define iac4 0x13b /* instruction address compare 4 */ | |
| 88 | #define dac1 0x13c /* data address compare 1 */ | |
| 89 | #define dac2 0x13d /* data address compare 2 */ | |
| 90 | #define dvc1 0x13e /* data value compare 1 */ | |
| 91 | #define dvc2 0x13f /* data value compare 2 */ | |
| 92 | #define tsr 0x150 /* timer status register */ | |
| 93 | #define tcr 0x154 /* timer control register */ | |
| 94 | #define ivor0 0x190 /* interrupt vector offset register 0 */ | |
| 95 | #define ivor1 0x191 /* interrupt vector offset register 1 */ | |
| 96 | #define ivor2 0x192 /* interrupt vector offset register 2 */ | |
| 97 | #define ivor3 0x193 /* interrupt vector offset register 3 */ | |
| 98 | #define ivor4 0x194 /* interrupt vector offset register 4 */ | |
| 99 | #define ivor5 0x195 /* interrupt vector offset register 5 */ | |
| 100 | #define ivor6 0x196 /* interrupt vector offset register 6 */ | |
| 101 | #define ivor7 0x197 /* interrupt vector offset register 7 */ | |
| 102 | #define ivor8 0x198 /* interrupt vector offset register 8 */ | |
| 103 | #define ivor9 0x199 /* interrupt vector offset register 9 */ | |
| 104 | #define ivor10 0x19a /* interrupt vector offset register 10 */ | |
| 105 | #define ivor11 0x19b /* interrupt vector offset register 11 */ | |
| 106 | #define ivor12 0x19c /* interrupt vector offset register 12 */ | |
| 107 | #define ivor13 0x19d /* interrupt vector offset register 13 */ | |
| 108 | #define ivor14 0x19e /* interrupt vector offset register 14 */ | |
| 109 | #define ivor15 0x19f /* interrupt vector offset register 15 */ | |
| efa35cf1 | 110 | #if defined(CONFIG_440) |
| ba56f625 WD |
111 | #define mcsrr0 0x23a /* machine check save/restore register 0 */ |
| 112 | #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ | |
| 113 | #define mcsr 0x23c /* machine check status register */ | |
| 114 | #endif | |
| 115 | #define inv0 0x370 /* instruction cache normal victim 0 */ | |
| 116 | #define inv1 0x371 /* instruction cache normal victim 1 */ | |
| 117 | #define inv2 0x372 /* instruction cache normal victim 2 */ | |
| 118 | #define inv3 0x373 /* instruction cache normal victim 3 */ | |
| 119 | #define itv0 0x374 /* instruction cache transient victim 0 */ | |
| 120 | #define itv1 0x375 /* instruction cache transient victim 1 */ | |
| 121 | #define itv2 0x376 /* instruction cache transient victim 2 */ | |
| 122 | #define itv3 0x377 /* instruction cache transient victim 3 */ | |
| 123 | #define dnv0 0x390 /* data cache normal victim 0 */ | |
| 124 | #define dnv1 0x391 /* data cache normal victim 1 */ | |
| 125 | #define dnv2 0x392 /* data cache normal victim 2 */ | |
| 126 | #define dnv3 0x393 /* data cache normal victim 3 */ | |
| 127 | #define dtv0 0x394 /* data cache transient victim 0 */ | |
| 128 | #define dtv1 0x395 /* data cache transient victim 1 */ | |
| 129 | #define dtv2 0x396 /* data cache transient victim 2 */ | |
| 130 | #define dtv3 0x397 /* data cache transient victim 3 */ | |
| 131 | #define dvlim 0x398 /* data cache victim limit */ | |
| 132 | #define ivlim 0x399 /* instruction cache victim limit */ | |
| 133 | #define rstcfg 0x39b /* reset configuration */ | |
| 134 | #define dcdbtrl 0x39c /* data cache debug tag register low */ | |
| 135 | #define dcdbtrh 0x39d /* data cache debug tag register high */ | |
| 136 | #define icdbtrl 0x39e /* instruction cache debug tag register low */ | |
| 137 | #define icdbtrh 0x39f /* instruction cache debug tag register high */ | |
| 138 | #define mmucr 0x3b2 /* mmu control register */ | |
| 139 | #define ccr0 0x3b3 /* core configuration register 0 */ | |
| 1636d1c8 | 140 | #define ccr1 0x378 /* core configuration for 440x5 only */ |
| ba56f625 WD |
141 | #define icdbdr 0x3d3 /* instruction cache debug data register */ |
| 142 | #define dbdr 0x3f3 /* debug data register */ | |
| c00b5f85 WD |
143 | |
| 144 | /****************************************************************************** | |
| 145 | * DCRs & Related | |
| 146 | ******************************************************************************/ | |
| 147 | ||
| ba56f625 WD |
148 | /*----------------------------------------------------------------------------- |
| 149 | | Clocking Controller | |
| 150 | +----------------------------------------------------------------------------*/ | |
| ba56f625 WD |
151 | /* values for clkcfga register - indirect addressing of these regs */ |
| 152 | #define clk_clkukpd 0x0020 | |
| 153 | #define clk_pllc 0x0040 | |
| 154 | #define clk_plld 0x0060 | |
| 155 | #define clk_primad 0x0080 | |
| 156 | #define clk_primbd 0x00a0 | |
| 157 | #define clk_opbd 0x00c0 | |
| 158 | #define clk_perd 0x00e0 | |
| 159 | #define clk_mald 0x0100 | |
| 1636d1c8 | 160 | #define clk_spcid 0x0120 |
| ba56f625 WD |
161 | #define clk_icfg 0x0140 |
| 162 | ||
| 163 | /* 440gx sdr register definations */ | |
| ba56f625 WD |
164 | #define sdr_sdstp0 0x0020 /* */ |
| 165 | #define sdr_sdstp1 0x0021 /* */ | |
| 90e6f41c | 166 | #define SDR_PINSTP 0x0040 |
| ba56f625 WD |
167 | #define sdr_sdcs 0x0060 |
| 168 | #define sdr_ecid0 0x0080 | |
| 169 | #define sdr_ecid1 0x0081 | |
| 170 | #define sdr_ecid2 0x0082 | |
| 171 | #define sdr_jtag 0x00c0 | |
| 887e2ec9 | 172 | #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) |
| ba56f625 | 173 | #define sdr_ddrdl 0x00e0 |
| 887e2ec9 SR |
174 | #else |
| 175 | #define sdr_cfg 0x00e0 | |
| 176 | #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ | |
| 177 | #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ | |
| 178 | #define SDR_CFG_32BITS 0x00000000 /* 32 bits */ | |
| 179 | #define SDR_CFG_64BITS 0x01000000 /* 64 bits */ | |
| 180 | #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ | |
| 181 | #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ | |
| 182 | #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ | |
| 183 | #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ | |
| ba56f625 WD |
184 | #define sdr_ebc 0x0100 |
| 185 | #define sdr_uart0 0x0120 /* UART0 Config */ | |
| 186 | #define sdr_uart1 0x0121 /* UART1 Config */ | |
| c157d8e2 SR |
187 | #define sdr_uart2 0x0122 /* UART2 Config */ |
| 188 | #define sdr_uart3 0x0123 /* UART3 Config */ | |
| ba56f625 WD |
189 | #define sdr_cp440 0x0180 |
| 190 | #define sdr_xcr 0x01c0 | |
| 191 | #define sdr_xpllc 0x01c1 | |
| 192 | #define sdr_xplld 0x01c2 | |
| 193 | #define sdr_srst 0x0200 | |
| 194 | #define sdr_slpipe 0x0220 | |
| c157d8e2 SR |
195 | #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ |
| 196 | #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ | |
| ba56f625 WD |
197 | #define sdr_mirq0 0x0260 |
| 198 | #define sdr_mirq1 0x0261 | |
| 199 | #define sdr_maltbl 0x0280 | |
| 200 | #define sdr_malrbl 0x02a0 | |
| 201 | #define sdr_maltbs 0x02c0 | |
| 202 | #define sdr_malrbs 0x02e0 | |
| 6c5879f3 MB |
203 | #define sdr_pci0 0x0300 |
| 204 | #define sdr_usb0 0x0320 | |
| ba56f625 | 205 | #define sdr_cust0 0x4000 |
| ba56f625 | 206 | #define sdr_cust1 0x4002 |
| ba56f625 WD |
207 | #define sdr_pfc0 0x4100 /* Pin Function 0 */ |
| 208 | #define sdr_pfc1 0x4101 /* Pin Function 1 */ | |
| 209 | #define sdr_plbtr 0x4200 | |
| 210 | #define sdr_mfr 0x4300 /* SDR0_MFR reg */ | |
| 211 | ||
| bba68377 | 212 | #ifdef CONFIG_440GX |
| 6c5879f3 MB |
213 | #define sdr_amp 0x0240 |
| 214 | #define sdr_xpllc 0x01c1 | |
| 215 | #define sdr_xplld 0x01c2 | |
| 216 | #define sdr_xcr 0x01c0 | |
| 217 | #define sdr_sdstp2 0x4001 | |
| 218 | #define sdr_sdstp3 0x4003 | |
| bba68377 | 219 | #endif /* CONFIG_440GX */ |
| 6c5879f3 | 220 | |
| a11e0696 IL |
221 | /*----------------------------------------------------------------------------+ |
| 222 | | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). | |
| 223 | +----------------------------------------------------------------------------*/ | |
| 224 | #define CCR0_PRE 0x40000000 | |
| 225 | #define CCR0_CRPE 0x08000000 | |
| 226 | #define CCR0_DSTG 0x00200000 | |
| 227 | #define CCR0_DAPUIB 0x00100000 | |
| 228 | #define CCR0_DTB 0x00008000 | |
| 229 | #define CCR0_GICBT 0x00004000 | |
| 230 | #define CCR0_GDCBT 0x00002000 | |
| 231 | #define CCR0_FLSTA 0x00000100 | |
| 232 | #define CCR0_ICSLC_MASK 0x0000000C | |
| 233 | #define CCR0_ICSLT_MASK 0x00000003 | |
| 234 | #define CCR1_TCS_MASK 0x00000080 | |
| 235 | #define CCR1_TCS_INTCLK 0x00000000 | |
| 236 | #define CCR1_TCS_EXTCLK 0x00000080 | |
| 237 | #define MMUCR_SWOA 0x01000000 | |
| 238 | #define MMUCR_U1TE 0x00400000 | |
| 239 | #define MMUCR_U2SWOAE 0x00200000 | |
| 240 | #define MMUCR_DULXE 0x00800000 | |
| 241 | #define MMUCR_IULXE 0x00400000 | |
| 242 | #define MMUCR_STS 0x00100000 | |
| 243 | #define MMUCR_STID_MASK 0x000000FF | |
| a11e0696 | 244 | |
| 6c5879f3 MB |
245 | #ifdef CONFIG_440SPE |
| 246 | #undef sdr_sdstp2 | |
| 247 | #define sdr_sdstp2 0x0022 | |
| 248 | #undef sdr_sdstp3 | |
| 249 | #define sdr_sdstp3 0x0023 | |
| 250 | #define sdr_ddr0 0x00E1 | |
| 251 | #define sdr_uart2 0x0122 | |
| 252 | #define sdr_xcr0 0x01c0 | |
| 253 | /* #define sdr_xcr1 0x01c3 only one PCIX - SG */ | |
| 254 | /* #define sdr_xcr2 0x01c6 only one PCIX - SG */ | |
| 255 | #define sdr_xpllc0 0x01c1 | |
| 256 | #define sdr_xplld0 0x01c2 | |
| 257 | #define sdr_xpllc1 0x01c4 /*notRCW - SG */ | |
| 258 | #define sdr_xplld1 0x01c5 /*notRCW - SG */ | |
| 259 | #define sdr_xpllc2 0x01c7 /*notRCW - SG */ | |
| 260 | #define sdr_xplld2 0x01c8 /*notRCW - SG */ | |
| 261 | #define sdr_amp0 0x0240 | |
| 262 | #define sdr_amp1 0x0241 | |
| 263 | #define sdr_cust2 0x4004 | |
| 264 | #define sdr_cust3 0x4006 | |
| 265 | #define sdr_sdstp4 0x4001 | |
| 266 | #define sdr_sdstp5 0x4003 | |
| 267 | #define sdr_sdstp6 0x4005 | |
| 268 | #define sdr_sdstp7 0x4007 | |
| 269 | ||
| df294497 | 270 | #endif /* CONFIG_440SPE */ |
| 6c5879f3 | 271 | |
| c00b5f85 | 272 | /*----------------------------------------------------------------------------- |
| 6ed6ce62 | 273 | | External Bus Controller |
| c00b5f85 | 274 | +----------------------------------------------------------------------------*/ |
| ba56f625 WD |
275 | /* values for ebccfga register - indirect addressing of these regs */ |
| 276 | #define pb0cr 0x00 /* periph bank 0 config reg */ | |
| 277 | #define pb1cr 0x01 /* periph bank 1 config reg */ | |
| 278 | #define pb2cr 0x02 /* periph bank 2 config reg */ | |
| 279 | #define pb3cr 0x03 /* periph bank 3 config reg */ | |
| 280 | #define pb4cr 0x04 /* periph bank 4 config reg */ | |
| 281 | #define pb5cr 0x05 /* periph bank 5 config reg */ | |
| 282 | #define pb6cr 0x06 /* periph bank 6 config reg */ | |
| 283 | #define pb7cr 0x07 /* periph bank 7 config reg */ | |
| 284 | #define pb0ap 0x10 /* periph bank 0 access parameters */ | |
| 285 | #define pb1ap 0x11 /* periph bank 1 access parameters */ | |
| 286 | #define pb2ap 0x12 /* periph bank 2 access parameters */ | |
| 287 | #define pb3ap 0x13 /* periph bank 3 access parameters */ | |
| 288 | #define pb4ap 0x14 /* periph bank 4 access parameters */ | |
| 289 | #define pb5ap 0x15 /* periph bank 5 access parameters */ | |
| 290 | #define pb6ap 0x16 /* periph bank 6 access parameters */ | |
| 291 | #define pb7ap 0x17 /* periph bank 7 access parameters */ | |
| 292 | #define pbear 0x20 /* periph bus error addr reg */ | |
| 293 | #define pbesr 0x21 /* periph bus error status reg */ | |
| 294 | #define xbcfg 0x23 /* external bus configuration reg */ | |
| 4745acaa | 295 | #define EBC0_CFG 0x23 /* external bus configuration reg */ |
| 6ed6ce62 | 296 | #define xbcid 0x24 /* external bus core id reg */ |
| c00b5f85 | 297 | |
| 887e2ec9 SR |
298 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 299 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| c157d8e2 SR |
300 | |
| 301 | /* PLB4 to PLB3 Bridge OUT */ | |
| 302 | #define P4P3_DCR_BASE 0x020 | |
| 303 | #define p4p3_esr0_read (P4P3_DCR_BASE+0x0) | |
| 304 | #define p4p3_esr0_write (P4P3_DCR_BASE+0x1) | |
| 305 | #define p4p3_eadr (P4P3_DCR_BASE+0x2) | |
| 306 | #define p4p3_euadr (P4P3_DCR_BASE+0x3) | |
| 307 | #define p4p3_esr1_read (P4P3_DCR_BASE+0x4) | |
| 308 | #define p4p3_esr1_write (P4P3_DCR_BASE+0x5) | |
| 309 | #define p4p3_confg (P4P3_DCR_BASE+0x6) | |
| 310 | #define p4p3_pic (P4P3_DCR_BASE+0x7) | |
| 311 | #define p4p3_peir (P4P3_DCR_BASE+0x8) | |
| 312 | #define p4p3_rev (P4P3_DCR_BASE+0xA) | |
| 313 | ||
| 314 | /* PLB3 to PLB4 Bridge IN */ | |
| 315 | #define P3P4_DCR_BASE 0x030 | |
| 316 | #define p3p4_esr0_read (P3P4_DCR_BASE+0x0) | |
| 317 | #define p3p4_esr0_write (P3P4_DCR_BASE+0x1) | |
| 318 | #define p3p4_eadr (P3P4_DCR_BASE+0x2) | |
| 319 | #define p3p4_euadr (P3P4_DCR_BASE+0x3) | |
| 320 | #define p3p4_esr1_read (P3P4_DCR_BASE+0x4) | |
| 321 | #define p3p4_esr1_write (P3P4_DCR_BASE+0x5) | |
| 322 | #define p3p4_confg (P3P4_DCR_BASE+0x6) | |
| 323 | #define p3p4_pic (P3P4_DCR_BASE+0x7) | |
| 324 | #define p3p4_peir (P3P4_DCR_BASE+0x8) | |
| 325 | #define p3p4_rev (P3P4_DCR_BASE+0xA) | |
| 326 | ||
| 327 | /* PLB3 Arbiter */ | |
| 328 | #define PLB3_DCR_BASE 0x070 | |
| 329 | #define plb3_revid (PLB3_DCR_BASE+0x2) | |
| 330 | #define plb3_besr (PLB3_DCR_BASE+0x3) | |
| 331 | #define plb3_bear (PLB3_DCR_BASE+0x6) | |
| 332 | #define plb3_acr (PLB3_DCR_BASE+0x7) | |
| 333 | ||
| 334 | /* PLB4 Arbiter - PowerPC440EP Pass1 */ | |
| 335 | #define PLB4_DCR_BASE 0x080 | |
| a78bc443 | 336 | #define plb4_acr (PLB4_DCR_BASE+0x1) |
| c157d8e2 | 337 | #define plb4_revid (PLB4_DCR_BASE+0x2) |
| c157d8e2 SR |
338 | #define plb4_besr (PLB4_DCR_BASE+0x4) |
| 339 | #define plb4_bearl (PLB4_DCR_BASE+0x6) | |
| 340 | #define plb4_bearh (PLB4_DCR_BASE+0x7) | |
| 341 | ||
| a78bc443 SR |
342 | #define PLB4_ACR_WRP (0x80000000 >> 7) |
| 343 | ||
| 17f50f22 SR |
344 | /* Pin Function Control Register 1 */ |
| 345 | #define SDR0_PFC1 0x4101 | |
| 346 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
| 347 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
| 348 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
| 349 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
| 350 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
| 351 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
| 352 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
| 353 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
| 354 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
| 355 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
| 356 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
| 357 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
| 358 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | |
| 359 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
| 360 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
| 361 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | |
| 362 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
| 363 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
| 364 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | |
| 365 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | |
| 366 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
| 367 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | |
| 368 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | |
| 369 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | |
| 370 | ||
| 371 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | |
| 372 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | |
| 373 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | |
| 374 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | |
| 375 | ||
| 376 | /* USB Control Register */ | |
| 377 | #define SDR0_USB0 0x0320 | |
| 378 | #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ | |
| 379 | #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
| 380 | #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
| 381 | #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
| 382 | #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
| 383 | #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
| 384 | ||
| 887e2ec9 SR |
385 | /* Miscealleneaous Function Reg. */ |
| 386 | #define SDR0_MFR 0x4300 | |
| 387 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | |
| 388 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
| 389 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
| 390 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
| 391 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
| 392 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
| 393 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
| 394 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
| 395 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | |
| 396 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
| 397 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
| 398 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | |
| 399 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | |
| 400 | ||
| 401 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
| 402 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
| 403 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | |
| 404 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | |
| 405 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | |
| 406 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | |
| 407 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | |
| 408 | ||
| 8f24e063 | 409 | #define GPT0_COMP6 0x00000098 |
| 8f15d4ad YT |
410 | #define GPT0_COMP5 0x00000094 |
| 411 | #define GPT0_COMP4 0x00000090 | |
| 412 | #define GPT0_COMP3 0x0000008C | |
| 3d610186 YT |
413 | #define GPT0_COMP2 0x00000088 |
| 414 | #define GPT0_COMP1 0x00000084 | |
| 887e2ec9 | 415 | |
| eb0615bf YT |
416 | #define GPT0_MASK6 0x000000D8 |
| 417 | #define GPT0_MASK5 0x000000D4 | |
| 418 | #define GPT0_MASK4 0x000000D0 | |
| 419 | #define GPT0_MASK3 0x000000CC | |
| 420 | #define GPT0_MASK2 0x000000C8 | |
| 421 | #define GPT0_MASK1 0x000000C4 | |
| 422 | ||
| 887e2ec9 | 423 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| f780b833 | 424 | #define SDR0_USB2D0CR 0x0320 |
| 887e2ec9 SR |
425 | #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ |
| 426 | #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ | |
| 427 | #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ | |
| 428 | ||
| 429 | #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */ | |
| 430 | #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
| 431 | #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
| 432 | ||
| 433 | #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
| 434 | #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
| 435 | #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
| 436 | ||
| 437 | /* USB2 Host Control Register */ | |
| 438 | #define SDR0_USB2H0CR 0x0340 | |
| 439 | #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */ | |
| 440 | #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ | |
| 441 | #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ | |
| 442 | #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */ | |
| 443 | ||
| 444 | /* Pin Function Control Register 1 */ | |
| 445 | #define SDR0_PFC1 0x4101 | |
| 446 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
| 447 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
| 448 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
| 449 | ||
| 450 | #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */ | |
| 451 | #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */ | |
| 452 | #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | |
| 453 | #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */ | |
| 454 | #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */ | |
| 455 | #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */ | |
| 456 | #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */ | |
| 457 | #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */ | |
| 458 | ||
| 459 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
| 460 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
| 461 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
| 462 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
| 463 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
| 464 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
| 465 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
| 466 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
| 467 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
| 468 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | |
| 469 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
| 470 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
| 471 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | |
| 472 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
| 473 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
| 474 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | |
| 475 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | |
| 476 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
| 477 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | |
| 478 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | |
| 479 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | |
| 480 | ||
| 481 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | |
| 482 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | |
| 483 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | |
| 484 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | |
| 485 | ||
| 486 | /* Ethernet PLL Configuration Register */ | |
| 487 | #define SDR0_PFC2 0x4102 | |
| 488 | #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ | |
| 489 | #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */ | |
| 490 | #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ | |
| 491 | #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ | |
| 492 | ||
| 493 | #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ | |
| 494 | #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ | |
| 495 | #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | |
| 496 | #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ | |
| 497 | #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ | |
| 498 | #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ | |
| 499 | #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ | |
| 500 | #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ | |
| 501 | ||
| b765ffb7 SR |
502 | #define SDR0_PFC4 0x4104 |
| 503 | ||
| 887e2ec9 SR |
504 | /* USB2PHY0 Control Register */ |
| 505 | #define SDR0_USB2PHY0CR 0x4103 | |
| 506 | #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ | |
| 507 | #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ | |
| 508 | #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ | |
| 509 | ||
| 510 | #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ | |
| 511 | #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ | |
| 512 | #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ | |
| 513 | ||
| 514 | #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */ | |
| 515 | #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */ | |
| 516 | #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */ | |
| 517 | ||
| 518 | #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */ | |
| 519 | #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ | |
| 520 | #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ | |
| 521 | ||
| 522 | #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ | |
| 523 | #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ | |
| 524 | #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */ | |
| 525 | ||
| 526 | #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */ | |
| 527 | #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ | |
| 528 | #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */ | |
| 529 | ||
| 530 | #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ | |
| 531 | #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ | |
| 532 | #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */ | |
| 533 | ||
| 534 | #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */ | |
| 535 | #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */ | |
| 536 | #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */ | |
| 537 | ||
| 538 | #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */ | |
| 539 | #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */ | |
| 540 | #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */ | |
| 541 | ||
| 542 | #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ | |
| 543 | #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/ | |
| 544 | #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/ | |
| 545 | #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/ | |
| 546 | ||
| 547 | /* Miscealleneaous Function Reg. */ | |
| 548 | #define SDR0_MFR 0x4300 | |
| 549 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | |
| 550 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
| 551 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
| 552 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
| 553 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
| 554 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
| 555 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
| 556 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
| 557 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
| 558 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | |
| 559 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | |
| 560 | ||
| 561 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
| 562 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
| 563 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | |
| 564 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | |
| 565 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | |
| 566 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | |
| 567 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | |
| 568 | ||
| 569 | #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ | |
| 570 | ||
| 17f50f22 SR |
571 | /* CUST1 Customer Configuration Register1 */ |
| 572 | #define SDR0_CUST1 0x4002 | |
| 573 | #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ | |
| 574 | #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) | |
| 575 | #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) | |
| 576 | ||
| 577 | /* Pin Function Control Register 0 */ | |
| 578 | #define SDR0_PFC0 0x4100 | |
| 579 | #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ | |
| 580 | #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ | |
| 581 | #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ | |
| 582 | #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | |
| 583 | #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | |
| 584 | ||
| 585 | /* Pin Function Control Register 1 */ | |
| 586 | #define SDR0_PFC1 0x4101 | |
| 587 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
| 588 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
| 589 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
| 590 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
| 591 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
| 592 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
| 593 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
| 594 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
| 595 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
| 596 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
| 597 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
| 598 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
| 599 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ | |
| 600 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
| 601 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
| 602 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ | |
| 603 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
| 604 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
| 605 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ | |
| 606 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | |
| 607 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
| 608 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ | |
| 609 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ | |
| 610 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ | |
| 611 | ||
| 612 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ | |
| 613 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ | |
| 614 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ | |
| 615 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ | |
| 616 | ||
| 43c60992 SR |
617 | #endif /* 440EP || 440GR || 440EPX || 440GRX */ |
| 618 | ||
| 887e2ec9 | 619 | /*----------------------------------------------------------------------------- |
| 43c60992 | 620 | | L2 Cache |
| 887e2ec9 | 621 | +----------------------------------------------------------------------------*/ |
| 43c60992 SR |
622 | #if defined (CONFIG_440GX) || \ |
| 623 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
| 96e5fc0e FK |
624 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
| 625 | defined(CONFIG_460SX) | |
| 43c60992 SR |
626 | #define L2_CACHE_BASE 0x030 |
| 627 | #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ | |
| 628 | #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ | |
| 629 | #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ | |
| 630 | #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ | |
| 631 | #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ | |
| 632 | #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ | |
| 633 | #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ | |
| 634 | #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ | |
| 17f50f22 | 635 | |
| 43c60992 | 636 | #endif /* CONFIG_440GX */ |
| c157d8e2 | 637 | |
| c00b5f85 WD |
638 | /*----------------------------------------------------------------------------- |
| 639 | | Internal SRAM | |
| 640 | +----------------------------------------------------------------------------*/ | |
| 43c60992 SR |
641 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| 642 | #define ISRAM0_DCR_BASE 0x380 | |
| 643 | #else | |
| c00b5f85 | 644 | #define ISRAM0_DCR_BASE 0x020 |
| 43c60992 | 645 | #endif |
| ba56f625 WD |
646 | #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ |
| 647 | #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ | |
| 648 | #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ | |
| 649 | #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ | |
| 650 | #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ | |
| 651 | #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ | |
| 652 | #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ | |
| 653 | #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ | |
| 654 | #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ | |
| 655 | #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ | |
| 656 | #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ | |
| 657 | ||
| 43c60992 SR |
658 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 659 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 660 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
| 661 | /* CUST0 Customer Configuration Register0 */ | |
| 662 | #define SDR0_CUST0 0x4000 | |
| 663 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | |
| 664 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
| 665 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
| 666 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
| ba56f625 | 667 | |
| 43c60992 SR |
668 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ |
| 669 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
| 670 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
| 671 | ||
| 672 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
| 673 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | |
| 674 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | |
| 675 | ||
| 676 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
| 677 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | |
| 678 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 679 | ||
| 680 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
| 681 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) | |
| 682 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
| 683 | ||
| 684 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
| 685 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
| 686 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
| 687 | ||
| 688 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
| 689 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
| 690 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
| 691 | ||
| 692 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
| 693 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) | |
| 694 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) | |
| 695 | ||
| 696 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | |
| 697 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | |
| 698 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ | |
| 699 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | |
| 700 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | |
| 701 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | |
| 702 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | |
| 703 | #endif | |
| c00b5f85 WD |
704 | |
| 705 | /*----------------------------------------------------------------------------- | |
| 706 | | On-Chip Buses | |
| 707 | +----------------------------------------------------------------------------*/ | |
| 708 | /* TODO: as needed */ | |
| 709 | ||
| 710 | /*----------------------------------------------------------------------------- | |
| 711 | | Clocking, Power Management and Chip Control | |
| 712 | +----------------------------------------------------------------------------*/ | |
| 96e5fc0e FK |
713 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
| 714 | defined(CONFIG_460SX) | |
| 43c60992 SR |
715 | #define CNTRL_DCR_BASE 0x160 |
| 716 | #else | |
| c00b5f85 | 717 | #define CNTRL_DCR_BASE 0x0b0 |
| 43c60992 | 718 | #endif |
| 5b2052e5 | 719 | |
| 63153492 WD |
720 | #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ |
| 721 | #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ | |
| 722 | #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ | |
| c00b5f85 | 723 | |
| 63153492 WD |
724 | #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ |
| 725 | #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ | |
| 726 | #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ | |
| 727 | #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ | |
| c00b5f85 WD |
728 | |
| 729 | #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ | |
| 730 | #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ | |
| 731 | #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ | |
| 732 | #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ | |
| 733 | ||
| 5568e613 SR |
734 | #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ |
| 735 | ||
| 63153492 WD |
736 | #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ |
| 737 | #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ | |
| c00b5f85 | 738 | |
| c00b5f85 WD |
739 | /*----------------------------------------------------------------------------- |
| 740 | | DMA | |
| 741 | +----------------------------------------------------------------------------*/ | |
| 43c60992 SR |
742 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 743 | #define DMA_DCR_BASE 0x200 | |
| 744 | #else | |
| c00b5f85 | 745 | #define DMA_DCR_BASE 0x100 |
| 43c60992 | 746 | #endif |
| ba56f625 WD |
747 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
| 748 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
| 749 | #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ | |
| 750 | #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ | |
| 751 | #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ | |
| 752 | #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ | |
| c00b5f85 WD |
753 | #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ |
| 754 | #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ | |
| ba56f625 WD |
755 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ |
| 756 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
| 757 | #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ | |
| 758 | #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ | |
| 759 | #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ | |
| 760 | #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ | |
| c00b5f85 WD |
761 | #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ |
| 762 | #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ | |
| ba56f625 WD |
763 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ |
| 764 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
| 765 | #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ | |
| 766 | #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ | |
| 767 | #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ | |
| 768 | #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ | |
| c00b5f85 WD |
769 | #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ |
| 770 | #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ | |
| ba56f625 WD |
771 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ |
| 772 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ | |
| 773 | #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ | |
| 774 | #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ | |
| 775 | #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ | |
| 776 | #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ | |
| c00b5f85 WD |
777 | #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ |
| 778 | #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ | |
| ba56f625 WD |
779 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ |
| 780 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
| 781 | #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ | |
| 782 | #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ | |
| c00b5f85 WD |
783 | |
| 784 | /*----------------------------------------------------------------------------- | |
| 785 | | Memory Access Layer | |
| 786 | +----------------------------------------------------------------------------*/ | |
| 787 | #define MAL_DCR_BASE 0x180 | |
| ba56f625 WD |
788 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ |
| 789 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ | |
| 790 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | |
| 791 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | |
| 792 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ | |
| c00b5f85 WD |
793 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ |
| 794 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | |
| ba56f625 WD |
795 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ |
| 796 | #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ | |
| 797 | #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ | |
| 798 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ | |
| c00b5f85 WD |
799 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ |
| 800 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | |
| ba56f625 WD |
801 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ |
| 802 | #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ | |
| 803 | #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ | |
| c00b5f85 WD |
804 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ |
| 805 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ | |
| ba56f625 WD |
806 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ |
| 807 | #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ | |
| c00b5f85 WD |
808 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| 809 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ | |
| ba56f625 WD |
810 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| 811 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ | |
| 43c60992 SR |
812 | #if defined(CONFIG_440GX) || \ |
| 813 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
| 814 | #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ | |
| 815 | #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ | |
| 816 | #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ | |
| 4c9e8557 SR |
817 | #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ |
| 818 | #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ | |
| ba56f625 WD |
819 | #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ |
| 820 | #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ | |
| 43c60992 | 821 | #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ |
| 4c9e8557 SR |
822 | #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ |
| 823 | #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ | |
| 846b0dd2 | 824 | #endif /* CONFIG_440GX */ |
| ba56f625 | 825 | |
| 0e6d798c | 826 | /*-----------------------------------------------------------------------------+ |
| 6e7fb6ea | 827 | | SDR0 Bit Settings |
| 0e6d798c | 828 | +-----------------------------------------------------------------------------*/ |
| df294497 SR |
829 | #if defined(CONFIG_440SP) |
| 830 | #define SDR0_SRST 0x0200 | |
| 831 | ||
| 832 | #define SDR0_DDR0 0x00E1 | |
| 833 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
| 834 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
| 835 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
| 836 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
| 837 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
| 838 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
| 839 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
| 840 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
| 841 | #endif | |
| 842 | ||
| 96e5fc0e | 843 | #if defined(CONFIG_440SPE) || defined(CONFIG_460SX) |
| 6c5879f3 MB |
844 | #define SDR0_CP440 0x0180 |
| 845 | #define SDR0_CP440_ERPN_MASK 0x30000000 | |
| 846 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 | |
| 847 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 | |
| 848 | #define SDR0_CP440_ERPN_EBC 0x10000000 | |
| 849 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 | |
| 850 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 | |
| 851 | #define SDR0_CP440_ERPN_PCI 0x20000000 | |
| 852 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 | |
| 853 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 | |
| 854 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
| 855 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
| 856 | #define SDR0_CP440_NTO1_MASK 0x00000002 | |
| 857 | #define SDR0_CP440_NTO1_NTOP 0x00000000 | |
| 858 | #define SDR0_CP440_NTO1_NTO1 0x00000002 | |
| 859 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
| 860 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
| 6c5879f3 MB |
861 | |
| 862 | #define SDR0_SDSTP0 0x0020 | |
| 863 | #define SDR0_SDSTP0_ENG_MASK 0x80000000 | |
| 864 | #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 | |
| 865 | #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 | |
| 866 | #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
| 867 | #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
| 868 | #define SDR0_SDSTP0_SRC_MASK 0x40000000 | |
| 869 | #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 | |
| 870 | #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 | |
| 871 | #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
| 872 | #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
| 873 | #define SDR0_SDSTP0_SEL_MASK 0x38000000 | |
| 874 | #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 | |
| 875 | #define SDR0_SDSTP0_SEL_CPU 0x08000000 | |
| 876 | #define SDR0_SDSTP0_SEL_EBC 0x28000000 | |
| 877 | #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) | |
| 878 | #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) | |
| 879 | #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 | |
| 880 | #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) | |
| 881 | #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) | |
| 882 | #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 | |
| 883 | #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | |
| 884 | #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) | |
| 885 | #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 | |
| 886 | #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) | |
| 887 | #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) | |
| 888 | #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 | |
| 889 | #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) | |
| 890 | #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) | |
| 891 | #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C | |
| 892 | #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) | |
| 893 | #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) | |
| 894 | #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 | |
| 895 | #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) | |
| 896 | #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) | |
| 897 | ||
| 898 | ||
| 899 | #define SDR0_SDSTP1 0x0021 | |
| 900 | #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 | |
| 901 | #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) | |
| 902 | #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) | |
| 903 | #define SDR0_SDSTP1_PERDV0_MASK 0x03000000 | |
| 904 | #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | |
| 905 | #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) | |
| 906 | #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 | |
| 907 | #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) | |
| 908 | #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
| 909 | #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 | |
| 910 | #define SDR0_SDSTP1_DDR1_MODE 0x00100000 | |
| 911 | #define SDR0_SDSTP1_DDR2_MODE 0x00200000 | |
| 912 | #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) | |
| 913 | #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) | |
| 914 | #define SDR0_SDSTP1_ERPN_MASK 0x00080000 | |
| 915 | #define SDR0_SDSTP1_ERPN_EBC 0x00000000 | |
| 916 | #define SDR0_SDSTP1_ERPN_PCI 0x00080000 | |
| 917 | #define SDR0_SDSTP1_PAE_MASK 0x00040000 | |
| 918 | #define SDR0_SDSTP1_PAE_DISABLE 0x00000000 | |
| 919 | #define SDR0_SDSTP1_PAE_ENABLE 0x00040000 | |
| 920 | #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | |
| 921 | #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | |
| 922 | #define SDR0_SDSTP1_PHCE_MASK 0x00020000 | |
| 923 | #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 | |
| 924 | #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 | |
| 925 | #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | |
| 926 | #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | |
| 927 | #define SDR0_SDSTP1_PISE_MASK 0x00010000 | |
| 928 | #define SDR0_SDSTP1_PISE_DISABLE 0x00000000 | |
| 929 | #define SDR0_SDSTP1_PISE_ENABLE 0x00001000 | |
| 930 | #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | |
| 931 | #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | |
| 932 | #define SDR0_SDSTP1_PCWE_MASK 0x00008000 | |
| 933 | #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 | |
| 934 | #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 | |
| 935 | #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | |
| 936 | #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | |
| 937 | #define SDR0_SDSTP1_PPIM_MASK 0x00007800 | |
| 938 | #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | |
| 939 | #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | |
| 940 | #define SDR0_SDSTP1_PR64E_MASK 0x00000400 | |
| 941 | #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 | |
| 942 | #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 | |
| 943 | #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) | |
| 944 | #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) | |
| 945 | #define SDR0_SDSTP1_PXFS_MASK 0x00000300 | |
| 946 | #define SDR0_SDSTP1_PXFS_100_133 0x00000000 | |
| 947 | #define SDR0_SDSTP1_PXFS_66_100 0x00000100 | |
| 948 | #define SDR0_SDSTP1_PXFS_50_66 0x00000200 | |
| 949 | #define SDR0_SDSTP1_PXFS_0_50 0x00000300 | |
| 950 | #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | |
| 951 | #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | |
| 952 | #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ | |
| 953 | #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ | |
| 954 | #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ | |
| 955 | #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ | |
| 956 | #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 | |
| 957 | #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 | |
| 958 | #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ | |
| 959 | #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ | |
| 960 | #define SDR0_SDSTP1_ETH_MASK 0x00000004 | |
| 961 | #define SDR0_SDSTP1_ETH_10_100 0x00000000 | |
| 962 | #define SDR0_SDSTP1_ETH_GIGA 0x00000004 | |
| 963 | #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) | |
| 964 | #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) | |
| 965 | #define SDR0_SDSTP1_NTO1_MASK 0x00000001 | |
| 966 | #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 | |
| 967 | #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 | |
| 968 | #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) | |
| 969 | #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) | |
| 970 | ||
| 971 | #define SDR0_SDSTP2 0x0022 | |
| 972 | #define SDR0_SDSTP2_P1AE_MASK 0x80000000 | |
| 973 | #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 | |
| 974 | #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 | |
| 975 | #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
| 976 | #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
| 977 | #define SDR0_SDSTP2_P1HCE_MASK 0x40000000 | |
| 978 | #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 | |
| 979 | #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 | |
| 980 | #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
| 981 | #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
| 982 | #define SDR0_SDSTP2_P1ISE_MASK 0x20000000 | |
| 983 | #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 | |
| 984 | #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 | |
| 985 | #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
| 986 | #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
| 987 | #define SDR0_SDSTP2_P1CWE_MASK 0x10000000 | |
| 988 | #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 | |
| 989 | #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 | |
| 990 | #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
| 991 | #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
| 992 | #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 | |
| 993 | #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
| 994 | #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 995 | #define SDR0_SDSTP2_P1R64E_MASK 0x00800000 | |
| 996 | #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 | |
| 997 | #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 | |
| 998 | #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
| 999 | #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
| 1000 | #define SDR0_SDSTP2_P1XFS_MASK 0x00600000 | |
| 1001 | #define SDR0_SDSTP2_P1XFS_100_133 0x00000000 | |
| 1002 | #define SDR0_SDSTP2_P1XFS_66_100 0x00200000 | |
| 1003 | #define SDR0_SDSTP2_P1XFS_50_66 0x00400000 | |
| 1004 | #define SDR0_SDSTP2_P1XFS_0_50 0x00600000 | |
| 1005 | #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
| 1006 | #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
| 1007 | #define SDR0_SDSTP2_P2AE_MASK 0x00040000 | |
| 1008 | #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 | |
| 1009 | #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 | |
| 1010 | #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | |
| 1011 | #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | |
| 1012 | #define SDR0_SDSTP2_P2HCE_MASK 0x00020000 | |
| 1013 | #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 | |
| 1014 | #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 | |
| 1015 | #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | |
| 1016 | #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | |
| 1017 | #define SDR0_SDSTP2_P2ISE_MASK 0x00010000 | |
| 1018 | #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 | |
| 1019 | #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 | |
| 1020 | #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | |
| 1021 | #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | |
| 1022 | #define SDR0_SDSTP2_P2CWE_MASK 0x00008000 | |
| 1023 | #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 | |
| 1024 | #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 | |
| 1025 | #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | |
| 1026 | #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | |
| 1027 | #define SDR0_SDSTP2_P2PIM_MASK 0x00007800 | |
| 1028 | #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | |
| 1029 | #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | |
| 1030 | #define SDR0_SDSTP2_P2XFS_MASK 0x00000300 | |
| 1031 | #define SDR0_SDSTP2_P2XFS_100_133 0x00000000 | |
| 1032 | #define SDR0_SDSTP2_P2XFS_66_100 0x00000100 | |
| 1033 | #define SDR0_SDSTP2_P2XFS_50_66 0x00000200 | |
| 1034 | #define SDR0_SDSTP2_P2XFS_0_50 0x00000100 | |
| 1035 | #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | |
| 1036 | #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | |
| 1037 | ||
| 1038 | #define SDR0_SDSTP3 0x0023 | |
| 1039 | ||
| 1040 | #define SDR0_PINSTP 0x0040 | |
| 1041 | #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ | |
| 1042 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */ | |
| 1043 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */ | |
| 1044 | #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */ | |
| 1045 | #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */ | |
| 1046 | #define SDR0_SDCS 0x0060 | |
| 1047 | #define SDR0_ECID0 0x0080 | |
| 1048 | #define SDR0_ECID1 0x0081 | |
| 1049 | #define SDR0_ECID2 0x0082 | |
| 1050 | #define SDR0_JTAG 0x00C0 | |
| 1051 | ||
| 1052 | #define SDR0_DDR0 0x00E1 | |
| 1053 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
| 1054 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
| 1055 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
| 1056 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
| 1057 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
| 1058 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
| 1059 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
| 1060 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
| 1061 | ||
| 1062 | #define SDR0_UART0 0x0120 | |
| 1063 | #define SDR0_UART1 0x0121 | |
| 1064 | #define SDR0_UART2 0x0122 | |
| 1065 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | |
| 1066 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | |
| 1067 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | |
| 1068 | #define SDR0_UARTX_UXEC_INT 0x00000000 | |
| 1069 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | |
| 1070 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | |
| 1071 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | |
| 1072 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | |
| 1073 | ||
| 1074 | #define SDR0_CP440 0x0180 | |
| 1075 | #define SDR0_CP440_ERPN_MASK 0x30000000 | |
| 1076 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 | |
| 1077 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 | |
| 1078 | #define SDR0_CP440_ERPN_EBC 0x10000000 | |
| 1079 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 | |
| 1080 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 | |
| 1081 | #define SDR0_CP440_ERPN_PCI 0x20000000 | |
| 1082 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 | |
| 1083 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 | |
| 1084 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
| 1085 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
| 1086 | #define SDR0_CP440_NTO1_MASK 0x00000002 | |
| 1087 | #define SDR0_CP440_NTO1_NTOP 0x00000000 | |
| 1088 | #define SDR0_CP440_NTO1_NTO1 0x00000002 | |
| 1089 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
| 1090 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
| 1091 | ||
| 1092 | #define SDR0_XCR0 0x01C0 | |
| 1093 | #define SDR0_XCR1 0x01C3 | |
| 1094 | #define SDR0_XCR2 0x01C6 | |
| 1095 | #define SDR0_XCRn_PAE_MASK 0x80000000 | |
| 1096 | #define SDR0_XCRn_PAE_DISABLE 0x00000000 | |
| 1097 | #define SDR0_XCRn_PAE_ENABLE 0x80000000 | |
| 1098 | #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
| 1099 | #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
| 1100 | #define SDR0_XCRn_PHCE_MASK 0x40000000 | |
| 1101 | #define SDR0_XCRn_PHCE_DISABLE 0x00000000 | |
| 1102 | #define SDR0_XCRn_PHCE_ENABLE 0x40000000 | |
| 1103 | #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
| 1104 | #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
| 1105 | #define SDR0_XCRn_PISE_MASK 0x20000000 | |
| 1106 | #define SDR0_XCRn_PISE_DISABLE 0x00000000 | |
| 1107 | #define SDR0_XCRn_PISE_ENABLE 0x20000000 | |
| 1108 | #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
| 1109 | #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
| 1110 | #define SDR0_XCRn_PCWE_MASK 0x10000000 | |
| 1111 | #define SDR0_XCRn_PCWE_DISABLE 0x00000000 | |
| 1112 | #define SDR0_XCRn_PCWE_ENABLE 0x10000000 | |
| 1113 | #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
| 1114 | #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
| 1115 | #define SDR0_XCRn_PPIM_MASK 0x0F000000 | |
| 1116 | #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
| 1117 | #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 1118 | #define SDR0_XCRn_PR64E_MASK 0x00800000 | |
| 1119 | #define SDR0_XCRn_PR64E_DISABLE 0x00000000 | |
| 1120 | #define SDR0_XCRn_PR64E_ENABLE 0x00800000 | |
| 1121 | #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
| 1122 | #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
| 1123 | #define SDR0_XCRn_PXFS_MASK 0x00600000 | |
| 1124 | #define SDR0_XCRn_PXFS_100_133 0x00000000 | |
| 1125 | #define SDR0_XCRn_PXFS_66_100 0x00200000 | |
| 1126 | #define SDR0_XCRn_PXFS_50_66 0x00400000 | |
| 1127 | #define SDR0_XCRn_PXFS_0_33 0x00600000 | |
| 1128 | #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
| 1129 | #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
| 1130 | ||
| 1131 | #define SDR0_XPLLC0 0x01C1 | |
| 1132 | #define SDR0_XPLLD0 0x01C2 | |
| 1133 | #define SDR0_XPLLC1 0x01C4 | |
| 1134 | #define SDR0_XPLLD1 0x01C5 | |
| 1135 | #define SDR0_XPLLC2 0x01C7 | |
| 1136 | #define SDR0_XPLLD2 0x01C8 | |
| 1137 | #define SDR0_SRST 0x0200 | |
| 1138 | #define SDR0_SLPIPE 0x0220 | |
| 1139 | ||
| 1140 | #define SDR0_AMP0 0x0240 | |
| 1141 | #define SDR0_AMP0_PRIORITY 0xFFFF0000 | |
| 1142 | #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 | |
| 1143 | #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF | |
| 1144 | ||
| 1145 | #define SDR0_AMP1 0x0241 | |
| 1146 | #define SDR0_AMP1_PRIORITY 0xFC000000 | |
| 1147 | #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 | |
| 1148 | #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF | |
| 1149 | ||
| 1150 | #define SDR0_MIRQ0 0x0260 | |
| 1151 | #define SDR0_MIRQ1 0x0261 | |
| 1152 | #define SDR0_MALTBL 0x0280 | |
| 1153 | #define SDR0_MALRBL 0x02A0 | |
| 1154 | #define SDR0_MALTBS 0x02C0 | |
| 1155 | #define SDR0_MALRBS 0x02E0 | |
| 1156 | ||
| 1157 | /* Reserved for Customer Use */ | |
| 1158 | #define SDR0_CUST0 0x4000 | |
| 1159 | #define SDR0_CUST0_AUTONEG_MASK 0x8000000 | |
| 1160 | #define SDR0_CUST0_NO_AUTONEG 0x0000000 | |
| 1161 | #define SDR0_CUST0_AUTONEG 0x8000000 | |
| 1162 | #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 | |
| 1163 | #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 | |
| 1164 | #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 | |
| 1165 | #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 | |
| 1166 | #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 | |
| 1167 | #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 | |
| 1168 | #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 | |
| 1169 | ||
| 1170 | #define SDR0_SDSTP4 0x4001 | |
| 1171 | #define SDR0_CUST1 0x4002 | |
| 1172 | #define SDR0_SDSTP5 0x4003 | |
| 1173 | #define SDR0_CUST2 0x4004 | |
| 1174 | #define SDR0_SDSTP6 0x4005 | |
| 1175 | #define SDR0_CUST3 0x4006 | |
| 1176 | #define SDR0_SDSTP7 0x4007 | |
| 1177 | ||
| 1178 | #define SDR0_PFC0 0x4100 | |
| 1179 | #define SDR0_PFC0_GPIO_0 0x80000000 | |
| 1180 | #define SDR0_PFC0_PCIX0REQ2_N 0x00000000 | |
| 1181 | #define SDR0_PFC0_GPIO_1 0x40000000 | |
| 1182 | #define SDR0_PFC0_PCIX0REQ3_N 0x00000000 | |
| 1183 | #define SDR0_PFC0_GPIO_2 0x20000000 | |
| 1184 | #define SDR0_PFC0_PCIX0GNT2_N 0x00000000 | |
| 1185 | #define SDR0_PFC0_GPIO_3 0x10000000 | |
| 1186 | #define SDR0_PFC0_PCIX0GNT3_N 0x00000000 | |
| 1187 | #define SDR0_PFC0_GPIO_4 0x08000000 | |
| 1188 | #define SDR0_PFC0_PCIX1REQ2_N 0x00000000 | |
| 1189 | #define SDR0_PFC0_GPIO_5 0x04000000 | |
| 1190 | #define SDR0_PFC0_PCIX1REQ3_N 0x00000000 | |
| 1191 | #define SDR0_PFC0_GPIO_6 0x02000000 | |
| 1192 | #define SDR0_PFC0_PCIX1GNT2_N 0x00000000 | |
| 1193 | #define SDR0_PFC0_GPIO_7 0x01000000 | |
| 1194 | #define SDR0_PFC0_PCIX1GNT3_N 0x00000000 | |
| 1195 | #define SDR0_PFC0_GPIO_8 0x00800000 | |
| 1196 | #define SDR0_PFC0_PERREADY 0x00000000 | |
| 1197 | #define SDR0_PFC0_GPIO_9 0x00400000 | |
| 1198 | #define SDR0_PFC0_PERCS1_N 0x00000000 | |
| 1199 | #define SDR0_PFC0_GPIO_10 0x00200000 | |
| 1200 | #define SDR0_PFC0_PERCS2_N 0x00000000 | |
| 1201 | #define SDR0_PFC0_GPIO_11 0x00100000 | |
| 1202 | #define SDR0_PFC0_IRQ0 0x00000000 | |
| 1203 | #define SDR0_PFC0_GPIO_12 0x00080000 | |
| 1204 | #define SDR0_PFC0_IRQ1 0x00000000 | |
| 1205 | #define SDR0_PFC0_GPIO_13 0x00040000 | |
| 1206 | #define SDR0_PFC0_IRQ2 0x00000000 | |
| 1207 | #define SDR0_PFC0_GPIO_14 0x00020000 | |
| 1208 | #define SDR0_PFC0_IRQ3 0x00000000 | |
| 1209 | #define SDR0_PFC0_GPIO_15 0x00010000 | |
| 1210 | #define SDR0_PFC0_IRQ4 0x00000000 | |
| 1211 | #define SDR0_PFC0_GPIO_16 0x00008000 | |
| 1212 | #define SDR0_PFC0_IRQ5 0x00000000 | |
| 1213 | #define SDR0_PFC0_GPIO_17 0x00004000 | |
| 1214 | #define SDR0_PFC0_PERBE0_N 0x00000000 | |
| 1215 | #define SDR0_PFC0_GPIO_18 0x00002000 | |
| 1216 | #define SDR0_PFC0_PCI0GNT0_N 0x00000000 | |
| 1217 | #define SDR0_PFC0_GPIO_19 0x00001000 | |
| 1218 | #define SDR0_PFC0_PCI0GNT1_N 0x00000000 | |
| 1219 | #define SDR0_PFC0_GPIO_20 0x00000800 | |
| 1220 | #define SDR0_PFC0_PCI0REQ0_N 0x00000000 | |
| 1221 | #define SDR0_PFC0_GPIO_21 0x00000400 | |
| 1222 | #define SDR0_PFC0_PCI0REQ1_N 0x00000000 | |
| 1223 | #define SDR0_PFC0_GPIO_22 0x00000200 | |
| 1224 | #define SDR0_PFC0_PCI1GNT0_N 0x00000000 | |
| 1225 | #define SDR0_PFC0_GPIO_23 0x00000100 | |
| 1226 | #define SDR0_PFC0_PCI1GNT1_N 0x00000000 | |
| 1227 | #define SDR0_PFC0_GPIO_24 0x00000080 | |
| 1228 | #define SDR0_PFC0_PCI1REQ0_N 0x00000000 | |
| 1229 | #define SDR0_PFC0_GPIO_25 0x00000040 | |
| 1230 | #define SDR0_PFC0_PCI1REQ1_N 0x00000000 | |
| 1231 | #define SDR0_PFC0_GPIO_26 0x00000020 | |
| 1232 | #define SDR0_PFC0_PCI2GNT0_N 0x00000000 | |
| 1233 | #define SDR0_PFC0_GPIO_27 0x00000010 | |
| 1234 | #define SDR0_PFC0_PCI2GNT1_N 0x00000000 | |
| 1235 | #define SDR0_PFC0_GPIO_28 0x00000008 | |
| 1236 | #define SDR0_PFC0_PCI2REQ0_N 0x00000000 | |
| 1237 | #define SDR0_PFC0_GPIO_29 0x00000004 | |
| 1238 | #define SDR0_PFC0_PCI2REQ1_N 0x00000000 | |
| 1239 | #define SDR0_PFC0_GPIO_30 0x00000002 | |
| 1240 | #define SDR0_PFC0_UART1RX 0x00000000 | |
| 1241 | #define SDR0_PFC0_GPIO_31 0x00000001 | |
| 1242 | #define SDR0_PFC0_UART1TX 0x00000000 | |
| 1243 | ||
| 1244 | #define SDR0_PFC1 0x4101 | |
| 1245 | #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 | |
| 1246 | #define SDR0_PFC1_UART1_DSR_DTR 0x00000000 | |
| 1247 | #define SDR0_PFC1_UART1_CTS_RTS 0x02000000 | |
| 1248 | #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 | |
| 1249 | #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 | |
| 1250 | #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 | |
| 1251 | #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 | |
| 1252 | #define SDR0_PFC1_ETH_10_100 0x00000000 | |
| 1253 | #define SDR0_PFC1_ETH_GIGA 0x00200000 | |
| 1254 | #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) | |
| 1255 | #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | |
| 1256 | #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ | |
| 1257 | #define SDR0_PFC1_CPU_NO_TRACE 0x00000000 | |
| 1258 | #define SDR0_PFC1_CPU_TRACE 0x00080000 | |
| 1259 | #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */ | |
| 1260 | #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */ | |
| 1261 | ||
| 1262 | #define SDR0_MFR 0x4300 | |
| 1263 | #endif /* CONFIG_440SPE */ | |
| 1264 | ||
| 43c60992 SR |
1265 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 1266 | /* Pin Function Control Register 0 (SDR0_PFC0) */ | |
| 1267 | #define SDR0_PFC0 0x4100 | |
| 1268 | #define SDR0_PFC0_DBG 0x00008000 /* debug enable */ | |
| 1269 | #define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */ | |
| 1270 | #define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */ | |
| 1271 | #define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */ | |
| 1272 | #define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */ | |
| 1273 | #define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */ | |
| 1274 | #define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */ | |
| 1275 | #define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */ | |
| 1276 | #define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */ | |
| 1277 | #define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */ | |
| 1278 | #define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */ | |
| 1279 | #define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */ | |
| 1280 | #define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */ | |
| 1281 | #define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */ | |
| 1282 | #define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */ | |
| 1283 | #define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */ | |
| 1284 | ||
| 1285 | /* Pin Function Control Register 1 (SDR0_PFC1) */ | |
| 1286 | #define SDR0_PFC1 0x4101 | |
| 1287 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
| 1288 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
| 1289 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
| 1290 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
| 1291 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
| 1292 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
| 1293 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
| 1294 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/ | |
| 1295 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/ | |
| 1296 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
| 1297 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
| 1298 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
| 1299 | ||
| 1300 | /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ | |
| 1301 | #define SDR0_ETH_PLL 0x4102 | |
| 1302 | #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ | |
| 1303 | #define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */ | |
| 1304 | #define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */ | |
| 1305 | #define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */ | |
| 1306 | #define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */ | |
| 1307 | #define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16) | |
| 1308 | #define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */ | |
| 1309 | #define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8) | |
| 1310 | #define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */ | |
| 1311 | #define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4) | |
| 1312 | #define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */ | |
| 1313 | #define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f) | |
| 1314 | ||
| 1315 | /* Ethernet Configuration Register (SDR0_ETH_CFG) */ | |
| 1316 | #define SDR0_ETH_CFG 0x4103 | |
| 1317 | #define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */ | |
| 1318 | #define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */ | |
| 1319 | #define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */ | |
| 1320 | #define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */ | |
| 1321 | #define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */ | |
| 1322 | #define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */ | |
| 1323 | #define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */ | |
| 1324 | #define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */ | |
| 1325 | #define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */ | |
| 1326 | #define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */ | |
| 1327 | #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */ | |
| 1328 | #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */ | |
| 1329 | #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */ | |
| 1330 | #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */ | |
| 1331 | #define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */ | |
| 1332 | #define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */ | |
| 1333 | #define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */ | |
| 1334 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */ | |
| 1335 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */ | |
| 1336 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */ | |
| 1337 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */ | |
| 1338 | #define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */ | |
| 1339 | #define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */ | |
| 1340 | #define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */ | |
| 1341 | #define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */ | |
| 1342 | #define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */ | |
| 1343 | #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */ | |
| 1344 | #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */ | |
| 1345 | ||
| 1346 | #define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4 | |
| 1347 | #define SDR0_ETH_CFG_ZMII_MII_MODE 0x00 | |
| 1348 | #define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01 | |
| 1349 | #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 | |
| 1350 | #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 | |
| 1351 | ||
| 1352 | /* Miscealleneaous Function Reg. (SDR0_MFR) */ | |
| 1353 | #define SDR0_MFR 0x4300 | |
| 1354 | #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */ | |
| 1355 | #define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */ | |
| 1356 | #define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */ | |
| 1357 | #define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */ | |
| 1358 | #define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */ | |
| 1359 | #define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */ | |
| 1360 | #define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */ | |
| 1361 | #define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */ | |
| 1362 | #define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */ | |
| 1363 | #define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */ | |
| 1364 | #define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */ | |
| 1365 | #define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */ | |
| 1366 | #define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */ | |
| 1367 | #define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */ | |
| 1368 | #define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */ | |
| 1369 | #define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */ | |
| 1370 | #define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */ | |
| 1371 | #define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */ | |
| 1372 | #define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */ | |
| 1373 | #define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */ | |
| 1374 | ||
| 1375 | /* EMACx TX Status Register (SDR0_EMACxTXST)*/ | |
| 1376 | #define SDR0_EMAC0TXST 0x4400 | |
| 1377 | #define SDR0_EMAC1TXST 0x4401 | |
| 1378 | #define SDR0_EMAC2TXST 0x4402 | |
| 1379 | #define SDR0_EMAC3TXST 0x4403 | |
| 1380 | ||
| 1381 | #define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ | |
| 1382 | #define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ | |
| 1383 | #define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ | |
| 1384 | #define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ | |
| 1385 | #define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ | |
| 1386 | #define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */ | |
| 1387 | #define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ | |
| 1388 | #define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ | |
| 1389 | #define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ | |
| 1390 | #define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ | |
| 1391 | #define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ | |
| 1392 | #define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ | |
| 1393 | #define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ | |
| 1394 | #define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ | |
| 1395 | #define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ | |
| 1396 | #define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ | |
| 1397 | #define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ | |
| 1398 | #define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ | |
| 1399 | #define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ | |
| 1400 | #define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ | |
| 1401 | #define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ | |
| 1402 | #define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ | |
| 1403 | #define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ | |
| 1404 | #define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ | |
| 1405 | ||
| 1406 | /* EMACx RX Status Register (SDR0_EMACxRXST)*/ | |
| 1407 | #define SDR0_EMAC0RXST 0x4404 | |
| 1408 | #define SDR0_EMAC1RXST 0x4405 | |
| 1409 | #define SDR0_EMAC2RXST 0x4406 | |
| 1410 | #define SDR0_EMAC3RXST 0x4407 | |
| 1411 | ||
| 1412 | #define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */ | |
| 1413 | #define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */ | |
| 1414 | #define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */ | |
| 1415 | #define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */ | |
| 1416 | #define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */ | |
| 1417 | #define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23) | |
| 1418 | #define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */ | |
| 1419 | #define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */ | |
| 1420 | #define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */ | |
| 1421 | #define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */ | |
| 1422 | #define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/ | |
| 1423 | #define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/ | |
| 1424 | #define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */ | |
| 1425 | #define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */ | |
| 1426 | #define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */ | |
| 1427 | #define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */ | |
| 1428 | #define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */ | |
| 1429 | #define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */ | |
| 1430 | #define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */ | |
| 1431 | #define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */ | |
| 1432 | #define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */ | |
| 1433 | #define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */ | |
| 1434 | #define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */ | |
| 1435 | #define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */ | |
| 1436 | #define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */ | |
| 1437 | #define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */ | |
| 1438 | #define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ | |
| 1439 | #define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */ | |
| 1440 | ||
| 1441 | /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/ | |
| 1442 | #define SDR0_EMAC0REJCNT 0x4408 | |
| 1443 | #define SDR0_EMAC1REJCNT 0x4409 | |
| 1444 | #define SDR0_EMAC2REJCNT 0x440A | |
| 1445 | #define SDR0_EMAC3REJCNT 0x440B | |
| 1446 | ||
| 1447 | #define SDR0_DDR0 0x00E1 | |
| 1448 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
| 1449 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
| 1450 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
| 1451 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
| 1452 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
| 1453 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
| 1454 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
| 1455 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
| 41712b4e SR |
1456 | |
| 1457 | #define AHB_TOP 0xA4 | |
| 1458 | #define AHB_BOT 0xA5 | |
| 745d8a0d SR |
1459 | #define SDR0_AHB_CFG 0x370 |
| 1460 | #define SDR0_USB2HOST_CFG 0x371 | |
| 43c60992 | 1461 | #endif /* CONFIG_460EX || CONFIG_460GT */ |
| 6c5879f3 | 1462 | |
| 6e7fb6ea SR |
1463 | #define SDR0_SDCS_SDD (0x80000000 >> 31) |
| 1464 | ||
| 1465 | #if defined(CONFIG_440GP) | |
| 1466 | #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) | |
| 1467 | #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) | |
| 1468 | #endif /* defined(CONFIG_440GP) */ | |
| 1469 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) | |
| 1470 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) | |
| 1471 | #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) | |
| 1472 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ | |
| 887e2ec9 SR |
1473 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 1474 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 6e7fb6ea SR |
1475 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) |
| 1476 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) | |
| 1477 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ | |
| 63153492 WD |
1478 | |
| 1479 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | |
| 1480 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | |
| 1481 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | |
| 1482 | #define SDR0_UARTX_UXEC_INT 0x00000000 | |
| 1483 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | |
| 1484 | #define SDR0_UARTX_UXDTE_MASK 0x00400000 | |
| 1485 | #define SDR0_UARTX_UXDTE_DISABLE 0x00000000 | |
| 1486 | #define SDR0_UARTX_UXDTE_ENABLE 0x00400000 | |
| 1487 | #define SDR0_UARTX_UXDRE_MASK 0x00200000 | |
| 1488 | #define SDR0_UARTX_UXDRE_DISABLE 0x00000000 | |
| 1489 | #define SDR0_UARTX_UXDRE_ENABLE 0x00200000 | |
| 1490 | #define SDR0_UARTX_UXDC_MASK 0x00100000 | |
| 1491 | #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 | |
| 1492 | #define SDR0_UARTX_UXDC_CLEARED 0x00100000 | |
| 1493 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | |
| 1494 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | |
| 1495 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | |
| 1496 | ||
| 1497 | #define SDR0_CPU440_EARV_MASK 0x30000000 | |
| 1498 | #define SDR0_CPU440_EARV_EBC 0x10000000 | |
| 1499 | #define SDR0_CPU440_EARV_PCI 0x20000000 | |
| 1500 | #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
| 1501 | #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
| 1502 | #define SDR0_CPU440_NTO1_MASK 0x00000002 | |
| 1503 | #define SDR0_CPU440_NTO1_NTOP 0x00000000 | |
| 1504 | #define SDR0_CPU440_NTO1_NTO1 0x00000002 | |
| 1505 | #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
| 1506 | #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
| 1507 | ||
| 1508 | #define SDR0_XCR_PAE_MASK 0x80000000 | |
| 1509 | #define SDR0_XCR_PAE_DISABLE 0x00000000 | |
| 1510 | #define SDR0_XCR_PAE_ENABLE 0x80000000 | |
| 1511 | #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
| 1512 | #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
| 1513 | #define SDR0_XCR_PHCE_MASK 0x40000000 | |
| 1514 | #define SDR0_XCR_PHCE_DISABLE 0x00000000 | |
| 1515 | #define SDR0_XCR_PHCE_ENABLE 0x40000000 | |
| 1516 | #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
| 1517 | #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
| 1518 | #define SDR0_XCR_PISE_MASK 0x20000000 | |
| 1519 | #define SDR0_XCR_PISE_DISABLE 0x00000000 | |
| 1520 | #define SDR0_XCR_PISE_ENABLE 0x20000000 | |
| 1521 | #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
| 1522 | #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
| 1523 | #define SDR0_XCR_PCWE_MASK 0x10000000 | |
| 1524 | #define SDR0_XCR_PCWE_DISABLE 0x00000000 | |
| 1525 | #define SDR0_XCR_PCWE_ENABLE 0x10000000 | |
| 1526 | #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
| 1527 | #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
| 1528 | #define SDR0_XCR_PPIM_MASK 0x0F000000 | |
| 1529 | #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
| 1530 | #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 1531 | #define SDR0_XCR_PR64E_MASK 0x00800000 | |
| 1532 | #define SDR0_XCR_PR64E_DISABLE 0x00000000 | |
| 1533 | #define SDR0_XCR_PR64E_ENABLE 0x00800000 | |
| 1534 | #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
| 1535 | #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
| 1536 | #define SDR0_XCR_PXFS_MASK 0x00600000 | |
| 1537 | #define SDR0_XCR_PXFS_HIGH 0x00000000 | |
| 1538 | #define SDR0_XCR_PXFS_MED 0x00200000 | |
| 1539 | #define SDR0_XCR_PXFS_LOW 0x00400000 | |
| 1540 | #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
| 1541 | #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
| 1542 | #define SDR0_XCR_PDM_MASK 0x00000040 | |
| 1543 | #define SDR0_XCR_PDM_MULTIPOINT 0x00000000 | |
| 1544 | #define SDR0_XCR_PDM_P2P 0x00000040 | |
| 1545 | #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) | |
| 1546 | #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) | |
| 0e6d798c WD |
1547 | |
| 1548 | #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 | |
| 63153492 WD |
1549 | #define SDR0_PFC0_GEIE_MASK 0x00003E00 |
| 1550 | #define SDR0_PFC0_GEIE_TRE 0x00003E00 | |
| 1551 | #define SDR0_PFC0_GEIE_NOTRE 0x00000000 | |
| 1552 | #define SDR0_PFC0_TRE_MASK 0x00000100 | |
| 1553 | #define SDR0_PFC0_TRE_DISABLE 0x00000000 | |
| 1554 | #define SDR0_PFC0_TRE_ENABLE 0x00000100 | |
| 1555 | #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | |
| 1556 | #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | |
| 1557 | ||
| 1558 | #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 | |
| 1559 | #define SDR0_PFC1_EPS_MASK 0x01C00000 | |
| 1560 | #define SDR0_PFC1_EPS_GROUP0 0x00000000 | |
| 1561 | #define SDR0_PFC1_EPS_GROUP1 0x00400000 | |
| 1562 | #define SDR0_PFC1_EPS_GROUP2 0x00800000 | |
| 1563 | #define SDR0_PFC1_EPS_GROUP3 0x00C00000 | |
| 1564 | #define SDR0_PFC1_EPS_GROUP4 0x01000000 | |
| 1565 | #define SDR0_PFC1_EPS_GROUP5 0x01400000 | |
| 1566 | #define SDR0_PFC1_EPS_GROUP6 0x01800000 | |
| 1567 | #define SDR0_PFC1_EPS_GROUP7 0x01C00000 | |
| 1568 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | |
| 1569 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | |
| 1570 | #define SDR0_PFC1_RMII_MASK 0x00200000 | |
| 1571 | #define SDR0_PFC1_RMII_100MBIT 0x00000000 | |
| 1572 | #define SDR0_PFC1_RMII_10MBIT 0x00200000 | |
| 1573 | #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) | |
| 1574 | #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | |
| 1575 | #define SDR0_PFC1_CTEMS_MASK 0x00100000 | |
| 1576 | #define SDR0_PFC1_CTEMS_EMS 0x00000000 | |
| 1577 | #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 | |
| 1578 | ||
| 1579 | #define SDR0_MFR_TAH0_MASK 0x80000000 | |
| 1580 | #define SDR0_MFR_TAH0_ENABLE 0x00000000 | |
| 1581 | #define SDR0_MFR_TAH0_DISABLE 0x80000000 | |
| 1582 | #define SDR0_MFR_TAH1_MASK 0x40000000 | |
| 1583 | #define SDR0_MFR_TAH1_ENABLE 0x00000000 | |
| 1584 | #define SDR0_MFR_TAH1_DISABLE 0x40000000 | |
| 1585 | #define SDR0_MFR_PCM_MASK 0x20000000 | |
| 1586 | #define SDR0_MFR_PCM_PPC440GX 0x00000000 | |
| 1587 | #define SDR0_MFR_PCM_PPC440GP 0x20000000 | |
| 1588 | #define SDR0_MFR_ECS_MASK 0x10000000 | |
| 1589 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | |
| 1590 | ||
| c157d8e2 SR |
1591 | #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ |
| 1592 | #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ | |
| 1593 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
| 1594 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
| 1595 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
| 1596 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
| 1597 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | |
| 1598 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
| 1599 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
| 1600 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
| 1601 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
| 887e2ec9 | 1602 | #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ |
| c157d8e2 SR |
1603 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ |
| 1604 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ | |
| 1605 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ | |
| 1606 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ | |
| 1607 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ | |
| 887e2ec9 SR |
1608 | #endif |
| 1609 | ||
| 1610 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 1611 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | |
| 1612 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | |
| 1613 | #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) | |
| 1614 | #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) | |
| 1615 | #endif | |
| 1616 | ||
| 1617 | #define SDR0_MFR_ECS_MASK 0x10000000 | |
| 1618 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | |
| 1619 | ||
| 1620 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 1621 | #define SDR0_SRST0 0x200 | |
| 1622 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ | |
| 1623 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | |
| 1624 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | |
| 1625 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | |
| 1626 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ | |
| 1627 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ | |
| 1628 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ | |
| 1629 | #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ | |
| 1630 | #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ | |
| 1631 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | |
| 1632 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | |
| 1633 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | |
| 1634 | #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ | |
| 1635 | #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ | |
| 1636 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | |
| 1637 | #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ | |
| 1638 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ | |
| 1639 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ | |
| 1640 | #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ | |
| 1641 | #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ | |
| 1642 | #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ | |
| 1643 | #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ | |
| 1644 | #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ | |
| 1645 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ | |
| 1646 | #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ | |
| 1647 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | |
| 1648 | #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ | |
| 1649 | #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ | |
| 1650 | #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ | |
| 1651 | #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */ | |
| 1652 | #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */ | |
| 1653 | ||
| 1654 | #define SDR0_SRST1 0x201 | |
| 1655 | #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ | |
| 1656 | #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ | |
| 1657 | #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ | |
| 1658 | #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 | |
| 1659 | #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ | |
| 1660 | #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ | |
| 1661 | #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */ | |
| 1662 | #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */ | |
| 1663 | #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */ | |
| 1664 | #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ | |
| 1665 | #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */ | |
| 1666 | #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ | |
| 1667 | #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ | |
| 1668 | #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ | |
| 1669 | #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ | |
| 1670 | #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ | |
| 1671 | #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ | |
| 1672 | #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ | |
| 1673 | #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ | |
| 1674 | #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ | |
| 1675 | ||
| 43c60992 SR |
1676 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 1677 | ||
| 1678 | #define SDR0_SRST0 0x0200 | |
| 1679 | #define SDR0_SRST SDR0_SRST0 /* for compatability reasons */ | |
| 1680 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ | |
| 1681 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | |
| 1682 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | |
| 1683 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | |
| 1684 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ | |
| 1685 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ | |
| 1686 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ | |
| 1687 | #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ | |
| 1688 | #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ | |
| 1689 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | |
| 1690 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | |
| 1691 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | |
| 1692 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | |
| 1693 | #define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ | |
| 1694 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ | |
| 1695 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ | |
| 1696 | #define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ | |
| 1697 | #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ | |
| 1698 | #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ | |
| 1699 | #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ | |
| 1700 | #define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */ | |
| 1701 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ | |
| 1702 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | |
| 1703 | #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ | |
| 1704 | #define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */ | |
| 1705 | #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ | |
| 1706 | ||
| 1707 | #define SDR0_SRST1 0x201 | |
| 1708 | #define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ | |
| 1709 | #define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ | |
| 1710 | #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ | |
| 1711 | #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ | |
| 1712 | #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ | |
| 1713 | #define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */ | |
| 1714 | #define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */ | |
| 1715 | #define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */ | |
| 1716 | #define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */ | |
| 1717 | #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ | |
| 1718 | #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ | |
| 1719 | #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ | |
| 1720 | #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ | |
| 1721 | #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ | |
| 1722 | #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ | |
| 1723 | #define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */ | |
| 1724 | #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ | |
| 1725 | #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ | |
| 1726 | #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ | |
| 1727 | #define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ | |
| 1728 | #define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ | |
| 1729 | #define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ | |
| 1730 | #define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ | |
| 1731 | #define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ | |
| 1732 | #define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ | |
| 1733 | #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ | |
| 1734 | #define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ | |
| 1735 | #define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ | |
| 1736 | #define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ | |
| 1737 | #define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ | |
| 1738 | #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ | |
| 1739 | #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ | |
| 1740 | ||
| 1741 | #define SDR0_PCI0 0x1c0 /* PCI Configuration Register */ | |
| 1742 | ||
| 887e2ec9 | 1743 | #else |
| c157d8e2 | 1744 | |
| 63153492 WD |
1745 | #define SDR0_SRST_BGO 0x80000000 |
| 1746 | #define SDR0_SRST_PLB 0x40000000 | |
| 1747 | #define SDR0_SRST_EBC 0x20000000 | |
| 1748 | #define SDR0_SRST_OPB 0x10000000 | |
| 1749 | #define SDR0_SRST_UART0 0x08000000 | |
| 1750 | #define SDR0_SRST_UART1 0x04000000 | |
| 1751 | #define SDR0_SRST_IIC0 0x02000000 | |
| 1752 | #define SDR0_SRST_IIC1 0x01000000 | |
| 1753 | #define SDR0_SRST_GPIO 0x00800000 | |
| 1754 | #define SDR0_SRST_GPT 0x00400000 | |
| 1755 | #define SDR0_SRST_DMC 0x00200000 | |
| 1756 | #define SDR0_SRST_PCI 0x00100000 | |
| 1757 | #define SDR0_SRST_EMAC0 0x00080000 | |
| 1758 | #define SDR0_SRST_EMAC1 0x00040000 | |
| 1759 | #define SDR0_SRST_CPM 0x00020000 | |
| 1760 | #define SDR0_SRST_IMU 0x00010000 | |
| 1761 | #define SDR0_SRST_UIC01 0x00008000 | |
| 1762 | #define SDR0_SRST_UICB2 0x00004000 | |
| 1763 | #define SDR0_SRST_SRAM 0x00002000 | |
| 1764 | #define SDR0_SRST_EBM 0x00001000 | |
| 1765 | #define SDR0_SRST_BGI 0x00000800 | |
| 1766 | #define SDR0_SRST_DMA 0x00000400 | |
| 1767 | #define SDR0_SRST_DMAC 0x00000200 | |
| 1768 | #define SDR0_SRST_MAL 0x00000100 | |
| 1769 | #define SDR0_SRST_ZMII 0x00000080 | |
| 1770 | #define SDR0_SRST_GPTR 0x00000040 | |
| 1771 | #define SDR0_SRST_PPM 0x00000020 | |
| 1772 | #define SDR0_SRST_EMAC2 0x00000010 | |
| 1773 | #define SDR0_SRST_EMAC3 0x00000008 | |
| 1774 | #define SDR0_SRST_RGMII 0x00000001 | |
| 0e6d798c | 1775 | |
| 887e2ec9 SR |
1776 | #endif |
| 1777 | ||
| c00b5f85 WD |
1778 | /*-----------------------------------------------------------------------------+ |
| 1779 | | Clocking | |
| 1780 | +-----------------------------------------------------------------------------*/ | |
| 96e5fc0e FK |
1781 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
| 1782 | defined(CONFIG_460SX) | |
| 43c60992 SR |
1783 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
| 1784 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ | |
| 1785 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ | |
| 1786 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ | |
| 1787 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ | |
| 1788 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
| 1789 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ | |
| 1790 | #elif !defined (CONFIG_440GX) && \ | |
| 887e2ec9 SR |
1791 | !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ |
| 1792 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
| 1793 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) | |
| ba56f625 WD |
1794 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ |
| 1795 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ | |
| 1796 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ | |
| 1797 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ | |
| 1798 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ | |
| 1799 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ | |
| 1800 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ | |
| 1801 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ | |
| 1802 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ | |
| 1803 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ | |
| 1804 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ | |
| 1805 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
| 1806 | ||
| 1807 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ | |
| 1808 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
| 1809 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
| 1810 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
| 846b0dd2 | 1811 | #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ |
| ba56f625 WD |
1812 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ |
| 1813 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | |
| 1814 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ | |
| 1815 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ | |
| 1816 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | |
| 1817 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | |
| 1818 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | |
| 1819 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | |
| 1820 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | |
| 1821 | ||
| c157d8e2 SR |
1822 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ |
| 1823 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ | |
| 1824 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | |
| 1825 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | |
| 1826 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | |
| 1827 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | |
| 1828 | ||
| 1829 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | |
| 1830 | #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ | |
| 1831 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ | |
| 1832 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | |
| 1833 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | |
| 1834 | ||
| ba56f625 WD |
1835 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
| 1836 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
| 1837 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
| 1838 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
| 1839 | ||
| 1840 | /* Strap 1 Register */ | |
| 1841 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | |
| 1842 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
| 1843 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | |
| 1844 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | |
| 1845 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ | |
| 1846 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ | |
| 1847 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | |
| 1848 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | |
| 1849 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | |
| 1850 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | |
| 1851 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | |
| 1852 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | |
| 1853 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | |
| 1854 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | |
| 1855 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | |
| 1856 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | |
| 1857 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | |
| 1858 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
| 846b0dd2 | 1859 | #endif /* CONFIG_440GX */ |
| c00b5f85 | 1860 | |
| 887e2ec9 | 1861 | #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) |
| 26173fc6 SR |
1862 | #define CPR0_ICFG_RLI_MASK 0x80000000 |
| 1863 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 | |
| 1864 | #define CPR0_PERD_PERDV0_MASK 0x07000000 | |
| 887e2ec9 | 1865 | #endif |
| 887e2ec9 | 1866 | |
| c00b5f85 WD |
1867 | /*----------------------------------------------------------------------------- |
| 1868 | | IIC Register Offsets | |
| 1869 | '----------------------------------------------------------------------------*/ | |
| 63153492 WD |
1870 | #define IICMDBUF 0x00 |
| 1871 | #define IICSDBUF 0x02 | |
| 1872 | #define IICLMADR 0x04 | |
| 1873 | #define IICHMADR 0x05 | |
| 1874 | #define IICCNTL 0x06 | |
| 1875 | #define IICMDCNTL 0x07 | |
| 1876 | #define IICSTS 0x08 | |
| 1877 | #define IICEXTSTS 0x09 | |
| 1878 | #define IICLSADR 0x0A | |
| 1879 | #define IICHSADR 0x0B | |
| 1880 | #define IICCLKDIV 0x0C | |
| 1881 | #define IICINTRMSK 0x0D | |
| 1882 | #define IICXFRCNT 0x0E | |
| 1883 | #define IICXTCNTLSS 0x0F | |
| 1884 | #define IICDIRECTCNTL 0x10 | |
| c00b5f85 | 1885 | |
| c00b5f85 WD |
1886 | /*----------------------------------------------------------------------------- |
| 1887 | | PCI Internal Registers et. al. (accessed via plb) | |
| 1888 | +----------------------------------------------------------------------------*/ | |
| 0e6d798c WD |
1889 | #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) |
| 1890 | #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) | |
| 1891 | #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) | |
| 1892 | #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) | |
| 1893 | ||
| 887e2ec9 SR |
1894 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 1895 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| c157d8e2 SR |
1896 | |
| 1897 | /* PCI Local Configuration Registers | |
| 1898 | --------------------------------- */ | |
| 1899 | #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ | |
| 1900 | ||
| 1901 | /* PCI Master Local Configuration Registers */ | |
| 1902 | #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ | |
| 1903 | #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | |
| 1904 | #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | |
| 1905 | #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | |
| 1906 | #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | |
| 1907 | #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | |
| 1908 | #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | |
| 1909 | #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | |
| 1910 | #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | |
| 1911 | #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | |
| 1912 | #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | |
| 1913 | #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | |
| 1914 | ||
| 1915 | /* PCI Target Local Configuration Registers */ | |
| 1916 | #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ | |
| 1917 | #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | |
| 1918 | #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ | |
| 1919 | #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | |
| 1920 | ||
| 1921 | #else | |
| 1922 | ||
| 0e6d798c WD |
1923 | #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) |
| 1924 | #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) | |
| 1925 | #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) | |
| 1926 | #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) | |
| 1927 | #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) | |
| 1928 | #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) | |
| 1929 | #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) | |
| 1930 | #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) | |
| 1931 | #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) | |
| 1932 | #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) | |
| 1933 | #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) | |
| 1934 | #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) | |
| 1935 | #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) | |
| 1936 | #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) | |
| 1937 | #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) | |
| 1938 | #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) | |
| 1939 | #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) | |
| 1940 | #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) | |
| 1941 | #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) | |
| 1942 | #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) | |
| 1943 | #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) | |
| 1944 | #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) | |
| 1945 | #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) | |
| 1946 | #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) | |
| 1947 | #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) | |
| 1948 | #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) | |
| 1949 | #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) | |
| 1950 | #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) | |
| 1951 | ||
| 63153492 WD |
1952 | #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) |
| 1953 | #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) | |
| 0e6d798c WD |
1954 | |
| 1955 | #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) | |
| 1956 | #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) | |
| 1957 | #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) | |
| 63153492 WD |
1958 | #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) |
| 1959 | #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) | |
| 0e6d798c WD |
1960 | #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) |
| 1961 | #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) | |
| 1962 | #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) | |
| 63153492 WD |
1963 | #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) |
| 1964 | #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) | |
| 0e6d798c WD |
1965 | #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) |
| 1966 | ||
| 1967 | #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) | |
| 1968 | #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) | |
| 1969 | #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) | |
| 1970 | #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) | |
| 1971 | #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) | |
| 1972 | #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) | |
| 1973 | #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) | |
| 1974 | #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) | |
| 1975 | #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) | |
| 1976 | ||
| 1977 | #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) | |
| c00b5f85 | 1978 | |
| 846b0dd2 | 1979 | #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ |
| c157d8e2 | 1980 | |
| 887e2ec9 SR |
1981 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| 1982 | ||
| 1983 | /* USB2.0 Device */ | |
| 1984 | #define USB2D0_BASE CFG_USB2D0_BASE | |
| 1985 | ||
| 1986 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) | |
| 1987 | ||
| 1988 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */ | |
| 1989 | #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */ | |
| 1990 | #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */ | |
| 1991 | #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */ | |
| 1992 | #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */ | |
| 1993 | #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */ | |
| 1994 | #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */ | |
| 1995 | #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */ | |
| 1996 | #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */ | |
| 1997 | #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */ | |
| 1998 | #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ | |
| 1999 | #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */ | |
| 2000 | #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */ | |
| 2001 | #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */ | |
| 2002 | #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
| 2003 | #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
| 2004 | #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ | |
| 2005 | #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ | |
| 2006 | #endif | |
| 2007 | ||
| c157d8e2 SR |
2008 | /****************************************************************************** |
| 2009 | * GPIO macro register defines | |
| 2010 | ******************************************************************************/ | |
| ba58e4c9 | 2011 | #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ |
| 96e5fc0e FK |
2012 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
| 2013 | defined(CONFIG_460SX) | |
| a4c8d138 | 2014 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) |
| 5568e613 | 2015 | |
| a4c8d138 SR |
2016 | #define GPIO0_OR (GPIO0_BASE+0x0) |
| 2017 | #define GPIO0_TCR (GPIO0_BASE+0x4) | |
| 2018 | #define GPIO0_ODR (GPIO0_BASE+0x18) | |
| 2019 | #define GPIO0_IR (GPIO0_BASE+0x1C) | |
| 5568e613 SR |
2020 | #endif /* CONFIG_440GP */ |
| 2021 | ||
| 887e2ec9 | 2022 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 43c60992 SR |
2023 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 2024 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
| a4c8d138 SR |
2025 | #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) |
| 2026 | #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) | |
| 2027 | ||
| a4c8d138 SR |
2028 | #define GPIO0_OR (GPIO0_BASE+0x0) |
| 2029 | #define GPIO0_TCR (GPIO0_BASE+0x4) | |
| 2030 | #define GPIO0_OSRL (GPIO0_BASE+0x8) | |
| 2031 | #define GPIO0_OSRH (GPIO0_BASE+0xC) | |
| 2032 | #define GPIO0_TSRL (GPIO0_BASE+0x10) | |
| 2033 | #define GPIO0_TSRH (GPIO0_BASE+0x14) | |
| 2034 | #define GPIO0_ODR (GPIO0_BASE+0x18) | |
| 2035 | #define GPIO0_IR (GPIO0_BASE+0x1C) | |
| 2036 | #define GPIO0_RR1 (GPIO0_BASE+0x20) | |
| 2037 | #define GPIO0_RR2 (GPIO0_BASE+0x24) | |
| 2038 | #define GPIO0_RR3 (GPIO0_BASE+0x28) | |
| 2039 | #define GPIO0_ISR1L (GPIO0_BASE+0x30) | |
| 2040 | #define GPIO0_ISR1H (GPIO0_BASE+0x34) | |
| 2041 | #define GPIO0_ISR2L (GPIO0_BASE+0x38) | |
| 2042 | #define GPIO0_ISR2H (GPIO0_BASE+0x3C) | |
| 2043 | #define GPIO0_ISR3L (GPIO0_BASE+0x40) | |
| 2044 | #define GPIO0_ISR3H (GPIO0_BASE+0x44) | |
| 2045 | ||
| 2046 | #define GPIO1_OR (GPIO1_BASE+0x0) | |
| 2047 | #define GPIO1_TCR (GPIO1_BASE+0x4) | |
| 2048 | #define GPIO1_OSRL (GPIO1_BASE+0x8) | |
| 2049 | #define GPIO1_OSRH (GPIO1_BASE+0xC) | |
| 2050 | #define GPIO1_TSRL (GPIO1_BASE+0x10) | |
| 2051 | #define GPIO1_TSRH (GPIO1_BASE+0x14) | |
| 2052 | #define GPIO1_ODR (GPIO1_BASE+0x18) | |
| 2053 | #define GPIO1_IR (GPIO1_BASE+0x1C) | |
| 2054 | #define GPIO1_RR1 (GPIO1_BASE+0x20) | |
| 2055 | #define GPIO1_RR2 (GPIO1_BASE+0x24) | |
| 2056 | #define GPIO1_RR3 (GPIO1_BASE+0x28) | |
| 2057 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) | |
| 2058 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) | |
| 2059 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) | |
| 2060 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) | |
| 2061 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) | |
| 2062 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) | |
| c157d8e2 SR |
2063 | #endif |
| 2064 | ||
| c00b5f85 WD |
2065 | #ifndef __ASSEMBLY__ |
| 2066 | ||
| ba56f625 | 2067 | #endif /* _ASMLANGUAGE */ |
| c00b5f85 | 2068 | |
| c00b5f85 | 2069 | #endif /* __PPC440_H__ */ |