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c00b5f85 | 1 | /*----------------------------------------------------------------------------+ |
31773496 JB |
2 | | This source code is dual-licensed. You may use it under the terms of the |
3 | | GNU General Public License version 2, or under the license below. | |
c00b5f85 | 4 | | |
ba56f625 WD |
5 | | This source code has been made available to you by IBM on an AS-IS |
6 | | basis. Anyone receiving this source is licensed under IBM | |
7 | | copyrights to use it in any way he or she deems fit, including | |
8 | | copying it, modifying it, compiling it, and redistributing it either | |
9 | | with or without modifications. No license under IBM patents or | |
10 | | patent applications is to be implied by the copyright license. | |
c00b5f85 | 11 | | |
ba56f625 WD |
12 | | Any user of this software should understand that IBM cannot provide |
13 | | technical support for this software and will not be responsible for | |
14 | | any consequences resulting from the use of this software. | |
c00b5f85 | 15 | | |
ba56f625 WD |
16 | | Any person who transfers this source code or any derivative work |
17 | | must include the IBM copyright notice, this paragraph, and the | |
18 | | preceding two paragraphs in the transferred software. | |
c00b5f85 | 19 | | |
ba56f625 WD |
20 | | COPYRIGHT I B M CORPORATION 1999 |
21 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
c00b5f85 WD |
22 | +----------------------------------------------------------------------------*/ |
23 | ||
c46f5333 LJ |
24 | /* |
25 | * (C) Copyright 2006 | |
26 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com | |
27 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
28 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com | |
29 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
30 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com | |
31 | * | |
32 | * This program is free software; you can redistribute it and/or | |
33 | * modify it under the terms of the GNU General Public License as | |
34 | * published by the Free Software Foundation; either version 2 of | |
35 | * the License, or (at your option) any later version. | |
36 | * | |
37 | * This program is distributed in the hope that it will be useful, | |
38 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
39 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
40 | * GNU General Public License for more details. | |
41 | * | |
42 | * You should have received a copy of the GNU General Public License | |
43 | * along with this program; if not, write to the Free Software | |
44 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
45 | * MA 02111-1307 USA | |
46 | */ | |
47 | ||
ba56f625 | 48 | #ifndef __PPC440_H__ |
c00b5f85 WD |
49 | #define __PPC440_H__ |
50 | ||
dbcc3571 | 51 | #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ |
9b94ac61 | 52 | |
c00b5f85 WD |
53 | /****************************************************************************** |
54 | * DCRs & Related | |
55 | ******************************************************************************/ | |
56 | ||
ba56f625 WD |
57 | /*----------------------------------------------------------------------------- |
58 | | Clocking Controller | |
59 | +----------------------------------------------------------------------------*/ | |
ba56f625 | 60 | /* values for clkcfga register - indirect addressing of these regs */ |
d1c3b275 SR |
61 | #define CPR0_PLLC 0x0040 |
62 | #define CPR0_PLLD 0x0060 | |
f80e61dc NG |
63 | #define CPR0_PRIMAD0 0x0080 |
64 | #define CPR0_PRIMBD0 0x00a0 | |
65 | #define CPR0_OPBD0 0x00c0 | |
d1c3b275 SR |
66 | #define CPR0_PERD 0x00e0 |
67 | #define CPR0_MALD 0x0100 | |
68 | #define CPR0_SPCID 0x0120 | |
69 | #define CPR0_ICFG 0x0140 | |
ba56f625 WD |
70 | |
71 | /* 440gx sdr register definations */ | |
d1c3b275 SR |
72 | #define SDR0_SDSTP0 0x0020 /* */ |
73 | #define SDR0_SDSTP1 0x0021 /* */ | |
74 | #define SDR0_PINSTP 0x0040 | |
75 | #define SDR0_SDCS0 0x0060 | |
711e2b2a SF |
76 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
77 | #define SDR0_DDRCFG 0x00e0 | |
78 | #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ | |
d1c3b275 SR |
79 | #define SDR0_EBC 0x0100 |
80 | #define SDR0_UART0 0x0120 /* UART0 Config */ | |
81 | #define SDR0_UART1 0x0121 /* UART1 Config */ | |
82 | #define SDR0_UART2 0x0122 /* UART2 Config */ | |
83 | #define SDR0_UART3 0x0123 /* UART3 Config */ | |
84 | #define SDR0_CP440 0x0180 | |
85 | #define SDR0_XCR 0x01c0 | |
86 | #define SDR0_XPLLC 0x01c1 | |
87 | #define SDR0_XPLLD 0x01c2 | |
88 | #define SDR0_SRST 0x0200 | |
dbcc3571 NG |
89 | #define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ |
90 | #define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ | |
d1c3b275 SR |
91 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
92 | #define SDR0_PCI0 0x01c0 | |
93 | #else | |
94 | #define SDR0_PCI0 0x0300 | |
95 | #endif | |
96 | #define SDR0_USB0 0x0320 | |
97 | #define SDR0_CUST0 0x4000 | |
98 | #define SDR0_CUST1 0x4002 | |
99 | #define SDR0_PFC0 0x4100 /* Pin Function 0 */ | |
100 | #define SDR0_PFC1 0x4101 /* Pin Function 1 */ | |
101 | #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ | |
ba56f625 | 102 | |
f80e61dc | 103 | #if defined(CONFIG_440GX) |
d1c3b275 SR |
104 | #define SD0_AMP 0x0240 |
105 | #define SDR0_XPLLC 0x01c1 | |
106 | #define SDR0_XPLLD 0x01c2 | |
107 | #define SDR0_XCR 0x01c0 | |
108 | #define SDR0_SDSTP2 0x4001 | |
109 | #define SDR0_SDSTP3 0x4003 | |
bba68377 | 110 | #endif /* CONFIG_440GX */ |
6c5879f3 | 111 | |
a11e0696 IL |
112 | /*----------------------------------------------------------------------------+ |
113 | | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). | |
114 | +----------------------------------------------------------------------------*/ | |
115 | #define CCR0_PRE 0x40000000 | |
116 | #define CCR0_CRPE 0x08000000 | |
117 | #define CCR0_DSTG 0x00200000 | |
118 | #define CCR0_DAPUIB 0x00100000 | |
119 | #define CCR0_DTB 0x00008000 | |
120 | #define CCR0_GICBT 0x00004000 | |
121 | #define CCR0_GDCBT 0x00002000 | |
122 | #define CCR0_FLSTA 0x00000100 | |
123 | #define CCR0_ICSLC_MASK 0x0000000C | |
124 | #define CCR0_ICSLT_MASK 0x00000003 | |
125 | #define CCR1_TCS_MASK 0x00000080 | |
126 | #define CCR1_TCS_INTCLK 0x00000000 | |
127 | #define CCR1_TCS_EXTCLK 0x00000080 | |
128 | #define MMUCR_SWOA 0x01000000 | |
129 | #define MMUCR_U1TE 0x00400000 | |
130 | #define MMUCR_U2SWOAE 0x00200000 | |
131 | #define MMUCR_DULXE 0x00800000 | |
132 | #define MMUCR_IULXE 0x00400000 | |
133 | #define MMUCR_STS 0x00100000 | |
134 | #define MMUCR_STID_MASK 0x000000FF | |
a11e0696 | 135 | |
6c5879f3 | 136 | #ifdef CONFIG_440SPE |
d1c3b275 SR |
137 | #undef SDR0_SDSTP2 |
138 | #define SDR0_SDSTP2 0x0022 | |
139 | #undef SDR0_SDSTP3 | |
140 | #define SDR0_SDSTP3 0x0023 | |
141 | #define SDR0_DDR0 0x00E1 | |
142 | #define SDR0_UART2 0x0122 | |
143 | #define SDR0_XCR0 0x01c0 | |
144 | #define SDR0_XCR1 0x01c3 | |
145 | #define SDR0_XCR2 0x01c6 | |
146 | #define SDR0_XPLLC0 0x01c1 | |
147 | #define SDR0_XPLLD0 0x01c2 | |
dbcc3571 NG |
148 | #define SDR0_XPLLC1 0x01c4 /* notRCW - SG */ |
149 | #define SDR0_XPLLD1 0x01c5 /* notRCW - SG */ | |
150 | #define SDR0_XPLLC2 0x01c7 /* notRCW - SG */ | |
151 | #define SDR0_XPLLD2 0x01c8 /* dnotRCW - SG */ | |
d1c3b275 SR |
152 | #define SD0_AMP0 0x0240 |
153 | #define SD0_AMP1 0x0241 | |
154 | #define SDR0_CUST2 0x4004 | |
155 | #define SDR0_CUST3 0x4006 | |
156 | #define SDR0_SDSTP4 0x4001 | |
157 | #define SDR0_SDSTP5 0x4003 | |
158 | #define SDR0_SDSTP6 0x4005 | |
159 | #define SDR0_SDSTP7 0x4007 | |
6c5879f3 | 160 | |
df294497 | 161 | #endif /* CONFIG_440SPE */ |
6c5879f3 | 162 | |
c00b5f85 | 163 | /*----------------------------------------------------------------------------- |
6ed6ce62 | 164 | | External Bus Controller |
c00b5f85 | 165 | +----------------------------------------------------------------------------*/ |
d1c3b275 SR |
166 | /* values for EBC0_CFGADDR register - indirect addressing of these regs */ |
167 | #define PB0CR 0x00 /* periph bank 0 config reg */ | |
168 | #define PB1CR 0x01 /* periph bank 1 config reg */ | |
169 | #define PB2CR 0x02 /* periph bank 2 config reg */ | |
170 | #define PB3CR 0x03 /* periph bank 3 config reg */ | |
171 | #define PB4CR 0x04 /* periph bank 4 config reg */ | |
172 | #define PB5CR 0x05 /* periph bank 5 config reg */ | |
173 | #define PB6CR 0x06 /* periph bank 6 config reg */ | |
174 | #define PB7CR 0x07 /* periph bank 7 config reg */ | |
175 | #define PB0AP 0x10 /* periph bank 0 access parameters */ | |
176 | #define PB1AP 0x11 /* periph bank 1 access parameters */ | |
177 | #define PB2AP 0x12 /* periph bank 2 access parameters */ | |
178 | #define PB3AP 0x13 /* periph bank 3 access parameters */ | |
179 | #define PB4AP 0x14 /* periph bank 4 access parameters */ | |
180 | #define PB5AP 0x15 /* periph bank 5 access parameters */ | |
181 | #define PB6AP 0x16 /* periph bank 6 access parameters */ | |
182 | #define PB7AP 0x17 /* periph bank 7 access parameters */ | |
183 | #define PBEAR 0x20 /* periph bus error addr reg */ | |
184 | #define PBESR 0x21 /* periph bus error status reg */ | |
4745acaa | 185 | #define EBC0_CFG 0x23 /* external bus configuration reg */ |
c00b5f85 | 186 | |
887e2ec9 SR |
187 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
188 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
c157d8e2 | 189 | |
dbcc3571 | 190 | /* PLB3 Arbiter */ |
d1c3b275 SR |
191 | #define PLB3_DCR_BASE 0x070 |
192 | #define PLB3_ACR (PLB3_DCR_BASE + 0x7) | |
c157d8e2 | 193 | |
dbcc3571 | 194 | /* PLB4 Arbiter - PowerPC440EP Pass1 */ |
d1c3b275 SR |
195 | #define PLB4_DCR_BASE 0x080 |
196 | #define PLB4_ACR (PLB4_DCR_BASE + 0x1) | |
c157d8e2 | 197 | |
a78bc443 SR |
198 | #define PLB4_ACR_WRP (0x80000000 >> 7) |
199 | ||
dbcc3571 | 200 | /* Pin Function Control Register 1 */ |
17f50f22 | 201 | #define SDR0_PFC1 0x4101 |
dbcc3571 NG |
202 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ |
203 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
204 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
205 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
206 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
207 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
208 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
209 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
210 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
211 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
212 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
213 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
214 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold | |
215 | Req Selection */ | |
216 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
217 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
218 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) | |
219 | Selection */ | |
220 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
221 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
222 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) | |
223 | Selection */ | |
224 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. | |
225 | Selected */ | |
226 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
227 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject | |
228 | Selection */ | |
229 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject | |
230 | Disable */ | |
231 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject | |
232 | Enable */ | |
233 | ||
234 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable | |
235 | Selection */ | |
236 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor | |
237 | Enable */ | |
238 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor | |
239 | Enable */ | |
240 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation | |
241 | Gated In */ | |
242 | ||
243 | /* USB Control Register */ | |
17f50f22 | 244 | #define SDR0_USB0 0x0320 |
dbcc3571 NG |
245 | #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ |
246 | #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
247 | #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
248 | #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
249 | #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
250 | #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
251 | ||
252 | /* Miscealleneaous Function Reg. */ | |
887e2ec9 | 253 | #define SDR0_MFR 0x4300 |
dbcc3571 NG |
254 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ |
255 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
256 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
257 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
258 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
259 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
260 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
261 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
262 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | |
263 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
264 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
265 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | |
266 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | |
267 | ||
268 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
269 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
270 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | |
271 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ | |
272 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | |
273 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | |
274 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | |
887e2ec9 | 275 | |
8f24e063 | 276 | #define GPT0_COMP6 0x00000098 |
8f15d4ad YT |
277 | #define GPT0_COMP5 0x00000094 |
278 | #define GPT0_COMP4 0x00000090 | |
279 | #define GPT0_COMP3 0x0000008C | |
3d610186 YT |
280 | #define GPT0_COMP2 0x00000088 |
281 | #define GPT0_COMP1 0x00000084 | |
887e2ec9 | 282 | |
eb0615bf YT |
283 | #define GPT0_MASK6 0x000000D8 |
284 | #define GPT0_MASK5 0x000000D4 | |
285 | #define GPT0_MASK4 0x000000D0 | |
286 | #define GPT0_MASK3 0x000000CC | |
287 | #define GPT0_MASK2 0x000000C8 | |
288 | #define GPT0_MASK1 0x000000C4 | |
289 | ||
887e2ec9 | 290 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
f780b833 | 291 | #define SDR0_USB2D0CR 0x0320 |
dbcc3571 NG |
292 | #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC |
293 | Master Selection */ | |
294 | #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ | |
295 | #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ | |
296 | ||
297 | #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface | |
298 | Selection */ | |
299 | #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
300 | #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
301 | ||
302 | #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
303 | #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
304 | #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
305 | ||
306 | /* USB2 Host Control Register */ | |
307 | #define SDR0_USB2H0CR 0x0340 | |
308 | #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ | |
309 | #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ | |
310 | #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ | |
311 | #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length | |
312 | Adjustment */ | |
313 | ||
314 | /* Pin Function Control Register 1 */ | |
315 | #define SDR0_PFC1 0x4101 | |
316 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
317 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
318 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
319 | ||
320 | #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select | |
321 | EMAC 0 */ | |
322 | #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII | |
323 | bridge */ | |
324 | #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII | |
325 | bridge */ | |
326 | #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII | |
327 | bridge */ | |
328 | #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII | |
329 | bridge */ | |
330 | #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII | |
331 | bridge */ | |
332 | #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII | |
333 | bridge */ | |
334 | #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII | |
335 | bridge */ | |
336 | ||
337 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
338 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
339 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
340 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
341 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
342 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
343 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
344 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
345 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
346 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req | |
347 | Selection */ | |
348 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
349 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
350 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) | |
351 | Selection */ | |
352 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
353 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
354 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) | |
355 | Selection */ | |
356 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | |
357 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
358 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject | |
359 | Selection */ | |
360 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject | |
361 | Disable */ | |
362 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject | |
363 | Enable */ | |
364 | ||
365 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 | |
366 | /* PLB3/PLB4 Perf. Monitor En. Selection */ | |
367 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 | |
368 | /* PLB3 Performance Monitor Enable */ | |
369 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 | |
370 | /* PLB3 Performance Monitor Enable */ | |
371 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation | |
372 | Gated In */ | |
373 | ||
374 | /* Ethernet PLL Configuration Register */ | |
375 | #define SDR0_PFC2 0x4102 | |
376 | #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ | |
377 | #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication | |
378 | selector */ | |
379 | #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ | |
380 | #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ | |
381 | ||
382 | #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ | |
383 | #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ | |
384 | #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ | |
385 | #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ | |
386 | #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ | |
387 | #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ | |
388 | #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ | |
389 | #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ | |
887e2ec9 | 390 | |
b765ffb7 SR |
391 | #define SDR0_PFC4 0x4104 |
392 | ||
dbcc3571 NG |
393 | /* USB2PHY0 Control Register */ |
394 | #define SDR0_USB2PHY0CR 0x4103 | |
395 | #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 | |
396 | ||
397 | /* PHY UTMI interface connection */ | |
398 | #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ | |
399 | #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ | |
400 | ||
401 | #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ | |
402 | #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ | |
403 | #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ | |
404 | ||
405 | #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 | |
406 | /* VBus detect (Device mode only) */ | |
407 | #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 | |
408 | /* Pull-up resistance on D+ is disabled */ | |
409 | #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 | |
410 | /* Pull-up resistance on D+ is enabled */ | |
411 | ||
412 | #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 | |
413 | /* PHY UTMI data width and clock select */ | |
414 | #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ | |
415 | #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ | |
416 | ||
417 | #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ | |
418 | #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ | |
419 | #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 | |
420 | /* Loop back enabled (only test purposes) */ | |
421 | ||
422 | #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 | |
423 | /* Force XO block on during a suspend */ | |
424 | #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ | |
425 | #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 | |
426 | /* PHY XO block is powered-off when all ports are suspended */ | |
427 | ||
428 | #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ | |
429 | #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ | |
430 | #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only | |
431 | for full-speed operation */ | |
432 | ||
433 | #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock | |
434 | source */ | |
435 | #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal | |
436 | 48M clock as a reference */ | |
437 | #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO | |
438 | block output as a reference */ | |
439 | ||
440 | #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO | |
441 | block*/ | |
442 | #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external | |
443 | clock */ | |
444 | #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock | |
445 | from a crystal */ | |
446 | ||
447 | #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ | |
448 | #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq | |
449 | = 12 MHz */ | |
450 | #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq | |
451 | = 48 MHz */ | |
452 | #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq | |
453 | = 24 MHz */ | |
454 | ||
455 | /* Miscealleneaous Function Reg. */ | |
456 | #define SDR0_MFR 0x4300 | |
457 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | |
458 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
459 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
460 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
461 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
462 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
463 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
464 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
465 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
466 | #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) | |
467 | #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) | |
468 | ||
469 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
470 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
471 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | |
472 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ | |
473 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | |
474 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | |
475 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | |
887e2ec9 SR |
476 | |
477 | #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ | |
478 | ||
dbcc3571 NG |
479 | /* CUST1 Customer Configuration Register1 */ |
480 | #define SDR0_CUST1 0x4002 | |
481 | #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ | |
482 | #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) | |
483 | #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) | |
484 | ||
485 | /* Pin Function Control Register 0 */ | |
486 | #define SDR0_PFC0 0x4100 | |
487 | #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ | |
488 | #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ | |
489 | #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ | |
490 | #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | |
491 | #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | |
492 | ||
493 | /* Pin Function Control Register 1 */ | |
494 | #define SDR0_PFC1 0x4101 | |
495 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
496 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
497 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
498 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
499 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
500 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
501 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
502 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
503 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
504 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
505 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
506 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
507 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req | |
508 | Selection */ | |
509 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
510 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
511 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) | |
512 | Selection */ | |
513 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
514 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
515 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) | |
516 | Selection */ | |
517 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ | |
518 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
519 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject | |
520 | Selection */ | |
521 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject | |
522 | Disable */ | |
523 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject | |
524 | Enable */ | |
525 | ||
526 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. | |
527 | Selection */ | |
528 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor | |
529 | Enable */ | |
530 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor | |
531 | Enable */ | |
532 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation | |
533 | Gated In */ | |
17f50f22 | 534 | |
43c60992 SR |
535 | #endif /* 440EP || 440GR || 440EPX || 440GRX */ |
536 | ||
43c60992 SR |
537 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
538 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
539 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
dbcc3571 NG |
540 | /* CUST0 Customer Configuration Register0 */ |
541 | #define SDR0_CUST0 0x4000 | |
542 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | |
543 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
544 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
545 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
546 | ||
547 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | |
548 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
549 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
550 | ||
551 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
552 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | |
553 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | |
554 | ||
555 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
556 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | |
557 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
558 | ||
559 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
560 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) | |
561 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
562 | ||
563 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
564 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
565 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
566 | ||
567 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
568 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
569 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
570 | ||
571 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
572 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) | |
573 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) | |
574 | ||
575 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | |
576 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | |
577 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ | |
578 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | |
579 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | |
580 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | |
581 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | |
43c60992 | 582 | #endif |
c00b5f85 WD |
583 | |
584 | /*----------------------------------------------------------------------------- | |
585 | | On-Chip Buses | |
586 | +----------------------------------------------------------------------------*/ | |
587 | /* TODO: as needed */ | |
588 | ||
589 | /*----------------------------------------------------------------------------- | |
590 | | Clocking, Power Management and Chip Control | |
591 | +----------------------------------------------------------------------------*/ | |
96e5fc0e FK |
592 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
593 | defined(CONFIG_460SX) | |
43c60992 SR |
594 | #define CNTRL_DCR_BASE 0x160 |
595 | #else | |
c00b5f85 | 596 | #define CNTRL_DCR_BASE 0x0b0 |
43c60992 | 597 | #endif |
5b2052e5 | 598 | |
dbcc3571 NG |
599 | #define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ |
600 | #define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ | |
c00b5f85 | 601 | |
dbcc3571 NG |
602 | #define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ |
603 | #define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ | |
c00b5f85 | 604 | |
dbcc3571 | 605 | #define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ |
5568e613 | 606 | |
dbcc3571 NG |
607 | #define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ |
608 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ | |
c00b5f85 | 609 | |
c00b5f85 WD |
610 | /*----------------------------------------------------------------------------- |
611 | | DMA | |
612 | +----------------------------------------------------------------------------*/ | |
43c60992 SR |
613 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
614 | #define DMA_DCR_BASE 0x200 | |
615 | #else | |
c00b5f85 | 616 | #define DMA_DCR_BASE 0x100 |
43c60992 | 617 | #endif |
d1c3b275 SR |
618 | #define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
619 | #define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
620 | #define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ | |
621 | #define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
622 | #define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ | |
623 | #define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
624 | #define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ | |
625 | #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ | |
626 | #define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
c00b5f85 WD |
627 | |
628 | /*----------------------------------------------------------------------------- | |
629 | | Memory Access Layer | |
630 | +----------------------------------------------------------------------------*/ | |
631 | #define MAL_DCR_BASE 0x180 | |
d1c3b275 SR |
632 | #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ |
633 | #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ | |
634 | #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ | |
635 | #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ | |
636 | #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ | |
dbcc3571 | 637 | #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ |
d1c3b275 SR |
638 | #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ |
639 | #define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ | |
640 | #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ | |
641 | #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ | |
dbcc3571 | 642 | #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ |
d1c3b275 SR |
643 | #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ |
644 | #define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ | |
645 | #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ | |
646 | #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ | |
647 | #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ | |
648 | #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ | |
649 | #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ | |
650 | #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ | |
651 | #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ | |
652 | #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ | |
43c60992 SR |
653 | #if defined(CONFIG_440GX) || \ |
654 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d1c3b275 SR |
655 | #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ |
656 | #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ | |
657 | #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ | |
658 | #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ | |
659 | #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ | |
660 | #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ | |
661 | #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ | |
662 | #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ | |
663 | #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ | |
664 | #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ | |
846b0dd2 | 665 | #endif /* CONFIG_440GX */ |
ba56f625 | 666 | |
0e6d798c | 667 | /*-----------------------------------------------------------------------------+ |
6e7fb6ea | 668 | | SDR0 Bit Settings |
0e6d798c | 669 | +-----------------------------------------------------------------------------*/ |
df294497 | 670 | #if defined(CONFIG_440SP) |
df294497 SR |
671 | #define SDR0_DDR0 0x00E1 |
672 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
673 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
674 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
675 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
676 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
677 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
678 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
679 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
680 | #endif | |
681 | ||
96e5fc0e | 682 | #if defined(CONFIG_440SPE) || defined(CONFIG_460SX) |
6c5879f3 MB |
683 | #define SDR0_CP440 0x0180 |
684 | #define SDR0_CP440_ERPN_MASK 0x30000000 | |
685 | #define SDR0_CP440_ERPN_MASK_HI 0x3000 | |
686 | #define SDR0_CP440_ERPN_MASK_LO 0x0000 | |
687 | #define SDR0_CP440_ERPN_EBC 0x10000000 | |
688 | #define SDR0_CP440_ERPN_EBC_HI 0x1000 | |
689 | #define SDR0_CP440_ERPN_EBC_LO 0x0000 | |
690 | #define SDR0_CP440_ERPN_PCI 0x20000000 | |
691 | #define SDR0_CP440_ERPN_PCI_HI 0x2000 | |
692 | #define SDR0_CP440_ERPN_PCI_LO 0x0000 | |
693 | #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
694 | #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
695 | #define SDR0_CP440_NTO1_MASK 0x00000002 | |
696 | #define SDR0_CP440_NTO1_NTOP 0x00000000 | |
697 | #define SDR0_CP440_NTO1_NTO1 0x00000002 | |
698 | #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
699 | #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
6c5879f3 MB |
700 | |
701 | #define SDR0_SDSTP0 0x0020 | |
702 | #define SDR0_SDSTP0_ENG_MASK 0x80000000 | |
703 | #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 | |
704 | #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 | |
705 | #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
706 | #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
707 | #define SDR0_SDSTP0_SRC_MASK 0x40000000 | |
708 | #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 | |
709 | #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 | |
710 | #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
711 | #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
712 | #define SDR0_SDSTP0_SEL_MASK 0x38000000 | |
713 | #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 | |
714 | #define SDR0_SDSTP0_SEL_CPU 0x08000000 | |
715 | #define SDR0_SDSTP0_SEL_EBC 0x28000000 | |
716 | #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) | |
717 | #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) | |
718 | #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 | |
719 | #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) | |
720 | #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) | |
721 | #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 | |
722 | #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) | |
dbcc3571 | 723 | #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) |
6c5879f3 MB |
724 | #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 |
725 | #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) | |
726 | #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) | |
727 | #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 | |
728 | #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) | |
729 | #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) | |
730 | #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C | |
731 | #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) | |
732 | #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) | |
733 | #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 | |
734 | #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) | |
735 | #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) | |
736 | ||
737 | ||
738 | #define SDR0_SDSTP1 0x0021 | |
739 | #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 | |
740 | #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) | |
741 | #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) | |
742 | #define SDR0_SDSTP1_PERDV0_MASK 0x03000000 | |
743 | #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) | |
744 | #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) | |
745 | #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 | |
746 | #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) | |
747 | #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
748 | #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 | |
749 | #define SDR0_SDSTP1_DDR1_MODE 0x00100000 | |
750 | #define SDR0_SDSTP1_DDR2_MODE 0x00200000 | |
751 | #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) | |
752 | #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) | |
753 | #define SDR0_SDSTP1_ERPN_MASK 0x00080000 | |
754 | #define SDR0_SDSTP1_ERPN_EBC 0x00000000 | |
755 | #define SDR0_SDSTP1_ERPN_PCI 0x00080000 | |
756 | #define SDR0_SDSTP1_PAE_MASK 0x00040000 | |
757 | #define SDR0_SDSTP1_PAE_DISABLE 0x00000000 | |
758 | #define SDR0_SDSTP1_PAE_ENABLE 0x00040000 | |
759 | #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | |
760 | #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | |
761 | #define SDR0_SDSTP1_PHCE_MASK 0x00020000 | |
762 | #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 | |
763 | #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 | |
764 | #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | |
765 | #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | |
766 | #define SDR0_SDSTP1_PISE_MASK 0x00010000 | |
767 | #define SDR0_SDSTP1_PISE_DISABLE 0x00000000 | |
768 | #define SDR0_SDSTP1_PISE_ENABLE 0x00001000 | |
769 | #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | |
770 | #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | |
771 | #define SDR0_SDSTP1_PCWE_MASK 0x00008000 | |
772 | #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 | |
773 | #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 | |
774 | #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | |
775 | #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | |
776 | #define SDR0_SDSTP1_PPIM_MASK 0x00007800 | |
777 | #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | |
778 | #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | |
779 | #define SDR0_SDSTP1_PR64E_MASK 0x00000400 | |
780 | #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 | |
781 | #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 | |
782 | #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) | |
783 | #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) | |
784 | #define SDR0_SDSTP1_PXFS_MASK 0x00000300 | |
785 | #define SDR0_SDSTP1_PXFS_100_133 0x00000000 | |
786 | #define SDR0_SDSTP1_PXFS_66_100 0x00000100 | |
787 | #define SDR0_SDSTP1_PXFS_50_66 0x00000200 | |
788 | #define SDR0_SDSTP1_PXFS_0_50 0x00000300 | |
789 | #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | |
790 | #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | |
791 | #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ | |
792 | #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ | |
793 | #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ | |
794 | #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ | |
795 | #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 | |
796 | #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 | |
dbcc3571 NG |
797 | #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ |
798 | #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ | |
6c5879f3 MB |
799 | #define SDR0_SDSTP1_ETH_MASK 0x00000004 |
800 | #define SDR0_SDSTP1_ETH_10_100 0x00000000 | |
801 | #define SDR0_SDSTP1_ETH_GIGA 0x00000004 | |
802 | #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) | |
803 | #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) | |
804 | #define SDR0_SDSTP1_NTO1_MASK 0x00000001 | |
805 | #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 | |
806 | #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 | |
807 | #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) | |
808 | #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) | |
809 | ||
810 | #define SDR0_SDSTP2 0x0022 | |
811 | #define SDR0_SDSTP2_P1AE_MASK 0x80000000 | |
812 | #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 | |
813 | #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 | |
814 | #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
815 | #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
816 | #define SDR0_SDSTP2_P1HCE_MASK 0x40000000 | |
817 | #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 | |
818 | #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 | |
819 | #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
820 | #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
821 | #define SDR0_SDSTP2_P1ISE_MASK 0x20000000 | |
822 | #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 | |
823 | #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 | |
824 | #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
825 | #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
826 | #define SDR0_SDSTP2_P1CWE_MASK 0x10000000 | |
827 | #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 | |
828 | #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 | |
829 | #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
830 | #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
831 | #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 | |
832 | #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
833 | #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
834 | #define SDR0_SDSTP2_P1R64E_MASK 0x00800000 | |
835 | #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 | |
836 | #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 | |
837 | #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
838 | #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
839 | #define SDR0_SDSTP2_P1XFS_MASK 0x00600000 | |
840 | #define SDR0_SDSTP2_P1XFS_100_133 0x00000000 | |
841 | #define SDR0_SDSTP2_P1XFS_66_100 0x00200000 | |
842 | #define SDR0_SDSTP2_P1XFS_50_66 0x00400000 | |
843 | #define SDR0_SDSTP2_P1XFS_0_50 0x00600000 | |
844 | #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
845 | #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
846 | #define SDR0_SDSTP2_P2AE_MASK 0x00040000 | |
847 | #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 | |
848 | #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 | |
849 | #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) | |
850 | #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) | |
851 | #define SDR0_SDSTP2_P2HCE_MASK 0x00020000 | |
852 | #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 | |
853 | #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 | |
854 | #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) | |
855 | #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) | |
856 | #define SDR0_SDSTP2_P2ISE_MASK 0x00010000 | |
857 | #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 | |
858 | #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 | |
859 | #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) | |
860 | #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) | |
861 | #define SDR0_SDSTP2_P2CWE_MASK 0x00008000 | |
862 | #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 | |
863 | #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 | |
864 | #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) | |
865 | #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) | |
866 | #define SDR0_SDSTP2_P2PIM_MASK 0x00007800 | |
867 | #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) | |
868 | #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) | |
869 | #define SDR0_SDSTP2_P2XFS_MASK 0x00000300 | |
870 | #define SDR0_SDSTP2_P2XFS_100_133 0x00000000 | |
871 | #define SDR0_SDSTP2_P2XFS_66_100 0x00000100 | |
872 | #define SDR0_SDSTP2_P2XFS_50_66 0x00000200 | |
873 | #define SDR0_SDSTP2_P2XFS_0_50 0x00000100 | |
874 | #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) | |
875 | #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) | |
876 | ||
877 | #define SDR0_SDSTP3 0x0023 | |
878 | ||
879 | #define SDR0_PINSTP 0x0040 | |
880 | #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ | |
dbcc3571 NG |
881 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 |
882 | (EBC boot) */ | |
883 | #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 | |
884 | (PCI boot) */ | |
885 | #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - | |
886 | Addr = 0x54 */ | |
887 | #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - | |
888 | Addr = 0x50 */ | |
6c5879f3 MB |
889 | #define SDR0_SDCS 0x0060 |
890 | #define SDR0_ECID0 0x0080 | |
891 | #define SDR0_ECID1 0x0081 | |
892 | #define SDR0_ECID2 0x0082 | |
893 | #define SDR0_JTAG 0x00C0 | |
894 | ||
895 | #define SDR0_DDR0 0x00E1 | |
896 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
897 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
898 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
899 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
900 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
901 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
902 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
903 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
904 | ||
905 | #define SDR0_UART0 0x0120 | |
906 | #define SDR0_UART1 0x0121 | |
907 | #define SDR0_UART2 0x0122 | |
6c5879f3 MB |
908 | #define SDR0_SLPIPE 0x0220 |
909 | ||
910 | #define SDR0_AMP0 0x0240 | |
911 | #define SDR0_AMP0_PRIORITY 0xFFFF0000 | |
912 | #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 | |
913 | #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF | |
914 | ||
915 | #define SDR0_AMP1 0x0241 | |
916 | #define SDR0_AMP1_PRIORITY 0xFC000000 | |
917 | #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 | |
918 | #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF | |
919 | ||
920 | #define SDR0_MIRQ0 0x0260 | |
921 | #define SDR0_MIRQ1 0x0261 | |
922 | #define SDR0_MALTBL 0x0280 | |
923 | #define SDR0_MALRBL 0x02A0 | |
924 | #define SDR0_MALTBS 0x02C0 | |
925 | #define SDR0_MALRBS 0x02E0 | |
926 | ||
927 | /* Reserved for Customer Use */ | |
928 | #define SDR0_CUST0 0x4000 | |
929 | #define SDR0_CUST0_AUTONEG_MASK 0x8000000 | |
930 | #define SDR0_CUST0_NO_AUTONEG 0x0000000 | |
931 | #define SDR0_CUST0_AUTONEG 0x8000000 | |
932 | #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 | |
933 | #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 | |
934 | #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 | |
935 | #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 | |
936 | #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 | |
937 | #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 | |
938 | #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 | |
939 | ||
940 | #define SDR0_SDSTP4 0x4001 | |
941 | #define SDR0_CUST1 0x4002 | |
942 | #define SDR0_SDSTP5 0x4003 | |
943 | #define SDR0_CUST2 0x4004 | |
944 | #define SDR0_SDSTP6 0x4005 | |
945 | #define SDR0_CUST3 0x4006 | |
946 | #define SDR0_SDSTP7 0x4007 | |
947 | ||
948 | #define SDR0_PFC0 0x4100 | |
949 | #define SDR0_PFC0_GPIO_0 0x80000000 | |
950 | #define SDR0_PFC0_PCIX0REQ2_N 0x00000000 | |
951 | #define SDR0_PFC0_GPIO_1 0x40000000 | |
952 | #define SDR0_PFC0_PCIX0REQ3_N 0x00000000 | |
953 | #define SDR0_PFC0_GPIO_2 0x20000000 | |
954 | #define SDR0_PFC0_PCIX0GNT2_N 0x00000000 | |
955 | #define SDR0_PFC0_GPIO_3 0x10000000 | |
956 | #define SDR0_PFC0_PCIX0GNT3_N 0x00000000 | |
957 | #define SDR0_PFC0_GPIO_4 0x08000000 | |
958 | #define SDR0_PFC0_PCIX1REQ2_N 0x00000000 | |
959 | #define SDR0_PFC0_GPIO_5 0x04000000 | |
960 | #define SDR0_PFC0_PCIX1REQ3_N 0x00000000 | |
961 | #define SDR0_PFC0_GPIO_6 0x02000000 | |
962 | #define SDR0_PFC0_PCIX1GNT2_N 0x00000000 | |
963 | #define SDR0_PFC0_GPIO_7 0x01000000 | |
964 | #define SDR0_PFC0_PCIX1GNT3_N 0x00000000 | |
965 | #define SDR0_PFC0_GPIO_8 0x00800000 | |
966 | #define SDR0_PFC0_PERREADY 0x00000000 | |
967 | #define SDR0_PFC0_GPIO_9 0x00400000 | |
968 | #define SDR0_PFC0_PERCS1_N 0x00000000 | |
969 | #define SDR0_PFC0_GPIO_10 0x00200000 | |
970 | #define SDR0_PFC0_PERCS2_N 0x00000000 | |
971 | #define SDR0_PFC0_GPIO_11 0x00100000 | |
972 | #define SDR0_PFC0_IRQ0 0x00000000 | |
973 | #define SDR0_PFC0_GPIO_12 0x00080000 | |
974 | #define SDR0_PFC0_IRQ1 0x00000000 | |
975 | #define SDR0_PFC0_GPIO_13 0x00040000 | |
976 | #define SDR0_PFC0_IRQ2 0x00000000 | |
977 | #define SDR0_PFC0_GPIO_14 0x00020000 | |
978 | #define SDR0_PFC0_IRQ3 0x00000000 | |
979 | #define SDR0_PFC0_GPIO_15 0x00010000 | |
980 | #define SDR0_PFC0_IRQ4 0x00000000 | |
981 | #define SDR0_PFC0_GPIO_16 0x00008000 | |
982 | #define SDR0_PFC0_IRQ5 0x00000000 | |
983 | #define SDR0_PFC0_GPIO_17 0x00004000 | |
984 | #define SDR0_PFC0_PERBE0_N 0x00000000 | |
985 | #define SDR0_PFC0_GPIO_18 0x00002000 | |
986 | #define SDR0_PFC0_PCI0GNT0_N 0x00000000 | |
987 | #define SDR0_PFC0_GPIO_19 0x00001000 | |
988 | #define SDR0_PFC0_PCI0GNT1_N 0x00000000 | |
989 | #define SDR0_PFC0_GPIO_20 0x00000800 | |
990 | #define SDR0_PFC0_PCI0REQ0_N 0x00000000 | |
991 | #define SDR0_PFC0_GPIO_21 0x00000400 | |
992 | #define SDR0_PFC0_PCI0REQ1_N 0x00000000 | |
993 | #define SDR0_PFC0_GPIO_22 0x00000200 | |
994 | #define SDR0_PFC0_PCI1GNT0_N 0x00000000 | |
995 | #define SDR0_PFC0_GPIO_23 0x00000100 | |
996 | #define SDR0_PFC0_PCI1GNT1_N 0x00000000 | |
997 | #define SDR0_PFC0_GPIO_24 0x00000080 | |
998 | #define SDR0_PFC0_PCI1REQ0_N 0x00000000 | |
999 | #define SDR0_PFC0_GPIO_25 0x00000040 | |
1000 | #define SDR0_PFC0_PCI1REQ1_N 0x00000000 | |
1001 | #define SDR0_PFC0_GPIO_26 0x00000020 | |
1002 | #define SDR0_PFC0_PCI2GNT0_N 0x00000000 | |
1003 | #define SDR0_PFC0_GPIO_27 0x00000010 | |
1004 | #define SDR0_PFC0_PCI2GNT1_N 0x00000000 | |
1005 | #define SDR0_PFC0_GPIO_28 0x00000008 | |
1006 | #define SDR0_PFC0_PCI2REQ0_N 0x00000000 | |
1007 | #define SDR0_PFC0_GPIO_29 0x00000004 | |
1008 | #define SDR0_PFC0_PCI2REQ1_N 0x00000000 | |
1009 | #define SDR0_PFC0_GPIO_30 0x00000002 | |
1010 | #define SDR0_PFC0_UART1RX 0x00000000 | |
1011 | #define SDR0_PFC0_GPIO_31 0x00000001 | |
1012 | #define SDR0_PFC0_UART1TX 0x00000000 | |
1013 | ||
1014 | #define SDR0_PFC1 0x4101 | |
1015 | #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 | |
1016 | #define SDR0_PFC1_UART1_DSR_DTR 0x00000000 | |
1017 | #define SDR0_PFC1_UART1_CTS_RTS 0x02000000 | |
1018 | #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 | |
1019 | #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 | |
1020 | #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 | |
1021 | #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 | |
1022 | #define SDR0_PFC1_ETH_10_100 0x00000000 | |
1023 | #define SDR0_PFC1_ETH_GIGA 0x00200000 | |
1024 | #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) | |
1025 | #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | |
1026 | #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ | |
1027 | #define SDR0_PFC1_CPU_NO_TRACE 0x00000000 | |
1028 | #define SDR0_PFC1_CPU_TRACE 0x00080000 | |
dbcc3571 NG |
1029 | #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) |
1030 | /* $218C */ | |
1031 | #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) | |
1032 | /* $218C */ | |
6c5879f3 MB |
1033 | |
1034 | #define SDR0_MFR 0x4300 | |
1035 | #endif /* CONFIG_440SPE */ | |
1036 | ||
43c60992 SR |
1037 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
1038 | /* Pin Function Control Register 0 (SDR0_PFC0) */ | |
1039 | #define SDR0_PFC0 0x4100 | |
1040 | #define SDR0_PFC0_DBG 0x00008000 /* debug enable */ | |
1041 | #define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */ | |
1042 | #define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */ | |
1043 | #define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */ | |
1044 | #define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */ | |
1045 | #define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */ | |
1046 | #define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */ | |
1047 | #define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */ | |
1048 | #define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */ | |
1049 | #define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */ | |
1050 | #define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */ | |
1051 | #define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */ | |
1052 | #define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */ | |
1053 | #define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */ | |
1054 | #define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */ | |
1055 | #define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */ | |
1056 | ||
1057 | /* Pin Function Control Register 1 (SDR0_PFC1) */ | |
1058 | #define SDR0_PFC1 0x4101 | |
1059 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
1060 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
1061 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
1062 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
1063 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
1064 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
1065 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
1066 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/ | |
1067 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/ | |
1068 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
1069 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
1070 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
1071 | ||
89bcc487 SR |
1072 | #define SDR0_ECID0 0x0080 |
1073 | #define SDR0_ECID1 0x0081 | |
1074 | #define SDR0_ECID2 0x0082 | |
1075 | #define SDR0_ECID3 0x0083 | |
1076 | ||
43c60992 SR |
1077 | /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ |
1078 | #define SDR0_ETH_PLL 0x4102 | |
1079 | #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ | |
1080 | #define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */ | |
1081 | #define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */ | |
1082 | #define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */ | |
1083 | #define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */ | |
1084 | #define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16) | |
1085 | #define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */ | |
1086 | #define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8) | |
1087 | #define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */ | |
1088 | #define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4) | |
1089 | #define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */ | |
1090 | #define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f) | |
1091 | ||
1092 | /* Ethernet Configuration Register (SDR0_ETH_CFG) */ | |
1093 | #define SDR0_ETH_CFG 0x4103 | |
dbcc3571 NG |
1094 | #define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback |
1095 | enable */ | |
1096 | #define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback | |
1097 | enable */ | |
1098 | #define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback | |
1099 | enable */ | |
1100 | #define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback | |
1101 | enable */ | |
1102 | #define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ | |
1103 | #define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ | |
1104 | #define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ | |
1105 | #define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ | |
1106 | #define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ | |
1107 | #define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ | |
1108 | #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ | |
1109 | #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ | |
1110 | #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ | |
1111 | #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ | |
1112 | #define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ | |
1113 | #define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ | |
1114 | #define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ | |
1115 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ | |
1116 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ | |
1117 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ | |
1118 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ | |
1119 | #define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /*ZMII bridge mode selector | |
1120 | mask */ | |
1121 | #define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /*ZMII bridge mode - MII */ | |
1122 | #define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /*ZMII bridge mode - SMII */ | |
1123 | #define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /*ZMII bridge mode - RMII | |
1124 | (10 Mbps) */ | |
1125 | #define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /*ZMII bridge mode - RMII | |
1126 | (100 Mbps) */ | |
1127 | #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge | |
1128 | selector */ | |
1129 | #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge | |
1130 | selector */ | |
43c60992 SR |
1131 | |
1132 | #define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4 | |
1133 | #define SDR0_ETH_CFG_ZMII_MII_MODE 0x00 | |
1134 | #define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01 | |
1135 | #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 | |
1136 | #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 | |
1137 | ||
f09f09d3 AG |
1138 | /* Ethernet Status Register */ |
1139 | #define SDR0_ETH_STS 0x4104 | |
1140 | ||
43c60992 SR |
1141 | /* Miscealleneaous Function Reg. (SDR0_MFR) */ |
1142 | #define SDR0_MFR 0x4300 | |
dbcc3571 NG |
1143 | #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx |
1144 | FIFO bits 0:63 */ | |
1145 | #define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx | |
1146 | FIFO bits 64:127 */ | |
1147 | #define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx | |
1148 | FIFO bits 0:63 */ | |
1149 | #define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx | |
1150 | FIFO bits 64:127 */ | |
1151 | #define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx | |
1152 | FIFO bits 0:63 */ | |
1153 | #define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx | |
1154 | FIFO bits 64:127 */ | |
1155 | #define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx | |
1156 | FIFO bits 0:63 */ | |
1157 | #define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx | |
1158 | FIFO bits 64:127 */ | |
1159 | #define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx | |
1160 | FIFO bits 0:63 */ | |
1161 | #define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx | |
1162 | FIFO bits 64:127 */ | |
1163 | #define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx | |
1164 | FIFO bits 0:63 */ | |
1165 | #define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx | |
1166 | FIFO bits 64:127 */ | |
1167 | #define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx | |
1168 | FIFO bits 0:63 */ | |
1169 | #define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx | |
1170 | FIFO bits 64:127 */ | |
1171 | #define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx | |
1172 | FIFO bits 0:63 */ | |
1173 | #define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx | |
1174 | FIFO bits 64:127 */ | |
1175 | #define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx | |
1176 | FIFO bits 0:63 */ | |
1177 | #define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx | |
1178 | FIFO bits 64:127 */ | |
1179 | #define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx | |
1180 | FIFO bits 0:63 */ | |
1181 | #define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx | |
1182 | FIFO bits 64:127 */ | |
43c60992 SR |
1183 | |
1184 | /* EMACx TX Status Register (SDR0_EMACxTXST)*/ | |
1185 | #define SDR0_EMAC0TXST 0x4400 | |
1186 | #define SDR0_EMAC1TXST 0x4401 | |
1187 | #define SDR0_EMAC2TXST 0x4402 | |
1188 | #define SDR0_EMAC3TXST 0x4403 | |
1189 | ||
dbcc3571 NG |
1190 | #define SDR0_EMACxTXST_FUR 0x02000000 /*TX FIFO underrun */ |
1191 | #define SDR0_EMACxTXST_BC 0x01000000 /*broadcase address */ | |
1192 | #define SDR0_EMACxTXST_MC 0x00800000 /*multicast address */ | |
1193 | #define SDR0_EMACxTXST_UC 0x00400000 /*unicast address */ | |
1194 | #define SDR0_EMACxTXST_FP 0x00200000 /*frame paused by control packet */ | |
1195 | #define SDR0_EMACxTXST_BFCS 0x00100000 /*bad FCS in the transmitted frame */ | |
1196 | #define SDR0_EMACxTXST_CPF 0x00080000 /*TX control pause frame */ | |
1197 | #define SDR0_EMACxTXST_CF 0x00040000 /*TX control frame */ | |
1198 | #define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ | |
1199 | #define SDR0_EMACxTXST_1023 0x00010000 /*512-1023 bytes transmitted */ | |
1200 | #define SDR0_EMACxTXST_511 0x00008000 /*256-511 bytes transmitted */ | |
1201 | #define SDR0_EMACxTXST_255 0x00004000 /*128-255 bytes transmitted */ | |
1202 | #define SDR0_EMACxTXST_127 0x00002000 /*65-127 bytes transmitted */ | |
1203 | #define SDR0_EMACxTXST_64 0x00001000 /*64 bytes transmitted */ | |
1204 | #define SDR0_EMACxTXST_SQE 0x00000800 /*SQE indication */ | |
1205 | #define SDR0_EMACxTXST_LOC 0x00000400 /*loss of carrier sense */ | |
1206 | #define SDR0_EMACxTXST_IERR 0x00000080 /*EMAC internal error */ | |
1207 | #define SDR0_EMACxTXST_EDF 0x00000040 /*excessive deferral */ | |
1208 | #define SDR0_EMACxTXST_ECOL 0x00000020 /*excessive collisions */ | |
1209 | #define SDR0_EMACxTXST_LCOL 0x00000010 /*late collision */ | |
1210 | #define SDR0_EMACxTXST_DFFR 0x00000008 /*deferred frame */ | |
1211 | #define SDR0_EMACxTXST_MCOL 0x00000004 /*multiple collision frame */ | |
1212 | #define SDR0_EMACxTXST_SCOL 0x00000002 /*single collision frame */ | |
1213 | #define SDR0_EMACxTXST_TXOK 0x00000001 /*transmit OK */ | |
43c60992 SR |
1214 | |
1215 | /* EMACx RX Status Register (SDR0_EMACxRXST)*/ | |
1216 | #define SDR0_EMAC0RXST 0x4404 | |
1217 | #define SDR0_EMAC1RXST 0x4405 | |
1218 | #define SDR0_EMAC2RXST 0x4406 | |
1219 | #define SDR0_EMAC3RXST 0x4407 | |
1220 | ||
1221 | #define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */ | |
1222 | #define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */ | |
1223 | #define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */ | |
1224 | #define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */ | |
1225 | #define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */ | |
1226 | #define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23) | |
1227 | #define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */ | |
1228 | #define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */ | |
1229 | #define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */ | |
1230 | #define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */ | |
1231 | #define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/ | |
1232 | #define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/ | |
1233 | #define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */ | |
1234 | #define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */ | |
1235 | #define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */ | |
1236 | #define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */ | |
1237 | #define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */ | |
1238 | #define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */ | |
1239 | #define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */ | |
1240 | #define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */ | |
1241 | #define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */ | |
1242 | #define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */ | |
1243 | #define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */ | |
1244 | #define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */ | |
1245 | #define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */ | |
dbcc3571 NG |
1246 | #define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal |
1247 | EMAC receive error */ | |
1248 | #define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ | |
43c60992 SR |
1249 | #define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */ |
1250 | ||
1251 | /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/ | |
1252 | #define SDR0_EMAC0REJCNT 0x4408 | |
1253 | #define SDR0_EMAC1REJCNT 0x4409 | |
1254 | #define SDR0_EMAC2REJCNT 0x440A | |
1255 | #define SDR0_EMAC3REJCNT 0x440B | |
1256 | ||
1257 | #define SDR0_DDR0 0x00E1 | |
1258 | #define SDR0_DDR0_DPLLRST 0x80000000 | |
1259 | #define SDR0_DDR0_DDRM_MASK 0x60000000 | |
1260 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
1261 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
1262 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) | |
1263 | #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) | |
1264 | #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) | |
1265 | #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) | |
41712b4e SR |
1266 | |
1267 | #define AHB_TOP 0xA4 | |
1268 | #define AHB_BOT 0xA5 | |
745d8a0d SR |
1269 | #define SDR0_AHB_CFG 0x370 |
1270 | #define SDR0_USB2HOST_CFG 0x371 | |
43c60992 | 1271 | #endif /* CONFIG_460EX || CONFIG_460GT */ |
6c5879f3 | 1272 | |
6e7fb6ea SR |
1273 | #define SDR0_SDCS_SDD (0x80000000 >> 31) |
1274 | ||
1275 | #if defined(CONFIG_440GP) | |
1276 | #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) | |
1277 | #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) | |
1278 | #endif /* defined(CONFIG_440GP) */ | |
a760b020 SR |
1279 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ |
1280 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
6e7fb6ea SR |
1281 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) |
1282 | #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) | |
1283 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ | |
887e2ec9 SR |
1284 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
1285 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6e7fb6ea SR |
1286 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) |
1287 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) | |
1288 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ | |
63153492 WD |
1289 | |
1290 | #define SDR0_UARTX_UXICS_MASK 0xF0000000 | |
1291 | #define SDR0_UARTX_UXICS_PLB 0x20000000 | |
1292 | #define SDR0_UARTX_UXEC_MASK 0x00800000 | |
1293 | #define SDR0_UARTX_UXEC_INT 0x00000000 | |
1294 | #define SDR0_UARTX_UXEC_EXT 0x00800000 | |
1295 | #define SDR0_UARTX_UXDTE_MASK 0x00400000 | |
1296 | #define SDR0_UARTX_UXDTE_DISABLE 0x00000000 | |
1297 | #define SDR0_UARTX_UXDTE_ENABLE 0x00400000 | |
1298 | #define SDR0_UARTX_UXDRE_MASK 0x00200000 | |
1299 | #define SDR0_UARTX_UXDRE_DISABLE 0x00000000 | |
1300 | #define SDR0_UARTX_UXDRE_ENABLE 0x00200000 | |
1301 | #define SDR0_UARTX_UXDC_MASK 0x00100000 | |
1302 | #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 | |
1303 | #define SDR0_UARTX_UXDC_CLEARED 0x00100000 | |
1304 | #define SDR0_UARTX_UXDIV_MASK 0x000000FF | |
1305 | #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) | |
1306 | #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) | |
1307 | ||
1308 | #define SDR0_CPU440_EARV_MASK 0x30000000 | |
1309 | #define SDR0_CPU440_EARV_EBC 0x10000000 | |
1310 | #define SDR0_CPU440_EARV_PCI 0x20000000 | |
1311 | #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) | |
1312 | #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) | |
1313 | #define SDR0_CPU440_NTO1_MASK 0x00000002 | |
1314 | #define SDR0_CPU440_NTO1_NTOP 0x00000000 | |
1315 | #define SDR0_CPU440_NTO1_NTO1 0x00000002 | |
1316 | #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) | |
1317 | #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) | |
1318 | ||
1319 | #define SDR0_XCR_PAE_MASK 0x80000000 | |
1320 | #define SDR0_XCR_PAE_DISABLE 0x00000000 | |
1321 | #define SDR0_XCR_PAE_ENABLE 0x80000000 | |
1322 | #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) | |
1323 | #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) | |
1324 | #define SDR0_XCR_PHCE_MASK 0x40000000 | |
1325 | #define SDR0_XCR_PHCE_DISABLE 0x00000000 | |
1326 | #define SDR0_XCR_PHCE_ENABLE 0x40000000 | |
1327 | #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) | |
1328 | #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) | |
1329 | #define SDR0_XCR_PISE_MASK 0x20000000 | |
1330 | #define SDR0_XCR_PISE_DISABLE 0x00000000 | |
1331 | #define SDR0_XCR_PISE_ENABLE 0x20000000 | |
1332 | #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) | |
1333 | #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) | |
1334 | #define SDR0_XCR_PCWE_MASK 0x10000000 | |
1335 | #define SDR0_XCR_PCWE_DISABLE 0x00000000 | |
1336 | #define SDR0_XCR_PCWE_ENABLE 0x10000000 | |
1337 | #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) | |
1338 | #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) | |
1339 | #define SDR0_XCR_PPIM_MASK 0x0F000000 | |
1340 | #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) | |
1341 | #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
1342 | #define SDR0_XCR_PR64E_MASK 0x00800000 | |
1343 | #define SDR0_XCR_PR64E_DISABLE 0x00000000 | |
1344 | #define SDR0_XCR_PR64E_ENABLE 0x00800000 | |
1345 | #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) | |
1346 | #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) | |
1347 | #define SDR0_XCR_PXFS_MASK 0x00600000 | |
1348 | #define SDR0_XCR_PXFS_HIGH 0x00000000 | |
1349 | #define SDR0_XCR_PXFS_MED 0x00200000 | |
1350 | #define SDR0_XCR_PXFS_LOW 0x00400000 | |
1351 | #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) | |
1352 | #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) | |
1353 | #define SDR0_XCR_PDM_MASK 0x00000040 | |
1354 | #define SDR0_XCR_PDM_MULTIPOINT 0x00000000 | |
1355 | #define SDR0_XCR_PDM_P2P 0x00000040 | |
1356 | #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) | |
1357 | #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) | |
0e6d798c WD |
1358 | |
1359 | #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 | |
63153492 WD |
1360 | #define SDR0_PFC0_GEIE_MASK 0x00003E00 |
1361 | #define SDR0_PFC0_GEIE_TRE 0x00003E00 | |
1362 | #define SDR0_PFC0_GEIE_NOTRE 0x00000000 | |
1363 | #define SDR0_PFC0_TRE_MASK 0x00000100 | |
1364 | #define SDR0_PFC0_TRE_DISABLE 0x00000000 | |
1365 | #define SDR0_PFC0_TRE_ENABLE 0x00000100 | |
1366 | #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) | |
1367 | #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) | |
1368 | ||
1369 | #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 | |
1370 | #define SDR0_PFC1_EPS_MASK 0x01C00000 | |
1371 | #define SDR0_PFC1_EPS_GROUP0 0x00000000 | |
1372 | #define SDR0_PFC1_EPS_GROUP1 0x00400000 | |
1373 | #define SDR0_PFC1_EPS_GROUP2 0x00800000 | |
1374 | #define SDR0_PFC1_EPS_GROUP3 0x00C00000 | |
1375 | #define SDR0_PFC1_EPS_GROUP4 0x01000000 | |
1376 | #define SDR0_PFC1_EPS_GROUP5 0x01400000 | |
1377 | #define SDR0_PFC1_EPS_GROUP6 0x01800000 | |
1378 | #define SDR0_PFC1_EPS_GROUP7 0x01C00000 | |
1379 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | |
1380 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | |
1381 | #define SDR0_PFC1_RMII_MASK 0x00200000 | |
1382 | #define SDR0_PFC1_RMII_100MBIT 0x00000000 | |
1383 | #define SDR0_PFC1_RMII_10MBIT 0x00200000 | |
1384 | #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) | |
1385 | #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) | |
1386 | #define SDR0_PFC1_CTEMS_MASK 0x00100000 | |
1387 | #define SDR0_PFC1_CTEMS_EMS 0x00000000 | |
1388 | #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 | |
1389 | ||
1390 | #define SDR0_MFR_TAH0_MASK 0x80000000 | |
1391 | #define SDR0_MFR_TAH0_ENABLE 0x00000000 | |
1392 | #define SDR0_MFR_TAH0_DISABLE 0x80000000 | |
1393 | #define SDR0_MFR_TAH1_MASK 0x40000000 | |
1394 | #define SDR0_MFR_TAH1_ENABLE 0x00000000 | |
1395 | #define SDR0_MFR_TAH1_DISABLE 0x40000000 | |
1396 | #define SDR0_MFR_PCM_MASK 0x20000000 | |
1397 | #define SDR0_MFR_PCM_PPC440GX 0x00000000 | |
1398 | #define SDR0_MFR_PCM_PPC440GP 0x20000000 | |
1399 | #define SDR0_MFR_ECS_MASK 0x10000000 | |
1400 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | |
1401 | ||
dbcc3571 NG |
1402 | #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ |
1403 | #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ | |
1404 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
1405 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
1406 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
1407 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
1408 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs*/ | |
1409 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
1410 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
1411 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
1412 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
887e2ec9 | 1413 | #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ |
dbcc3571 NG |
1414 | #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ |
1415 | #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 | |
1416 | 0-1 */ | |
1417 | #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ | |
1418 | #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ | |
1419 | #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ | |
887e2ec9 SR |
1420 | #endif |
1421 | ||
f80e61dc NG |
1422 | |
1423 | #if defined(CONFIG_440EPX) | |
1424 | #define CPM0_ER 0x000000B0 | |
1425 | #define CPM1_ER 0x000000F0 | |
1426 | #define PLB4A0_ACR 0x00000081 | |
1427 | #define PLB4A1_ACR 0x00000089 | |
1428 | #define PLB3A0_ACR 0x00000077 | |
1429 | #define OPB2PLB40_BCTRL 0x00000350 | |
1430 | #define P4P3BO0_CFG 0x00000026 | |
1431 | #define SPI0_MODE 0xEF600090 /* SPI Mode Regsgiter */ | |
1432 | ||
1433 | #endif | |
1434 | ||
887e2ec9 SR |
1435 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1436 | #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) | |
1437 | #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) | |
1438 | #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) | |
1439 | #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) | |
1440 | #endif | |
1441 | ||
1442 | #define SDR0_MFR_ECS_MASK 0x10000000 | |
1443 | #define SDR0_MFR_ECS_INTERNAL 0x10000000 | |
1444 | ||
1445 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
dbcc3571 NG |
1446 | #define SDR0_SRST0 0x200 |
1447 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ | |
1448 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | |
1449 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | |
1450 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | |
1451 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ | |
1452 | transmitter 0 */ | |
1453 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ | |
1454 | transmitter 1 */ | |
1455 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ | |
1456 | #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ | |
1457 | #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ | |
1458 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | |
1459 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | |
1460 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | |
1461 | #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ | |
1462 | #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ | |
1463 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | |
1464 | #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ | |
1465 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ | |
1466 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ | |
1467 | #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ | |
1468 | #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ | |
1469 | #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ | |
1470 | #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ | |
1471 | #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ | |
1472 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ | |
1473 | #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ | |
1474 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | |
1475 | #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ | |
1476 | #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ | |
1477 | #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ | |
1478 | #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ | |
1479 | transmitter 2 */ | |
1480 | #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ | |
1481 | transmitter 3 */ | |
1482 | ||
1483 | #define SDR0_SRST1 0x201 | |
1484 | #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ | |
1485 | #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ | |
1486 | #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ | |
887e2ec9 | 1487 | #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 |
dbcc3571 NG |
1488 | #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ |
1489 | #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ | |
1490 | #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 | |
1491 | USB 2.0 Host */ | |
1492 | #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to | |
1493 | USB 2.0 Host */ | |
1494 | #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to | |
1495 | USB 2.0 Host */ | |
1496 | #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ | |
1497 | #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ | |
1498 | #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ | |
1499 | #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ | |
1500 | #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ | |
1501 | #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ | |
1502 | #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ | |
1503 | #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ | |
1504 | #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ | |
1505 | #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ | |
1506 | #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ | |
887e2ec9 | 1507 | |
f80e61dc NG |
1508 | #define SDR0_EMAC0RXST 0x00004301 /* */ |
1509 | #define SDR0_EMAC0TXST 0x00004302 /* */ | |
1510 | #define SDR0_CRYP0 0x00004500 | |
1511 | #define SDR0_EBC0 0x00000100 | |
1512 | #define SDR0_SDSTP2 0x00004001 | |
1513 | #define SDR0_SDSTP3 0x00004001 | |
43c60992 SR |
1514 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
1515 | ||
d1c3b275 | 1516 | #define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ |
43c60992 SR |
1517 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ |
1518 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ | |
1519 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ | |
1520 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ | |
dbcc3571 NG |
1521 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ |
1522 | transmitter 0 */ | |
1523 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ | |
1524 | transmitter 1 */ | |
43c60992 SR |
1525 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ |
1526 | #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ | |
1527 | #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ | |
1528 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ | |
1529 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ | |
1530 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ | |
1531 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ | |
1532 | #define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ | |
1533 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ | |
1534 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ | |
1535 | #define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ | |
1536 | #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ | |
1537 | #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ | |
1538 | #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ | |
dbcc3571 NG |
1539 | #define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ |
1540 | transmitter 2 */ | |
43c60992 SR |
1541 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ |
1542 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ | |
1543 | #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ | |
dbcc3571 NG |
1544 | #define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ |
1545 | transmitter 3 */ | |
43c60992 SR |
1546 | #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ |
1547 | ||
1548 | #define SDR0_SRST1 0x201 | |
1549 | #define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ | |
1550 | #define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ | |
1551 | #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ | |
1552 | #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ | |
1553 | #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ | |
dbcc3571 NG |
1554 | #define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access |
1555 | controller 0 */ | |
1556 | #define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access | |
1557 | controller 1 */ | |
1558 | #define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access | |
1559 | controller 2 */ | |
1560 | #define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access | |
1561 | controller 3 */ | |
43c60992 SR |
1562 | #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ |
1563 | #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ | |
1564 | #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ | |
1565 | #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ | |
1566 | #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ | |
1567 | #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ | |
dbcc3571 NG |
1568 | #define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and |
1569 | serdes */ | |
43c60992 SR |
1570 | #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ |
1571 | #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ | |
1572 | #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ | |
1573 | #define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ | |
1574 | #define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ | |
1575 | #define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ | |
1576 | #define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ | |
1577 | #define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ | |
1578 | #define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ | |
1579 | #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ | |
1580 | #define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ | |
1581 | #define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ | |
1582 | #define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ | |
1583 | #define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ | |
1584 | #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ | |
1585 | #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ | |
1586 | ||
887e2ec9 | 1587 | #else |
c157d8e2 | 1588 | |
63153492 WD |
1589 | #define SDR0_SRST_BGO 0x80000000 |
1590 | #define SDR0_SRST_PLB 0x40000000 | |
1591 | #define SDR0_SRST_EBC 0x20000000 | |
1592 | #define SDR0_SRST_OPB 0x10000000 | |
1593 | #define SDR0_SRST_UART0 0x08000000 | |
1594 | #define SDR0_SRST_UART1 0x04000000 | |
1595 | #define SDR0_SRST_IIC0 0x02000000 | |
1596 | #define SDR0_SRST_IIC1 0x01000000 | |
1597 | #define SDR0_SRST_GPIO 0x00800000 | |
1598 | #define SDR0_SRST_GPT 0x00400000 | |
1599 | #define SDR0_SRST_DMC 0x00200000 | |
1600 | #define SDR0_SRST_PCI 0x00100000 | |
1601 | #define SDR0_SRST_EMAC0 0x00080000 | |
1602 | #define SDR0_SRST_EMAC1 0x00040000 | |
1603 | #define SDR0_SRST_CPM 0x00020000 | |
1604 | #define SDR0_SRST_IMU 0x00010000 | |
1605 | #define SDR0_SRST_UIC01 0x00008000 | |
1606 | #define SDR0_SRST_UICB2 0x00004000 | |
1607 | #define SDR0_SRST_SRAM 0x00002000 | |
1608 | #define SDR0_SRST_EBM 0x00001000 | |
1609 | #define SDR0_SRST_BGI 0x00000800 | |
1610 | #define SDR0_SRST_DMA 0x00000400 | |
1611 | #define SDR0_SRST_DMAC 0x00000200 | |
1612 | #define SDR0_SRST_MAL 0x00000100 | |
1613 | #define SDR0_SRST_ZMII 0x00000080 | |
1614 | #define SDR0_SRST_GPTR 0x00000040 | |
1615 | #define SDR0_SRST_PPM 0x00000020 | |
1616 | #define SDR0_SRST_EMAC2 0x00000010 | |
1617 | #define SDR0_SRST_EMAC3 0x00000008 | |
1618 | #define SDR0_SRST_RGMII 0x00000001 | |
0e6d798c | 1619 | |
887e2ec9 SR |
1620 | #endif |
1621 | ||
c00b5f85 WD |
1622 | /*-----------------------------------------------------------------------------+ |
1623 | | Clocking | |
1624 | +-----------------------------------------------------------------------------*/ | |
96e5fc0e FK |
1625 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
1626 | defined(CONFIG_460SX) | |
43c60992 SR |
1627 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
1628 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ | |
1629 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ | |
1630 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ | |
1631 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ | |
1632 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
1633 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ | |
1634 | #elif !defined (CONFIG_440GX) && \ | |
887e2ec9 SR |
1635 | !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ |
1636 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
1637 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) | |
ba56f625 WD |
1638 | #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ |
1639 | #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ | |
1640 | #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ | |
1641 | #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ | |
1642 | #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ | |
1643 | #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ | |
1644 | #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ | |
1645 | #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ | |
1646 | #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ | |
1647 | #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ | |
1648 | #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ | |
1649 | #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
1650 | ||
1651 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ | |
1652 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
1653 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
1654 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
846b0dd2 | 1655 | #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ |
ba56f625 WD |
1656 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ |
1657 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | |
dbcc3571 | 1658 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ |
ba56f625 WD |
1659 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ |
1660 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | |
1661 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | |
1662 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | |
1663 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | |
1664 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | |
1665 | ||
dbcc3571 | 1666 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ |
c157d8e2 SR |
1667 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ |
1668 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | |
1669 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | |
1670 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | |
1671 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | |
1672 | ||
1673 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | |
1674 | #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ | |
1675 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ | |
1676 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | |
1677 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | |
1678 | ||
ba56f625 WD |
1679 | #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ |
1680 | #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ | |
1681 | #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ | |
1682 | #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ | |
1683 | ||
1684 | /* Strap 1 Register */ | |
1685 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | |
1686 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
1687 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | |
1688 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | |
1689 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ | |
1690 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ | |
1691 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | |
1692 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | |
1693 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | |
1694 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | |
1695 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | |
1696 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | |
1697 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | |
1698 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | |
1699 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | |
1700 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | |
1701 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | |
1702 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
846b0dd2 | 1703 | #endif /* CONFIG_440GX */ |
c00b5f85 | 1704 | |
5e47f953 SR |
1705 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
1706 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
26173fc6 SR |
1707 | #define CPR0_ICFG_RLI_MASK 0x80000000 |
1708 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 | |
5e47f953 SR |
1709 | #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 |
1710 | #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 | |
1711 | #define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 | |
1712 | #define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 | |
26173fc6 | 1713 | #define CPR0_PERD_PERDV0_MASK 0x07000000 |
887e2ec9 | 1714 | #endif |
887e2ec9 | 1715 | |
c00b5f85 WD |
1716 | /*----------------------------------------------------------------------------- |
1717 | | PCI Internal Registers et. al. (accessed via plb) | |
1718 | +----------------------------------------------------------------------------*/ | |
f80e61dc NG |
1719 | #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) |
1720 | #define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) | |
1721 | #define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) | |
1722 | #define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) | |
0e6d798c | 1723 | |
887e2ec9 SR |
1724 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
1725 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
c157d8e2 SR |
1726 | |
1727 | /* PCI Local Configuration Registers | |
1728 | --------------------------------- */ | |
dbcc3571 NG |
1729 | #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => |
1730 | 0x0EF400000 */ | |
c157d8e2 SR |
1731 | |
1732 | /* PCI Master Local Configuration Registers */ | |
dbcc3571 NG |
1733 | #define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ |
1734 | #define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | |
1735 | #define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | |
1736 | #define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | |
1737 | #define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | |
1738 | #define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | |
1739 | #define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | |
1740 | #define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | |
1741 | #define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | |
1742 | #define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | |
1743 | #define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | |
1744 | #define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | |
c157d8e2 SR |
1745 | |
1746 | /* PCI Target Local Configuration Registers */ | |
dbcc3571 NG |
1747 | #define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ |
1748 | Attribute */ | |
1749 | #define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | |
1750 | #define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ | |
1751 | Attribute */ | |
1752 | #define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | |
c157d8e2 SR |
1753 | |
1754 | #else | |
1755 | ||
f80e61dc NG |
1756 | #define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) |
1757 | #define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) | |
1758 | #define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) | |
1759 | #define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) | |
1760 | #define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) | |
1761 | #define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) | |
1762 | #define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) | |
1763 | #define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) | |
1764 | #define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) | |
1765 | #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) | |
1766 | #define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) | |
1767 | #define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) | |
1768 | #define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) | |
1769 | #define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) | |
1770 | #define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) | |
1771 | #define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) | |
1772 | #define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) | |
1773 | #define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) | |
1774 | #define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) | |
1775 | #define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) | |
1776 | #define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) | |
1777 | #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) | |
1778 | #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) | |
1779 | #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) | |
1780 | #define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) | |
1781 | #define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) | |
dbcc3571 NG |
1782 | #define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ |
1783 | #define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ | |
1784 | #define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ | |
1785 | #define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ | |
1786 | #define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ | |
1787 | #define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame*/ | |
1788 | #define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ | |
1789 | #define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ | |
1790 | #define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ | |
1791 | #define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ | |
1792 | #define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ | |
1793 | #define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ | |
1794 | #define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ | |
1795 | #define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ | |
1796 | #define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ | |
1797 | #define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ | |
1798 | #define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ | |
1799 | #define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ | |
1800 | #define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ | |
1801 | #define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ | |
1802 | #define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ | |
1803 | #define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ | |
1804 | #define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ | |
1805 | #define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ | |
1806 | ||
f80e61dc NG |
1807 | #define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) |
1808 | #define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) | |
1809 | ||
1810 | #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) | |
1811 | #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) | |
1812 | ||
1813 | #define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) | |
1814 | #define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) | |
1815 | #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) | |
1816 | #define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) | |
1817 | #define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) | |
1818 | #define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) | |
1819 | #define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) | |
1820 | #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) | |
1821 | #define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) | |
1822 | #define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) | |
1823 | #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) | |
1824 | ||
1825 | #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) | |
1826 | #define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) | |
1827 | #define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) | |
1828 | #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) | |
1829 | #define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) | |
1830 | #define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) | |
1831 | #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) | |
1832 | #define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) | |
1833 | #define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) | |
1834 | ||
1835 | #define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) | |
c00b5f85 | 1836 | |
846b0dd2 | 1837 | #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ |
c157d8e2 | 1838 | |
887e2ec9 SR |
1839 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1840 | ||
1841 | /* USB2.0 Device */ | |
6d0f6bcf | 1842 | #define USB2D0_BASE CONFIG_SYS_USB2D0_BASE |
887e2ec9 SR |
1843 | |
1844 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) | |
1845 | ||
dbcc3571 NG |
1846 | #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for |
1847 | Endpoint 0 plus IN Endpoints 1 to 3 */ | |
1848 | #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management | |
1849 | register */ | |
1850 | #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address | |
1851 | register */ | |
1852 | #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
1853 | register for USB2D0_INTRIN */ | |
1854 | #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for | |
1855 | OUT Endpoints 1 to 3 */ | |
1856 | #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
1857 | register for USB2D0_INTRUSB */ | |
1858 | #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for | |
1859 | common USB interrupts */ | |
1860 | #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable | |
1861 | register for IntrOut */ | |
1862 | #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 | |
1863 | test modes */ | |
1864 | #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for | |
1865 | selecting the Endpoint status/control registers */ | |
887e2ec9 | 1866 | #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ |
dbcc3571 NG |
1867 | #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status |
1868 | register for Endpoint 0. (Index register set to select Endpoint 0) */ | |
1869 | #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status | |
1870 | register for IN Endpoint. (Index register set to select Endpoints 13) */ | |
1871 | #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet | |
1872 | size for IN Endpoint. (Index register set to select Endpoints 13) */ | |
1873 | #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status | |
1874 | register for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
1875 | #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet | |
1876 | size for OUT Endpoint. (Index register set to select Endpoints 13) */ | |
1877 | #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received | |
1878 | bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ | |
1879 | #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in | |
1880 | OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ | |
887e2ec9 SR |
1881 | #endif |
1882 | ||
c157d8e2 SR |
1883 | /****************************************************************************** |
1884 | * GPIO macro register defines | |
1885 | ******************************************************************************/ | |
ba58e4c9 | 1886 | #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ |
96e5fc0e FK |
1887 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
1888 | defined(CONFIG_460SX) | |
dbcc3571 | 1889 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700) |
5568e613 | 1890 | |
dbcc3571 NG |
1891 | #define GPIO0_OR (GPIO0_BASE+0x0) |
1892 | #define GPIO0_TCR (GPIO0_BASE+0x4) | |
1893 | #define GPIO0_ODR (GPIO0_BASE+0x18) | |
1894 | #define GPIO0_IR (GPIO0_BASE+0x1C) | |
5568e613 SR |
1895 | #endif /* CONFIG_440GP */ |
1896 | ||
887e2ec9 | 1897 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
43c60992 SR |
1898 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
1899 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
dbcc3571 NG |
1900 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) |
1901 | #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) | |
1902 | ||
1903 | #define GPIO0_OR (GPIO0_BASE+0x0) | |
1904 | #define GPIO0_TCR (GPIO0_BASE+0x4) | |
1905 | #define GPIO0_OSRL (GPIO0_BASE+0x8) | |
1906 | #define GPIO0_OSRH (GPIO0_BASE+0xC) | |
1907 | #define GPIO0_TSRL (GPIO0_BASE+0x10) | |
1908 | #define GPIO0_TSRH (GPIO0_BASE+0x14) | |
1909 | #define GPIO0_ODR (GPIO0_BASE+0x18) | |
1910 | #define GPIO0_IR (GPIO0_BASE+0x1C) | |
1911 | #define GPIO0_RR1 (GPIO0_BASE+0x20) | |
1912 | #define GPIO0_RR2 (GPIO0_BASE+0x24) | |
1913 | #define GPIO0_RR3 (GPIO0_BASE+0x28) | |
1914 | #define GPIO0_ISR1L (GPIO0_BASE+0x30) | |
1915 | #define GPIO0_ISR1H (GPIO0_BASE+0x34) | |
1916 | #define GPIO0_ISR2L (GPIO0_BASE+0x38) | |
1917 | #define GPIO0_ISR2H (GPIO0_BASE+0x3C) | |
1918 | #define GPIO0_ISR3L (GPIO0_BASE+0x40) | |
1919 | #define GPIO0_ISR3H (GPIO0_BASE+0x44) | |
1920 | ||
1921 | #define GPIO1_OR (GPIO1_BASE+0x0) | |
1922 | #define GPIO1_TCR (GPIO1_BASE+0x4) | |
1923 | #define GPIO1_OSRL (GPIO1_BASE+0x8) | |
1924 | #define GPIO1_OSRH (GPIO1_BASE+0xC) | |
1925 | #define GPIO1_TSRL (GPIO1_BASE+0x10) | |
1926 | #define GPIO1_TSRH (GPIO1_BASE+0x14) | |
1927 | #define GPIO1_ODR (GPIO1_BASE+0x18) | |
1928 | #define GPIO1_IR (GPIO1_BASE+0x1C) | |
1929 | #define GPIO1_RR1 (GPIO1_BASE+0x20) | |
1930 | #define GPIO1_RR2 (GPIO1_BASE+0x24) | |
1931 | #define GPIO1_RR3 (GPIO1_BASE+0x28) | |
1932 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) | |
1933 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) | |
1934 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) | |
1935 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) | |
1936 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) | |
1937 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) | |
c157d8e2 SR |
1938 | #endif |
1939 | ||
c00b5f85 WD |
1940 | #ifndef __ASSEMBLY__ |
1941 | ||
ba56f625 | 1942 | #endif /* _ASMLANGUAGE */ |
c00b5f85 | 1943 | |
c00b5f85 | 1944 | #endif /* __PPC440_H__ */ |