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Commit | Line | Data |
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d25ce7d2 | 1 | /* |
a5e8199a | 2 | * Common SPI flash Interface |
d25ce7d2 HS |
3 | * |
4 | * Copyright (C) 2008 Atmel Corporation | |
a5e8199a | 5 | * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. |
d25ce7d2 HS |
6 | * |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
3765b3e7 | 12 | * version 2 as published by the Free Software Foundation. |
d25ce7d2 | 13 | */ |
a5e8199a | 14 | |
d25ce7d2 HS |
15 | #ifndef _SPI_FLASH_H_ |
16 | #define _SPI_FLASH_H_ | |
17 | ||
4c2dbefd | 18 | #include <dm.h> /* Because we dereference struct udevice here */ |
e06ab654 | 19 | #include <linux/types.h> |
d25ce7d2 | 20 | |
88e34e5f NK |
21 | #ifndef CONFIG_SF_DEFAULT_SPEED |
22 | # define CONFIG_SF_DEFAULT_SPEED 1000000 | |
23 | #endif | |
24 | #ifndef CONFIG_SF_DEFAULT_MODE | |
25 | # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
26 | #endif | |
27 | #ifndef CONFIG_SF_DEFAULT_CS | |
28 | # define CONFIG_SF_DEFAULT_CS 0 | |
29 | #endif | |
30 | #ifndef CONFIG_SF_DEFAULT_BUS | |
31 | # define CONFIG_SF_DEFAULT_BUS 0 | |
32 | #endif | |
33 | ||
ff0960f9 | 34 | struct spi_slave; |
33adfb5f | 35 | |
7ab35d92 JT |
36 | /** |
37 | * struct spi_flash - SPI flash structure | |
38 | * | |
39 | * @spi: SPI slave | |
40 | * @name: Name of SPI flash | |
ff0960f9 | 41 | * @dual_flash: Indicates dual flash memories - dual stacked, parallel |
056fbc73 | 42 | * @shift: Flash shift useful in dual parallel |
7ab35d92 JT |
43 | * @size: Total flash size |
44 | * @page_size: Write (page) size | |
45 | * @sector_size: Sector size | |
ff0960f9 | 46 | * @erase_size: Erase size |
7ab35d92 JT |
47 | * @bank_read_cmd: Bank read cmd |
48 | * @bank_write_cmd: Bank write cmd | |
49 | * @bank_curr: Current flash bank | |
50 | * @poll_cmd: Poll cmd - for flash erase/program | |
51 | * @erase_cmd: Erase cmd 4K, 32K, 64K | |
3163aaa6 JT |
52 | * @read_cmd: Read cmd - Array Fast, Extn read and quad read. |
53 | * @write_cmd: Write cmd - page and quad program. | |
ff0960f9 SG |
54 | * @dummy_byte: Dummy cycles for read operation. |
55 | * @memory_map: Address of read-only SPI flash access | |
7ab35d92 JT |
56 | * @read: Flash read ops: Read len bytes at offset into buf |
57 | * Supported cmds: Fast Array Read | |
801cec59 | 58 | * @write: Flash write ops: Write len bytes from buf into offset |
7ab35d92 JT |
59 | * Supported cmds: Page Program |
60 | * @erase: Flash erase ops: Erase len bytes from offset | |
61 | * Supported cmds: Sector erase 4K, 32K, 64K | |
801cec59 | 62 | * return 0 - Success, 1 - Failure |
7ab35d92 | 63 | */ |
d25ce7d2 | 64 | struct spi_flash { |
4c2dbefd | 65 | #ifdef CONFIG_DM_SPI_FLASH |
d25ce7d2 | 66 | struct spi_slave *spi; |
4c2dbefd SG |
67 | struct udevice *dev; |
68 | #else | |
69 | struct spi_slave *spi; | |
70 | #endif | |
7ab35d92 | 71 | const char *name; |
f77f4691 | 72 | u8 dual_flash; |
056fbc73 | 73 | u8 shift; |
d25ce7d2 | 74 | |
7ab35d92 JT |
75 | u32 size; |
76 | u32 page_size; | |
77 | u32 sector_size; | |
78 | u32 erase_size; | |
1dcd6d03 | 79 | #ifdef CONFIG_SPI_FLASH_BAR |
7ab35d92 JT |
80 | u8 bank_read_cmd; |
81 | u8 bank_write_cmd; | |
82 | u8 bank_curr; | |
1dcd6d03 | 83 | #endif |
7ab35d92 JT |
84 | u8 poll_cmd; |
85 | u8 erase_cmd; | |
4e09cc1e | 86 | u8 read_cmd; |
3163aaa6 | 87 | u8 write_cmd; |
ff063ed4 | 88 | u8 dummy_byte; |
615a1561 | 89 | |
7ab35d92 | 90 | void *memory_map; |
4c2dbefd SG |
91 | #ifndef CONFIG_DM_SPI_FLASH |
92 | /* | |
93 | * These are not strictly needed for driver model, but keep them here | |
94 | * whilt the transition is in progress. | |
95 | * | |
96 | * Normally each driver would provide its own operations, but for | |
97 | * SPI flash most chips use the same algorithms. One approach is | |
98 | * to create a 'common' SPI flash device which knows how to talk | |
99 | * to most devices, and then allow other drivers to be used instead | |
100 | * if requird, perhaps with a way of scanning through the list to | |
101 | * find the driver that matches the device. | |
102 | */ | |
7ab35d92 JT |
103 | int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); |
104 | int (*write)(struct spi_flash *flash, u32 offset, size_t len, | |
105 | const void *buf); | |
106 | int (*erase)(struct spi_flash *flash, u32 offset, size_t len); | |
4c2dbefd SG |
107 | #endif |
108 | }; | |
109 | ||
110 | struct dm_spi_flash_ops { | |
111 | int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf); | |
112 | int (*write)(struct udevice *dev, u32 offset, size_t len, | |
113 | const void *buf); | |
114 | int (*erase)(struct udevice *dev, u32 offset, size_t len); | |
d25ce7d2 HS |
115 | }; |
116 | ||
4c2dbefd SG |
117 | /* Access the serial operations for a device */ |
118 | #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) | |
119 | ||
120 | #ifdef CONFIG_DM_SPI_FLASH | |
121 | int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, | |
122 | unsigned int max_hz, unsigned int spi_mode, | |
123 | struct udevice **devp); | |
124 | ||
125 | /* Compatibility function - this is the old U-Boot API */ | |
126 | struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, | |
127 | unsigned int max_hz, unsigned int spi_mode); | |
128 | ||
129 | /* Compatibility function - this is the old U-Boot API */ | |
130 | void spi_flash_free(struct spi_flash *flash); | |
131 | ||
132 | int spi_flash_remove(struct udevice *flash); | |
133 | ||
134 | static inline int spi_flash_read(struct spi_flash *flash, u32 offset, | |
135 | size_t len, void *buf) | |
136 | { | |
137 | return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf); | |
138 | } | |
139 | ||
140 | static inline int spi_flash_write(struct spi_flash *flash, u32 offset, | |
141 | size_t len, const void *buf) | |
142 | { | |
143 | return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf); | |
144 | } | |
145 | ||
146 | static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, | |
147 | size_t len) | |
148 | { | |
149 | return sf_get_ops(flash->dev)->erase(flash->dev, offset, len); | |
150 | } | |
151 | ||
152 | struct sandbox_state; | |
153 | ||
154 | int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs, | |
155 | struct udevice *bus, int of_offset, const char *spec); | |
156 | ||
157 | void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs); | |
158 | ||
159 | #else | |
d25ce7d2 HS |
160 | struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, |
161 | unsigned int max_hz, unsigned int spi_mode); | |
0efc0249 SG |
162 | |
163 | /** | |
164 | * Set up a new SPI flash from an fdt node | |
165 | * | |
166 | * @param blob Device tree blob | |
167 | * @param slave_node Pointer to this SPI slave node in the device tree | |
168 | * @param spi_node Cached pointer to the SPI interface this node belongs | |
169 | * to | |
170 | * @return 0 if ok, -1 on error | |
171 | */ | |
172 | struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node, | |
173 | int spi_node); | |
174 | ||
d25ce7d2 HS |
175 | void spi_flash_free(struct spi_flash *flash); |
176 | ||
177 | static inline int spi_flash_read(struct spi_flash *flash, u32 offset, | |
178 | size_t len, void *buf) | |
179 | { | |
180 | return flash->read(flash, offset, len, buf); | |
181 | } | |
182 | ||
183 | static inline int spi_flash_write(struct spi_flash *flash, u32 offset, | |
184 | size_t len, const void *buf) | |
185 | { | |
186 | return flash->write(flash, offset, len, buf); | |
187 | } | |
188 | ||
189 | static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, | |
190 | size_t len) | |
191 | { | |
192 | return flash->erase(flash, offset, len); | |
193 | } | |
4c2dbefd | 194 | #endif |
d25ce7d2 | 195 | |
32b11273 | 196 | void spi_boot(void) __noreturn; |
1eaa742d | 197 | void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); |
32b11273 | 198 | |
d25ce7d2 | 199 | #endif /* _SPI_FLASH_H_ */ |