]>
Commit | Line | Data |
---|---|---|
6706b115 | 1 | /* |
a857d5f8 | 2 | * Copyright 2013, 2015 Freescale Semiconductor, Inc. |
6706b115 | 3 | * |
a857d5f8 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
6706b115 | 5 | * |
a857d5f8 | 6 | * Driver for the Vitesse VSC9953 L2 Switch |
6706b115 CC |
7 | */ |
8 | ||
9 | #ifndef _VSC9953_H_ | |
10 | #define _VSC9953_H_ | |
11 | ||
12 | #include <config.h> | |
13 | #include <miiphy.h> | |
14 | #include <asm/types.h> | |
6706b115 CC |
15 | |
16 | #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) | |
17 | ||
18 | #define VSC9953_SYS_OFFSET 0x010000 | |
9de05987 | 19 | #define VSC9953_REW_OFFSET 0x030000 |
6706b115 CC |
20 | #define VSC9953_DEV_GMII_OFFSET 0x100000 |
21 | #define VSC9953_QSYS_OFFSET 0x200000 | |
22 | #define VSC9953_ANA_OFFSET 0x280000 | |
23 | #define VSC9953_DEVCPU_GCB 0x070000 | |
24 | #define VSC9953_ES0 0x040000 | |
25 | #define VSC9953_IS1 0x050000 | |
26 | #define VSC9953_IS2 0x060000 | |
27 | ||
28 | #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 | |
29 | #define VSC9953_PHY_REGS_OFFST 0x0000AC | |
30 | ||
3cc8cfff | 31 | /* Macros for vsc9953_chip_regs.soft_rst register */ |
c4390486 | 32 | #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 |
3cc8cfff CC |
33 | |
34 | /* Macros for vsc9953_sys_sys.reset_cfg register */ | |
c4390486 CC |
35 | #define VSC9953_CORE_ENABLE 0x80 |
36 | #define VSC9953_MEM_ENABLE 0x40 | |
37 | #define VSC9953_MEM_INIT 0x20 | |
6706b115 | 38 | |
3cc8cfff | 39 | /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ |
c4390486 | 40 | #define VSC9953_MAC_ENA_CFG 0x00000011 |
3cc8cfff CC |
41 | |
42 | /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ | |
c4390486 | 43 | #define VSC9953_MAC_MODE_CFG 0x00000011 |
3cc8cfff CC |
44 | |
45 | /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ | |
c4390486 | 46 | #define VSC9953_MAC_IFG_CFG 0x00000515 |
3cc8cfff CC |
47 | |
48 | /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ | |
c4390486 | 49 | #define VSC9953_MAC_HDX_CFG 0x00001043 |
3cc8cfff CC |
50 | |
51 | /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ | |
52 | #define VSC9953_MAC_MAX_LEN 0x000005ee | |
53 | ||
54 | /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ | |
c4390486 CC |
55 | #define VSC9953_CLOCK_CFG 0x00000001 |
56 | #define VSC9953_CLOCK_CFG_1000M 0x00000001 | |
3cc8cfff CC |
57 | |
58 | /* Macros for vsc9953_sys_sys.front_port_mode register */ | |
59 | #define VSC9953_FRONT_PORT_MODE 0x00000000 | |
60 | ||
61 | /* Macros for vsc9953_ana_pfc.pfc_cfg register */ | |
c4390486 CC |
62 | #define VSC9953_PFC_FC 0x00000001 |
63 | #define VSC9953_PFC_FC_QSGMII 0x00000000 | |
3cc8cfff CC |
64 | |
65 | /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ | |
c4390486 CC |
66 | #define VSC9953_MAC_FC_CFG 0x04700000 |
67 | #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 | |
3cc8cfff CC |
68 | |
69 | /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ | |
c4390486 | 70 | #define VSC9953_PAUSE_CFG 0x001ffffe |
3cc8cfff CC |
71 | |
72 | /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ | |
c4390486 | 73 | #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff |
6706b115 | 74 | |
86719f0c CC |
75 | /* Macros for vsc9953_sys_sys.stat_cfg register */ |
76 | #define VSC9953_STAT_CLEAR_RX 0x00000400 | |
77 | #define VSC9953_STAT_CLEAR_TX 0x00000800 | |
78 | #define VSC9953_STAT_CLEAR_DR 0x00001000 | |
79 | ||
3cc8cfff | 80 | /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ |
c4390486 CC |
81 | #define VSC9953_VCAP_MV_CFG 0x0000ffff |
82 | #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 | |
3cc8cfff | 83 | |
22449858 CC |
84 | /* Macros for register vsc9953_ana_ana_tables.mac_access register */ |
85 | #define VSC9953_MAC_CMD_IDLE 0x00000000 | |
86 | #define VSC9953_MAC_CMD_LEARN 0x00000001 | |
87 | #define VSC9953_MAC_CMD_FORGET 0x00000002 | |
88 | #define VSC9953_MAC_CMD_AGE 0x00000003 | |
89 | #define VSC9953_MAC_CMD_NEXT 0x00000004 | |
90 | #define VSC9953_MAC_CMD_READ 0x00000006 | |
91 | #define VSC9953_MAC_CMD_WRITE 0x00000007 | |
92 | #define VSC9953_MAC_CMD_MASK 0x00000007 | |
93 | #define VSC9953_MAC_CMD_VALID 0x00000800 | |
94 | #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 | |
95 | #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 | |
96 | #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 | |
97 | #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 | |
98 | #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 | |
99 | #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 | |
100 | #define VSC9953_MAC_VID_MASK 0x1fff0000 | |
101 | #define VSC9953_MAC_MACH_MASK 0x0000ffff | |
102 | ||
9de05987 CC |
103 | /* Macros for vsc9953_ana_port.vlan_cfg register */ |
104 | #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 | |
105 | #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 | |
a2477924 CC |
106 | #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 |
107 | #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 | |
9de05987 CC |
108 | #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff |
109 | ||
110 | /* Macros for vsc9953_rew_port.port_vlan_cfg register */ | |
111 | #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff | |
112 | ||
113 | /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ | |
114 | #define VSC9953_ANA_TBL_VID_MASK 0x00000fff | |
115 | ||
116 | /* Macros for vsc9953_ana_ana_tables.vlan_access register */ | |
117 | #define VSC9953_VLAN_PORT_MASK 0x00001ffc | |
118 | #define VSC9953_VLAN_CMD_MASK 0x00000003 | |
119 | #define VSC9953_VLAN_CMD_IDLE 0x00000000 | |
120 | #define VSC9953_VLAN_CMD_READ 0x00000001 | |
121 | #define VSC9953_VLAN_CMD_WRITE 0x00000002 | |
122 | #define VSC9953_VLAN_CMD_INIT 0x00000003 | |
123 | ||
68c929da CC |
124 | /* Macros for vsc9953_ana_port.port_cfg register */ |
125 | #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 | |
126 | #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 | |
127 | #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 | |
128 | #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 | |
129 | ||
3cc8cfff | 130 | /* Macros for vsc9953_qsys_sys.switch_port_mode register */ |
fe91095b | 131 | #define VSC9953_PORT_ENA 0x00002000 |
3cc8cfff | 132 | |
21d214fc CC |
133 | /* Macros for vsc9953_ana_ana.agen_ctrl register */ |
134 | #define VSC9953_FID_MASK_ALL 0x00fff000 | |
135 | ||
9de05987 CC |
136 | /* Macros for vsc9953_ana_ana.adv_learn register */ |
137 | #define VSC9953_VLAN_CHK 0x00000400 | |
138 | ||
139 | /* Macros for vsc9953_rew_port.port_tag_cfg register */ | |
140 | #define VSC9953_TAG_CFG_MASK 0x00000180 | |
141 | #define VSC9953_TAG_CFG_NONE 0x00000000 | |
142 | #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 | |
143 | #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 | |
144 | #define VSC9953_TAG_CFG_ALL 0x00000180 | |
a2477924 | 145 | #define VSC9953_TAG_VID_PVID 0x00000010 |
9de05987 | 146 | |
22449858 CC |
147 | /* Macros for vsc9953_ana_ana.anag_efil register */ |
148 | #define VSC9953_AGE_PORT_EN 0x00080000 | |
149 | #define VSC9953_AGE_PORT_MASK 0x0007c000 | |
150 | #define VSC9953_AGE_VID_EN 0x00002000 | |
151 | #define VSC9953_AGE_VID_MASK 0x00001fff | |
152 | ||
153 | /* Macros for vsc9953_ana_ana_tables.mach_data register */ | |
154 | #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 | |
155 | ||
6706b115 CC |
156 | #define VSC9953_MAX_PORTS 10 |
157 | #define VSC9953_PORT_CHECK(port) \ | |
158 | (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) | |
159 | #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ | |
160 | ( \ | |
161 | (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ | |
162 | ) ? 0 : 1 \ | |
163 | ) | |
9de05987 CC |
164 | #define VSC9953_MAX_VLAN 4096 |
165 | #define VSC9953_VLAN_CHECK(vid) \ | |
166 | (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) | |
6706b115 CC |
167 | |
168 | #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" | |
169 | ||
170 | #define MIIMIND_OPR_PEND 0x00000004 | |
171 | ||
172 | struct vsc9953_mdio_info { | |
173 | struct vsc9953_mii_mng *regs; | |
174 | char *name; | |
175 | }; | |
176 | ||
3cc8cfff | 177 | /* VSC9953 ANA structure */ |
6706b115 | 178 | |
3cc8cfff | 179 | struct vsc9953_ana_port { |
6706b115 CC |
180 | u32 vlan_cfg; |
181 | u32 drop_cfg; | |
182 | u32 qos_cfg; | |
183 | u32 vcap_cfg; | |
184 | u32 vcap_s1_key_cfg[3]; | |
185 | u32 vcap_s2_cfg; | |
186 | u32 qos_pcp_dei_map_cfg[16]; | |
187 | u32 cpu_fwd_cfg; | |
188 | u32 cpu_fwd_bpdu_cfg; | |
189 | u32 cpu_fwd_garp_cfg; | |
190 | u32 cpu_fwd_ccm_cfg; | |
191 | u32 port_cfg; | |
192 | u32 pol_cfg; | |
193 | u32 reserved[34]; | |
194 | }; | |
195 | ||
196 | struct vsc9953_ana_pol { | |
197 | u32 pol_pir_cfg; | |
198 | u32 pol_cir_cfg; | |
199 | u32 pol_mode_cfg; | |
200 | u32 pol_pir_state; | |
201 | u32 pol_cir_state; | |
202 | u32 reserved1[3]; | |
203 | }; | |
204 | ||
205 | struct vsc9953_ana_ana_tables { | |
206 | u32 entry_lim[11]; | |
207 | u32 an_moved; | |
208 | u32 mach_data; | |
209 | u32 macl_data; | |
210 | u32 mac_access; | |
211 | u32 mact_indx; | |
212 | u32 vlan_access; | |
213 | u32 vlan_tidx; | |
214 | }; | |
215 | ||
216 | struct vsc9953_ana_ana { | |
217 | u32 adv_learn; | |
218 | u32 vlan_mask; | |
440873df | 219 | u32 reserved; |
6706b115 CC |
220 | u32 anag_efil; |
221 | u32 an_events; | |
222 | u32 storm_limit_burst; | |
223 | u32 storm_limit_cfg[4]; | |
224 | u32 isolated_prts; | |
225 | u32 community_ports; | |
226 | u32 auto_age; | |
227 | u32 mac_options; | |
228 | u32 learn_disc; | |
229 | u32 agen_ctrl; | |
230 | u32 mirror_ports; | |
231 | u32 emirror_ports; | |
232 | u32 flooding; | |
233 | u32 flooding_ipmc; | |
234 | u32 sflow_cfg[11]; | |
235 | u32 port_mode[12]; | |
236 | }; | |
237 | ||
238 | struct vsc9953_ana_pgid { | |
239 | u32 port_grp_id[91]; | |
240 | }; | |
241 | ||
3cc8cfff | 242 | struct vsc9953_ana_pfc { |
6706b115 CC |
243 | u32 pfc_cfg; |
244 | u32 reserved1[15]; | |
245 | }; | |
246 | ||
247 | struct vsc9953_ana_pol_misc { | |
248 | u32 pol_flowc[10]; | |
249 | u32 reserved1[17]; | |
250 | u32 pol_hyst; | |
251 | }; | |
252 | ||
3cc8cfff | 253 | struct vsc9953_ana_common { |
6706b115 CC |
254 | u32 aggr_cfg; |
255 | u32 cpuq_cfg; | |
256 | u32 cpuq_8021_cfg; | |
257 | u32 dscp_cfg; | |
258 | u32 dscp_rewr_cfg; | |
259 | u32 vcap_rng_type_cfg; | |
260 | u32 vcap_rng_val_cfg; | |
261 | u32 discard_cfg; | |
262 | u32 fid_cfg; | |
263 | }; | |
264 | ||
265 | struct vsc9953_analyzer { | |
266 | struct vsc9953_ana_port port[11]; | |
267 | u32 reserved1[9536]; | |
268 | struct vsc9953_ana_pol pol[164]; | |
269 | struct vsc9953_ana_ana_tables ana_tables; | |
270 | u32 reserved2[14]; | |
271 | struct vsc9953_ana_ana ana; | |
272 | u32 reserved3[22]; | |
273 | struct vsc9953_ana_pgid port_id_tbl; | |
274 | u32 reserved4[549]; | |
275 | struct vsc9953_ana_pfc pfc[10]; | |
276 | struct vsc9953_ana_pol_misc pol_misc; | |
277 | u32 reserved5[196]; | |
278 | struct vsc9953_ana_common common; | |
279 | }; | |
3cc8cfff | 280 | /* END VSC9953 ANA structure t*/ |
6706b115 | 281 | |
3cc8cfff | 282 | /* VSC9953 DEV_GMII structure */ |
6706b115 | 283 | |
3cc8cfff | 284 | struct vsc9953_dev_gmii_port_mode { |
6706b115 CC |
285 | u32 clock_cfg; |
286 | u32 port_misc; | |
287 | u32 reserved1; | |
288 | u32 eee_cfg; | |
289 | }; | |
290 | ||
3cc8cfff | 291 | struct vsc9953_dev_gmii_mac_cfg_status { |
6706b115 CC |
292 | u32 mac_ena_cfg; |
293 | u32 mac_mode_cfg; | |
294 | u32 mac_maxlen_cfg; | |
295 | u32 mac_tags_cfg; | |
296 | u32 mac_adv_chk_cfg; | |
297 | u32 mac_ifg_cfg; | |
298 | u32 mac_hdx_cfg; | |
299 | u32 mac_fc_mac_low_cfg; | |
300 | u32 mac_fc_mac_high_cfg; | |
301 | u32 mac_sticky; | |
302 | }; | |
303 | ||
304 | struct vsc9953_dev_gmii { | |
305 | struct vsc9953_dev_gmii_port_mode port_mode; | |
306 | struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; | |
307 | }; | |
308 | ||
3cc8cfff | 309 | /* END VSC9953 DEV_GMII structure */ |
6706b115 | 310 | |
3cc8cfff | 311 | /* VSC9953 QSYS structure */ |
6706b115 | 312 | |
3cc8cfff | 313 | struct vsc9953_qsys_hsch { |
6706b115 CC |
314 | u32 cir_cfg; |
315 | u32 reserved1; | |
316 | u32 se_cfg; | |
317 | u32 se_dwrr_cfg[8]; | |
318 | u32 cir_state; | |
319 | u32 reserved2[20]; | |
320 | }; | |
321 | ||
3cc8cfff | 322 | struct vsc9953_qsys_sys { |
6706b115 CC |
323 | u32 port_mode[12]; |
324 | u32 switch_port_mode[11]; | |
325 | u32 stat_cnt_cfg; | |
326 | u32 eee_cfg[10]; | |
327 | u32 eee_thrs; | |
328 | u32 igr_no_sharing; | |
329 | u32 egr_no_sharing; | |
330 | u32 sw_status[11]; | |
331 | u32 ext_cpu_cfg; | |
332 | u32 cpu_group_map; | |
333 | u32 reserved1[23]; | |
334 | }; | |
335 | ||
3cc8cfff | 336 | struct vsc9953_qsys_qos_cfg { |
6706b115 CC |
337 | u32 red_profile[16]; |
338 | u32 res_qos_mode; | |
339 | }; | |
340 | ||
3cc8cfff | 341 | struct vsc9953_qsys_drop_cfg { |
6706b115 CC |
342 | u32 egr_drop_mode; |
343 | }; | |
344 | ||
3cc8cfff | 345 | struct vsc9953_qsys_mmgt { |
6706b115 CC |
346 | u32 eq_cntrl; |
347 | u32 reserved1; | |
348 | }; | |
349 | ||
3cc8cfff | 350 | struct vsc9953_qsys_hsch_misc { |
6706b115 CC |
351 | u32 hsch_misc_cfg; |
352 | u32 reserved1[546]; | |
353 | }; | |
354 | ||
3cc8cfff | 355 | struct vsc9953_qsys_res_ctrl { |
6706b115 CC |
356 | u32 res_cfg; |
357 | u32 res_stat; | |
358 | ||
359 | }; | |
360 | ||
3cc8cfff | 361 | struct vsc9953_qsys_reg { |
6706b115 CC |
362 | struct vsc9953_qsys_hsch hsch[108]; |
363 | struct vsc9953_qsys_sys sys; | |
364 | struct vsc9953_qsys_qos_cfg qos_cfg; | |
365 | struct vsc9953_qsys_drop_cfg drop_cfg; | |
366 | struct vsc9953_qsys_mmgt mmgt; | |
367 | struct vsc9953_qsys_hsch_misc hsch_misc; | |
368 | struct vsc9953_qsys_res_ctrl res_ctrl[1024]; | |
369 | }; | |
370 | ||
3cc8cfff | 371 | /* END VSC9953 QSYS structure */ |
6706b115 | 372 | |
3cc8cfff | 373 | /* VSC9953 SYS structure */ |
6706b115 | 374 | |
86719f0c CC |
375 | struct vsc9953_rx_cntrs { |
376 | u32 c_rx_oct; | |
377 | u32 c_rx_uc; | |
378 | u32 c_rx_mc; | |
379 | u32 c_rx_bc; | |
380 | u32 c_rx_short; | |
381 | u32 c_rx_frag; | |
382 | u32 c_rx_jabber; | |
383 | u32 c_rx_crc; | |
384 | u32 c_rx_symbol_err; | |
385 | u32 c_rx_sz_64; | |
386 | u32 c_rx_sz_65_127; | |
387 | u32 c_rx_sz_128_255; | |
388 | u32 c_rx_sz_256_511; | |
389 | u32 c_rx_sz_512_1023; | |
390 | u32 c_rx_sz_1024_1526; | |
391 | u32 c_rx_sz_jumbo; | |
392 | u32 c_rx_pause; | |
393 | u32 c_rx_control; | |
394 | u32 c_rx_long; | |
395 | u32 c_rx_cat_drop; | |
396 | u32 c_rx_red_prio_0; | |
397 | u32 c_rx_red_prio_1; | |
398 | u32 c_rx_red_prio_2; | |
399 | u32 c_rx_red_prio_3; | |
400 | u32 c_rx_red_prio_4; | |
401 | u32 c_rx_red_prio_5; | |
402 | u32 c_rx_red_prio_6; | |
403 | u32 c_rx_red_prio_7; | |
404 | u32 c_rx_yellow_prio_0; | |
405 | u32 c_rx_yellow_prio_1; | |
406 | u32 c_rx_yellow_prio_2; | |
407 | u32 c_rx_yellow_prio_3; | |
408 | u32 c_rx_yellow_prio_4; | |
409 | u32 c_rx_yellow_prio_5; | |
410 | u32 c_rx_yellow_prio_6; | |
411 | u32 c_rx_yellow_prio_7; | |
412 | u32 c_rx_green_prio_0; | |
413 | u32 c_rx_green_prio_1; | |
414 | u32 c_rx_green_prio_2; | |
415 | u32 c_rx_green_prio_3; | |
416 | u32 c_rx_green_prio_4; | |
417 | u32 c_rx_green_prio_5; | |
418 | u32 c_rx_green_prio_6; | |
419 | u32 c_rx_green_prio_7; | |
420 | u32 reserved[20]; | |
421 | }; | |
422 | ||
423 | struct vsc9953_tx_cntrs { | |
424 | u32 c_tx_oct; | |
425 | u32 c_tx_uc; | |
426 | u32 c_tx_mc; | |
427 | u32 c_tx_bc; | |
428 | u32 c_tx_col; | |
429 | u32 c_tx_drop; | |
430 | u32 c_tx_pause; | |
431 | u32 c_tx_sz_64; | |
432 | u32 c_tx_sz_65_127; | |
433 | u32 c_tx_sz_128_255; | |
434 | u32 c_tx_sz_256_511; | |
435 | u32 c_tx_sz_512_1023; | |
436 | u32 c_tx_sz_1024_1526; | |
437 | u32 c_tx_sz_jumbo; | |
438 | u32 c_tx_yellow_prio_0; | |
439 | u32 c_tx_yellow_prio_1; | |
440 | u32 c_tx_yellow_prio_2; | |
441 | u32 c_tx_yellow_prio_3; | |
442 | u32 c_tx_yellow_prio_4; | |
443 | u32 c_tx_yellow_prio_5; | |
444 | u32 c_tx_yellow_prio_6; | |
445 | u32 c_tx_yellow_prio_7; | |
446 | u32 c_tx_green_prio_0; | |
447 | u32 c_tx_green_prio_1; | |
448 | u32 c_tx_green_prio_2; | |
449 | u32 c_tx_green_prio_3; | |
450 | u32 c_tx_green_prio_4; | |
451 | u32 c_tx_green_prio_5; | |
452 | u32 c_tx_green_prio_6; | |
453 | u32 c_tx_green_prio_7; | |
454 | u32 c_tx_aged; | |
455 | u32 reserved[33]; | |
456 | }; | |
457 | ||
458 | struct vsc9953_drop_cntrs { | |
459 | u32 c_dr_local; | |
460 | u32 c_dr_tail; | |
461 | u32 c_dr_yellow_prio_0; | |
462 | u32 c_dr_yellow_prio_1; | |
463 | u32 c_dr_yellow_prio_2; | |
464 | u32 c_dr_yellow_prio_3; | |
465 | u32 c_dr_yellow_prio_4; | |
466 | u32 c_dr_yellow_prio_5; | |
467 | u32 c_dr_yellow_prio_6; | |
468 | u32 c_dr_yellow_prio_7; | |
469 | u32 c_dr_green_prio_0; | |
470 | u32 c_dr_green_prio_1; | |
471 | u32 c_dr_green_prio_2; | |
472 | u32 c_dr_green_prio_3; | |
473 | u32 c_dr_green_prio_4; | |
474 | u32 c_dr_green_prio_5; | |
475 | u32 c_dr_green_prio_6; | |
476 | u32 c_dr_green_prio_7; | |
477 | u32 reserved[46]; | |
478 | }; | |
479 | ||
3cc8cfff | 480 | struct vsc9953_sys_stat { |
86719f0c CC |
481 | struct vsc9953_rx_cntrs rx_cntrs; |
482 | struct vsc9953_tx_cntrs tx_cntrs; | |
483 | struct vsc9953_drop_cntrs drop_cntrs; | |
6706b115 CC |
484 | u32 reserved1[6]; |
485 | }; | |
486 | ||
3cc8cfff | 487 | struct vsc9953_sys_sys { |
6706b115 CC |
488 | u32 reset_cfg; |
489 | u32 reserved1; | |
490 | u32 vlan_etype_cfg; | |
491 | u32 port_mode[12]; | |
492 | u32 front_port_mode[10]; | |
493 | u32 frame_aging; | |
494 | u32 stat_cfg; | |
495 | u32 reserved2[50]; | |
496 | }; | |
497 | ||
3cc8cfff | 498 | struct vsc9953_sys_pause_cfg { |
6706b115 CC |
499 | u32 pause_cfg[11]; |
500 | u32 pause_tot_cfg; | |
501 | u32 tail_drop_level[11]; | |
502 | u32 tot_tail_drop_lvl; | |
503 | u32 mac_fc_cfg[10]; | |
504 | }; | |
505 | ||
3cc8cfff | 506 | struct vsc9953_sys_mmgt { |
6706b115 CC |
507 | u16 free_cnt; |
508 | }; | |
509 | ||
3cc8cfff | 510 | struct vsc9953_system_reg { |
6706b115 CC |
511 | struct vsc9953_sys_stat stat; |
512 | struct vsc9953_sys_sys sys; | |
513 | struct vsc9953_sys_pause_cfg pause_cfg; | |
514 | struct vsc9953_sys_mmgt mmgt; | |
515 | }; | |
516 | ||
3cc8cfff | 517 | /* END VSC9953 SYS structure */ |
6706b115 | 518 | |
9de05987 CC |
519 | /* VSC9953 REW structure */ |
520 | ||
521 | struct vsc9953_rew_port { | |
522 | u32 port_vlan_cfg; | |
523 | u32 port_tag_cfg; | |
524 | u32 port_port_cfg; | |
525 | u32 port_dscp_cfg; | |
526 | u32 port_pcp_dei_qos_map_cfg[16]; | |
527 | u32 reserved[12]; | |
528 | }; | |
529 | ||
530 | struct vsc9953_rew_common { | |
531 | u32 reserve[4]; | |
532 | u32 dscp_remap_dp1_cfg[64]; | |
533 | u32 dscp_remap_cfg[64]; | |
534 | }; | |
535 | ||
536 | struct vsc9953_rew_reg { | |
537 | struct vsc9953_rew_port port[12]; | |
538 | struct vsc9953_rew_common common; | |
539 | }; | |
540 | ||
541 | /* END VSC9953 REW structure */ | |
6706b115 | 542 | |
3cc8cfff | 543 | /* VSC9953 DEVCPU_GCB structure */ |
6706b115 | 544 | |
3cc8cfff | 545 | struct vsc9953_chip_regs { |
6706b115 CC |
546 | u32 chipd_id; |
547 | u32 gpr; | |
548 | u32 soft_rst; | |
549 | }; | |
550 | ||
3cc8cfff | 551 | struct vsc9953_gpio { |
6706b115 CC |
552 | u32 gpio_out_set[10]; |
553 | u32 gpio_out_clr[10]; | |
554 | u32 gpio_out[10]; | |
555 | u32 gpio_in[10]; | |
556 | }; | |
557 | ||
558 | struct vsc9953_mii_mng { | |
559 | u32 miimstatus; | |
560 | u32 reserved1; | |
561 | u32 miimcmd; | |
562 | u32 miimdata; | |
563 | u32 miimcfg; | |
564 | u32 miimscan_0; | |
565 | u32 miimscan_1; | |
566 | u32 miiscan_lst_rslts; | |
567 | u32 miiscan_lst_rslts_valid; | |
568 | }; | |
569 | ||
3cc8cfff | 570 | struct vsc9953_mii_read_scan { |
6706b115 CC |
571 | u32 mii_scan_results_sticky[2]; |
572 | }; | |
573 | ||
3cc8cfff | 574 | struct vsc9953_devcpu_gcb { |
6706b115 CC |
575 | struct vsc9953_chip_regs chip_regs; |
576 | struct vsc9953_gpio gpio; | |
577 | struct vsc9953_mii_mng mii_mng[2]; | |
578 | struct vsc9953_mii_read_scan mii_read_scan; | |
579 | }; | |
580 | ||
3cc8cfff | 581 | /* END VSC9953 DEVCPU_GCB structure */ |
6706b115 | 582 | |
3cc8cfff | 583 | /* VSC9953 IS* structure */ |
6706b115 | 584 | |
3cc8cfff | 585 | struct vsc9953_vcap_core_cfg { |
6706b115 CC |
586 | u32 vcap_update_ctrl; |
587 | u32 vcap_mv_cfg; | |
588 | }; | |
589 | ||
3cc8cfff CC |
590 | struct vsc9953_vcap { |
591 | struct vsc9953_vcap_core_cfg vcap_core_cfg; | |
6706b115 CC |
592 | }; |
593 | ||
3cc8cfff | 594 | /* END VSC9953 IS* structure */ |
6706b115 CC |
595 | |
596 | #define VSC9953_PORT_INFO_INITIALIZER(idx) \ | |
597 | { \ | |
598 | .enabled = 0, \ | |
599 | .phyaddr = 0, \ | |
600 | .index = idx, \ | |
601 | .phy_regs = NULL, \ | |
602 | .enet_if = PHY_INTERFACE_MODE_NONE, \ | |
603 | .bus = NULL, \ | |
604 | .phydev = NULL, \ | |
605 | } | |
606 | ||
607 | /* Structure to describe a VSC9953 port */ | |
608 | struct vsc9953_port_info { | |
609 | u8 enabled; | |
610 | u8 phyaddr; | |
611 | int index; | |
612 | void *phy_regs; | |
613 | phy_interface_t enet_if; | |
614 | struct mii_dev *bus; | |
615 | struct phy_device *phydev; | |
616 | }; | |
617 | ||
618 | /* Structure to describe a VSC9953 switch */ | |
619 | struct vsc9953_info { | |
3cc8cfff | 620 | struct vsc9953_port_info port[VSC9953_MAX_PORTS]; |
6706b115 CC |
621 | }; |
622 | ||
623 | void vsc9953_init(bd_t *bis); | |
624 | ||
3cc8cfff CC |
625 | void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); |
626 | void vsc9953_port_info_set_phy_address(int port_no, int address); | |
627 | void vsc9953_port_enable(int port_no); | |
628 | void vsc9953_port_disable(int port_no); | |
629 | void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); | |
6706b115 CC |
630 | |
631 | #endif /* _VSC9953_H_ */ |