[people/ms/u-boot.git] / include / vsc9953.h

/*
 *  vsc9953.h
 *
 *  Driver for the Vitesse VSC9953 L2 Switch
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * Copyright 2013  Freescale Semiconductor, Inc.
 *
 */

#ifndef _VSC9953_H_
#define _VSC9953_H_

#include <config.h>
#include <miiphy.h>
#include <asm/types.h>

#define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)

#define VSC9953_SYS_OFFSET		0x010000
#define VSC9953_REW_OFFSET		0x030000
#define VSC9953_DEV_GMII_OFFSET		0x100000
#define VSC9953_QSYS_OFFSET		0x200000
#define VSC9953_ANA_OFFSET		0x280000
#define VSC9953_DEVCPU_GCB		0x070000
#define VSC9953_ES0			0x040000
#define VSC9953_IS1			0x050000
#define VSC9953_IS2			0x060000

#define T1040_SWITCH_GMII_DEV_OFFSET	0x010000
#define VSC9953_PHY_REGS_OFFST		0x0000AC

/* Macros for vsc9953_chip_regs.soft_rst register */
#define VSC9953_SOFT_SWC_RST_ENA	0x00000001

/* Macros for vsc9953_sys_sys.reset_cfg register */
#define VSC9953_CORE_ENABLE		0x80
#define VSC9953_MEM_ENABLE		0x40
#define VSC9953_MEM_INIT		0x20

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
#define VSC9953_MAC_ENA_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
#define VSC9953_MAC_MODE_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
#define VSC9953_MAC_IFG_CFG		0x00000515

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
#define VSC9953_MAC_HDX_CFG		0x00001043

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
#define VSC9953_MAC_MAX_LEN		0x000005ee

/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
#define VSC9953_CLOCK_CFG		0x00000001
#define VSC9953_CLOCK_CFG_1000M		0x00000001

/* Macros for vsc9953_sys_sys.front_port_mode register */
#define VSC9953_FRONT_PORT_MODE	0x00000000

/* Macros for vsc9953_ana_pfc.pfc_cfg register */
#define VSC9953_PFC_FC			0x00000001
#define VSC9953_PFC_FC_QSGMII		0x00000000

/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
#define VSC9953_MAC_FC_CFG		0x04700000
#define VSC9953_MAC_FC_CFG_QSGMII	0x00700000

/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
#define VSC9953_PAUSE_CFG		0x001ffffe

/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
#define VSC9953_TOT_TAIL_DROP_LVL	0x000003ff

/* Macros for vsc9953_sys_sys.stat_cfg register */
#define VSC9953_STAT_CLEAR_RX		0x00000400
#define VSC9953_STAT_CLEAR_TX		0x00000800
#define VSC9953_STAT_CLEAR_DR		0x00001000

/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
#define VSC9953_VCAP_MV_CFG		0x0000ffff
#define VSC9953_VCAP_UPDATE_CTRL	0x01000004

/* Macros for vsc9953_ana_port.vlan_cfg register */
#define VSC9953_VLAN_CFG_AWARE_ENA	0x00100000
#define VSC9953_VLAN_CFG_POP_CNT_MASK	0x000c0000
#define VSC9953_VLAN_CFG_VID_MASK	0x00000fff

/* Macros for vsc9953_rew_port.port_vlan_cfg register */
#define VSC9953_PORT_VLAN_CFG_VID_MASK	0x00000fff

/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
#define VSC9953_ANA_TBL_VID_MASK	0x00000fff

/* Macros for vsc9953_ana_ana_tables.vlan_access register */
#define VSC9953_VLAN_PORT_MASK		0x00001ffc
#define VSC9953_VLAN_CMD_MASK		0x00000003
#define VSC9953_VLAN_CMD_IDLE		0x00000000
#define VSC9953_VLAN_CMD_READ		0x00000001
#define VSC9953_VLAN_CMD_WRITE		0x00000002
#define VSC9953_VLAN_CMD_INIT		0x00000003

/* Macros for vsc9953_ana_port.port_cfg register */
#define VSC9953_PORT_CFG_LEARN_ENA	0x00000080
#define VSC9953_PORT_CFG_LEARN_AUTO	0x00000100
#define VSC9953_PORT_CFG_LEARN_CPU	0x00000200
#define VSC9953_PORT_CFG_LEARN_DROP	0x00000400

/* Macros for vsc9953_qsys_sys.switch_port_mode register */
#define VSC9953_PORT_ENA		0x00002000

/* Macros for vsc9953_ana_ana.adv_learn register */
#define VSC9953_VLAN_CHK		0x00000400

/* Macros for vsc9953_rew_port.port_tag_cfg register */
#define VSC9953_TAG_CFG_MASK		0x00000180
#define VSC9953_TAG_CFG_NONE		0x00000000
#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO	0x00000080
#define VSC9953_TAG_CFG_ALL_BUT_ZERO		0x00000100
#define VSC9953_TAG_CFG_ALL		0x00000180

#define VSC9953_MAX_PORTS		10
#define VSC9953_PORT_CHECK(port)	\
	(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	( \
		(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
	) ? 0 : 1 \
)
#define VSC9953_MAX_VLAN		4096
#define VSC9953_VLAN_CHECK(vid)	\
	(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)

#define DEFAULT_VSC9953_MDIO_NAME	"VSC9953_MDIO0"

#define MIIMIND_OPR_PEND		0x00000004

struct vsc9953_mdio_info {
	struct vsc9953_mii_mng	*regs;
	char	*name;
};

/* VSC9953 ANA structure */

struct vsc9953_ana_port {
	u32	vlan_cfg;
	u32	drop_cfg;
	u32	qos_cfg;
	u32	vcap_cfg;
	u32	vcap_s1_key_cfg[3];
	u32	vcap_s2_cfg;
	u32	qos_pcp_dei_map_cfg[16];
	u32	cpu_fwd_cfg;
	u32	cpu_fwd_bpdu_cfg;
	u32	cpu_fwd_garp_cfg;
	u32	cpu_fwd_ccm_cfg;
	u32	port_cfg;
	u32	pol_cfg;
	u32	reserved[34];
};

struct vsc9953_ana_pol {
	u32	pol_pir_cfg;
	u32	pol_cir_cfg;
	u32	pol_mode_cfg;
	u32	pol_pir_state;
	u32	pol_cir_state;
	u32	reserved1[3];
};

struct vsc9953_ana_ana_tables {
	u32	entry_lim[11];
	u32	an_moved;
	u32	mach_data;
	u32	macl_data;
	u32	mac_access;
	u32	mact_indx;
	u32	vlan_access;
	u32	vlan_tidx;
};

struct vsc9953_ana_ana {
	u32	adv_learn;
	u32	vlan_mask;
	u32	reserved;
	u32	anag_efil;
	u32	an_events;
	u32	storm_limit_burst;
	u32	storm_limit_cfg[4];
	u32	isolated_prts;
	u32	community_ports;
	u32	auto_age;
	u32	mac_options;
	u32	learn_disc;
	u32	agen_ctrl;
	u32	mirror_ports;
	u32	emirror_ports;
	u32	flooding;
	u32	flooding_ipmc;
	u32	sflow_cfg[11];
	u32	port_mode[12];
};

struct vsc9953_ana_pgid {
	u32	port_grp_id[91];
};

struct vsc9953_ana_pfc {
	u32	pfc_cfg;
	u32	reserved1[15];
};

struct vsc9953_ana_pol_misc {
	u32	pol_flowc[10];
	u32	reserved1[17];
	u32	pol_hyst;
};

struct vsc9953_ana_common {
	u32	aggr_cfg;
	u32	cpuq_cfg;
	u32	cpuq_8021_cfg;
	u32	dscp_cfg;
	u32	dscp_rewr_cfg;
	u32	vcap_rng_type_cfg;
	u32	vcap_rng_val_cfg;
	u32	discard_cfg;
	u32	fid_cfg;
};

struct vsc9953_analyzer {
	struct vsc9953_ana_port	port[11];
	u32	reserved1[9536];
	struct vsc9953_ana_pol	pol[164];
	struct vsc9953_ana_ana_tables	ana_tables;
	u32	reserved2[14];
	struct vsc9953_ana_ana	ana;
	u32	reserved3[22];
	struct vsc9953_ana_pgid	port_id_tbl;
	u32	reserved4[549];
	struct vsc9953_ana_pfc	pfc[10];
	struct vsc9953_ana_pol_misc	pol_misc;
	u32	reserved5[196];
	struct vsc9953_ana_common	common;
};
/* END VSC9953 ANA structure t*/

/* VSC9953 DEV_GMII structure */

struct vsc9953_dev_gmii_port_mode {
	u32	clock_cfg;
	u32	port_misc;
	u32	reserved1;
	u32	eee_cfg;
};

struct vsc9953_dev_gmii_mac_cfg_status {
	u32	mac_ena_cfg;
	u32	mac_mode_cfg;
	u32	mac_maxlen_cfg;
	u32	mac_tags_cfg;
	u32	mac_adv_chk_cfg;
	u32	mac_ifg_cfg;
	u32	mac_hdx_cfg;
	u32	mac_fc_mac_low_cfg;
	u32	mac_fc_mac_high_cfg;
	u32	mac_sticky;
};

struct vsc9953_dev_gmii {
	struct vsc9953_dev_gmii_port_mode	port_mode;
	struct vsc9953_dev_gmii_mac_cfg_status	mac_cfg_status;
};

/* END VSC9953 DEV_GMII structure */

/* VSC9953 QSYS structure */

struct vsc9953_qsys_hsch {
	u32	cir_cfg;
	u32	reserved1;
	u32	se_cfg;
	u32	se_dwrr_cfg[8];
	u32	cir_state;
	u32	reserved2[20];
};

struct vsc9953_qsys_sys {
	u32	port_mode[12];
	u32	switch_port_mode[11];
	u32	stat_cnt_cfg;
	u32	eee_cfg[10];
	u32	eee_thrs;
	u32	igr_no_sharing;
	u32	egr_no_sharing;
	u32	sw_status[11];
	u32	ext_cpu_cfg;
	u32	cpu_group_map;
	u32	reserved1[23];
};

struct vsc9953_qsys_qos_cfg {
	u32	red_profile[16];
	u32	res_qos_mode;
};

struct vsc9953_qsys_drop_cfg {
	u32	egr_drop_mode;
};

struct vsc9953_qsys_mmgt {
	u32	eq_cntrl;
	u32	reserved1;
};

struct vsc9953_qsys_hsch_misc {
	u32	hsch_misc_cfg;
	u32	reserved1[546];
};

struct vsc9953_qsys_res_ctrl {
	u32	res_cfg;
	u32	res_stat;

};

struct vsc9953_qsys_reg {
	struct vsc9953_qsys_hsch	hsch[108];
	struct vsc9953_qsys_sys	sys;
	struct vsc9953_qsys_qos_cfg	qos_cfg;
	struct vsc9953_qsys_drop_cfg	drop_cfg;
	struct vsc9953_qsys_mmgt	mmgt;
	struct vsc9953_qsys_hsch_misc	hsch_misc;
	struct vsc9953_qsys_res_ctrl	res_ctrl[1024];
};

/* END VSC9953 QSYS structure */

/* VSC9953 SYS structure */

struct vsc9953_rx_cntrs {
	u32	c_rx_oct;
	u32	c_rx_uc;
	u32	c_rx_mc;
	u32	c_rx_bc;
	u32	c_rx_short;
	u32	c_rx_frag;
	u32	c_rx_jabber;
	u32	c_rx_crc;
	u32	c_rx_symbol_err;
	u32	c_rx_sz_64;
	u32	c_rx_sz_65_127;
	u32	c_rx_sz_128_255;
	u32	c_rx_sz_256_511;
	u32	c_rx_sz_512_1023;
	u32	c_rx_sz_1024_1526;
	u32	c_rx_sz_jumbo;
	u32	c_rx_pause;
	u32	c_rx_control;
	u32	c_rx_long;
	u32	c_rx_cat_drop;
	u32	c_rx_red_prio_0;
	u32	c_rx_red_prio_1;
	u32	c_rx_red_prio_2;
	u32	c_rx_red_prio_3;
	u32	c_rx_red_prio_4;
	u32	c_rx_red_prio_5;
	u32	c_rx_red_prio_6;
	u32	c_rx_red_prio_7;
	u32	c_rx_yellow_prio_0;
	u32	c_rx_yellow_prio_1;
	u32	c_rx_yellow_prio_2;
	u32	c_rx_yellow_prio_3;
	u32	c_rx_yellow_prio_4;
	u32	c_rx_yellow_prio_5;
	u32	c_rx_yellow_prio_6;
	u32	c_rx_yellow_prio_7;
	u32	c_rx_green_prio_0;
	u32	c_rx_green_prio_1;
	u32	c_rx_green_prio_2;
	u32	c_rx_green_prio_3;
	u32	c_rx_green_prio_4;
	u32	c_rx_green_prio_5;
	u32	c_rx_green_prio_6;
	u32	c_rx_green_prio_7;
	u32	reserved[20];
};

struct vsc9953_tx_cntrs {
	u32	c_tx_oct;
	u32	c_tx_uc;
	u32	c_tx_mc;
	u32	c_tx_bc;
	u32	c_tx_col;
	u32	c_tx_drop;
	u32	c_tx_pause;
	u32	c_tx_sz_64;
	u32	c_tx_sz_65_127;
	u32	c_tx_sz_128_255;
	u32	c_tx_sz_256_511;
	u32	c_tx_sz_512_1023;
	u32	c_tx_sz_1024_1526;
	u32	c_tx_sz_jumbo;
	u32	c_tx_yellow_prio_0;
	u32	c_tx_yellow_prio_1;
	u32	c_tx_yellow_prio_2;
	u32	c_tx_yellow_prio_3;
	u32	c_tx_yellow_prio_4;
	u32	c_tx_yellow_prio_5;
	u32	c_tx_yellow_prio_6;
	u32	c_tx_yellow_prio_7;
	u32	c_tx_green_prio_0;
	u32	c_tx_green_prio_1;
	u32	c_tx_green_prio_2;
	u32	c_tx_green_prio_3;
	u32	c_tx_green_prio_4;
	u32	c_tx_green_prio_5;
	u32	c_tx_green_prio_6;
	u32	c_tx_green_prio_7;
	u32	c_tx_aged;
	u32	reserved[33];
};

struct vsc9953_drop_cntrs {
	u32	c_dr_local;
	u32	c_dr_tail;
	u32	c_dr_yellow_prio_0;
	u32	c_dr_yellow_prio_1;
	u32	c_dr_yellow_prio_2;
	u32	c_dr_yellow_prio_3;
	u32	c_dr_yellow_prio_4;
	u32	c_dr_yellow_prio_5;
	u32	c_dr_yellow_prio_6;
	u32	c_dr_yellow_prio_7;
	u32	c_dr_green_prio_0;
	u32	c_dr_green_prio_1;
	u32	c_dr_green_prio_2;
	u32	c_dr_green_prio_3;
	u32	c_dr_green_prio_4;
	u32	c_dr_green_prio_5;
	u32	c_dr_green_prio_6;
	u32	c_dr_green_prio_7;
	u32	reserved[46];
};

struct vsc9953_sys_stat {
	struct vsc9953_rx_cntrs	rx_cntrs;
	struct vsc9953_tx_cntrs	tx_cntrs;
	struct vsc9953_drop_cntrs	drop_cntrs;
	u32	reserved1[6];
};

struct vsc9953_sys_sys {
	u32	reset_cfg;
	u32	reserved1;
	u32	vlan_etype_cfg;
	u32	port_mode[12];
	u32	front_port_mode[10];
	u32	frame_aging;
	u32	stat_cfg;
	u32	reserved2[50];
};

struct vsc9953_sys_pause_cfg {
	u32	pause_cfg[11];
	u32	pause_tot_cfg;
	u32	tail_drop_level[11];
	u32	tot_tail_drop_lvl;
	u32	mac_fc_cfg[10];
};

struct vsc9953_sys_mmgt {
	u16	free_cnt;
};

struct vsc9953_system_reg {
	struct vsc9953_sys_stat	stat;
	struct vsc9953_sys_sys	sys;
	struct vsc9953_sys_pause_cfg	pause_cfg;
	struct vsc9953_sys_mmgt	mmgt;
};

/* END VSC9953 SYS structure */

/* VSC9953 REW structure */

struct	vsc9953_rew_port {
	u32	port_vlan_cfg;
	u32	port_tag_cfg;
	u32	port_port_cfg;
	u32	port_dscp_cfg;
	u32	port_pcp_dei_qos_map_cfg[16];
	u32	reserved[12];
};

struct	vsc9953_rew_common {
	u32	reserve[4];
	u32	dscp_remap_dp1_cfg[64];
	u32	dscp_remap_cfg[64];
};

struct	vsc9953_rew_reg {
	struct vsc9953_rew_port	port[12];
	struct vsc9953_rew_common	common;
};

/* END VSC9953 REW structure */

/* VSC9953 DEVCPU_GCB structure */

struct vsc9953_chip_regs {
	u32	chipd_id;
	u32	gpr;
	u32	soft_rst;
};

struct vsc9953_gpio {
	u32	gpio_out_set[10];
	u32	gpio_out_clr[10];
	u32	gpio_out[10];
	u32	gpio_in[10];
};

struct vsc9953_mii_mng {
	u32	miimstatus;
	u32	reserved1;
	u32	miimcmd;
	u32	miimdata;
	u32	miimcfg;
	u32	miimscan_0;
	u32	miimscan_1;
	u32	miiscan_lst_rslts;
	u32	miiscan_lst_rslts_valid;
};

struct vsc9953_mii_read_scan {
	u32	mii_scan_results_sticky[2];
};

struct vsc9953_devcpu_gcb {
	struct vsc9953_chip_regs	chip_regs;
	struct vsc9953_gpio		gpio;
	struct vsc9953_mii_mng	mii_mng[2];
	struct vsc9953_mii_read_scan	mii_read_scan;
};

/* END VSC9953 DEVCPU_GCB structure */

/* VSC9953 IS* structure */

struct vsc9953_vcap_core_cfg {
	u32	vcap_update_ctrl;
	u32	vcap_mv_cfg;
};

struct vsc9953_vcap {
	struct vsc9953_vcap_core_cfg	vcap_core_cfg;
};

/* END VSC9953 IS* structure */

#define VSC9953_PORT_INFO_INITIALIZER(idx) \
{									\
	.enabled	= 0,						\
	.phyaddr	= 0,						\
	.index		= idx,						\
	.phy_regs	= NULL,						\
	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
	.bus		= NULL,						\
	.phydev		= NULL,						\
}

/* Structure to describe a VSC9953 port */
struct vsc9953_port_info {
	u8	enabled;
	u8	phyaddr;
	int	index;
	void	*phy_regs;
	phy_interface_t	enet_if;
	struct mii_dev	*bus;
	struct phy_device	*phydev;
};

/* Structure to describe a VSC9953 switch */
struct vsc9953_info {
	struct vsc9953_port_info	port[VSC9953_MAX_PORTS];
};

void vsc9953_init(bd_t *bis);

void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
void vsc9953_port_info_set_phy_address(int port_no, int address);
void vsc9953_port_enable(int port_no);
void vsc9953_port_disable(int port_no);
void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);

#endif /* _VSC9953_H_ */
Commit	Line	Data
6706b115 CC	1	/*
	2	* vsc9953.h
	3	*
	4	* Driver for the Vitesse VSC9953 L2 Switch
	5	*
	6	* This software may be used and distributed according to the
	7	* terms of the GNU Public License, Version 2, incorporated
	8	* herein by reference.
	9	*
	10	* Copyright 2013 Freescale Semiconductor, Inc.
	11	*
	12	*/
	13
	14	#ifndef _VSC9953_H_
	15	#define _VSC9953_H_
	16
	17	#include <config.h>
	18	#include <miiphy.h>
	19	#include <asm/types.h>
6706b115 CC	20
	21	#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
	22
	23	#define VSC9953_SYS_OFFSET 0x010000
9de05987	24	#define VSC9953_REW_OFFSET 0x030000
6706b115 CC	25	#define VSC9953_DEV_GMII_OFFSET 0x100000
	26	#define VSC9953_QSYS_OFFSET 0x200000
	27	#define VSC9953_ANA_OFFSET 0x280000
	28	#define VSC9953_DEVCPU_GCB 0x070000
	29	#define VSC9953_ES0 0x040000
	30	#define VSC9953_IS1 0x050000
	31	#define VSC9953_IS2 0x060000
	32
	33	#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
	34	#define VSC9953_PHY_REGS_OFFST 0x0000AC
	35
3cc8cfff	36	/* Macros for vsc9953_chip_regs.soft_rst register */
c4390486	37	#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
3cc8cfff CC	38
3cc8cfff CC	39	/* Macros for vsc9953_sys_sys.reset_cfg register */
c4390486 CC	40	#define VSC9953_CORE_ENABLE 0x80
	41	#define VSC9953_MEM_ENABLE 0x40
	42	#define VSC9953_MEM_INIT 0x20
6706b115	43
3cc8cfff	44	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
c4390486	45	#define VSC9953_MAC_ENA_CFG 0x00000011
3cc8cfff CC	46
3cc8cfff CC	47	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
c4390486	48	#define VSC9953_MAC_MODE_CFG 0x00000011
3cc8cfff CC	49
3cc8cfff CC	50	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
c4390486	51	#define VSC9953_MAC_IFG_CFG 0x00000515
3cc8cfff CC	52
3cc8cfff CC	53	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
c4390486	54	#define VSC9953_MAC_HDX_CFG 0x00001043
3cc8cfff CC	55
	56	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
	57	#define VSC9953_MAC_MAX_LEN 0x000005ee
	58
	59	/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
c4390486 CC	60	#define VSC9953_CLOCK_CFG 0x00000001
c4390486 CC	61	#define VSC9953_CLOCK_CFG_1000M 0x00000001
3cc8cfff CC	62
	63	/* Macros for vsc9953_sys_sys.front_port_mode register */
	64	#define VSC9953_FRONT_PORT_MODE 0x00000000
	65
	66	/* Macros for vsc9953_ana_pfc.pfc_cfg register */
c4390486 CC	67	#define VSC9953_PFC_FC 0x00000001
c4390486 CC	68	#define VSC9953_PFC_FC_QSGMII 0x00000000
3cc8cfff CC	69
3cc8cfff CC	70	/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
c4390486 CC	71	#define VSC9953_MAC_FC_CFG 0x04700000
c4390486 CC	72	#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
3cc8cfff CC	73
3cc8cfff CC	74	/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
c4390486	75	#define VSC9953_PAUSE_CFG 0x001ffffe
3cc8cfff CC	76
3cc8cfff CC	77	/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
c4390486	78	#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
6706b115	79
86719f0c CC	80	/* Macros for vsc9953_sys_sys.stat_cfg register */
	81	#define VSC9953_STAT_CLEAR_RX 0x00000400
	82	#define VSC9953_STAT_CLEAR_TX 0x00000800
	83	#define VSC9953_STAT_CLEAR_DR 0x00001000
	84
3cc8cfff	85	/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
c4390486 CC	86	#define VSC9953_VCAP_MV_CFG 0x0000ffff
c4390486 CC	87	#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
3cc8cfff	88
9de05987 CC	89	/* Macros for vsc9953_ana_port.vlan_cfg register */
	90	#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
	91	#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
	92	#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
	93
	94	/* Macros for vsc9953_rew_port.port_vlan_cfg register */
	95	#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
	96
	97	/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
	98	#define VSC9953_ANA_TBL_VID_MASK 0x00000fff
	99
	100	/* Macros for vsc9953_ana_ana_tables.vlan_access register */
	101	#define VSC9953_VLAN_PORT_MASK 0x00001ffc
	102	#define VSC9953_VLAN_CMD_MASK 0x00000003
	103	#define VSC9953_VLAN_CMD_IDLE 0x00000000
	104	#define VSC9953_VLAN_CMD_READ 0x00000001
	105	#define VSC9953_VLAN_CMD_WRITE 0x00000002
	106	#define VSC9953_VLAN_CMD_INIT 0x00000003
	107
68c929da CC	108	/* Macros for vsc9953_ana_port.port_cfg register */
	109	#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
	110	#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
	111	#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
	112	#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
	113
3cc8cfff	114	/* Macros for vsc9953_qsys_sys.switch_port_mode register */
fe91095b	115	#define VSC9953_PORT_ENA 0x00002000
3cc8cfff	116
9de05987 CC	117	/* Macros for vsc9953_ana_ana.adv_learn register */
	118	#define VSC9953_VLAN_CHK 0x00000400
	119
	120	/* Macros for vsc9953_rew_port.port_tag_cfg register */
	121	#define VSC9953_TAG_CFG_MASK 0x00000180
	122	#define VSC9953_TAG_CFG_NONE 0x00000000
	123	#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
	124	#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
	125	#define VSC9953_TAG_CFG_ALL 0x00000180
	126
6706b115 CC	127	#define VSC9953_MAX_PORTS 10
	128	#define VSC9953_PORT_CHECK(port) \
	129	(((port) < 0 \|\| (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
	130	#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	131	( \
	132	(port) < VSC9953_MAX_PORTS - 2 \|\| (port) >= VSC9953_MAX_PORTS \
	133	) ? 0 : 1 \
	134	)
9de05987 CC	135	#define VSC9953_MAX_VLAN 4096
	136	#define VSC9953_VLAN_CHECK(vid) \
	137	(((vid) < 0 \|\| (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
6706b115 CC	138
	139	#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
	140
	141	#define MIIMIND_OPR_PEND 0x00000004
	142
	143	struct vsc9953_mdio_info {
	144	struct vsc9953_mii_mng *regs;
	145	char *name;
	146	};
	147
3cc8cfff	148	/* VSC9953 ANA structure */
6706b115	149
3cc8cfff	150	struct vsc9953_ana_port {
6706b115 CC	151	u32 vlan_cfg;
	152	u32 drop_cfg;
	153	u32 qos_cfg;
	154	u32 vcap_cfg;
	155	u32 vcap_s1_key_cfg[3];
	156	u32 vcap_s2_cfg;
	157	u32 qos_pcp_dei_map_cfg[16];
	158	u32 cpu_fwd_cfg;
	159	u32 cpu_fwd_bpdu_cfg;
	160	u32 cpu_fwd_garp_cfg;
	161	u32 cpu_fwd_ccm_cfg;
	162	u32 port_cfg;
	163	u32 pol_cfg;
	164	u32 reserved[34];
	165	};
	166
	167	struct vsc9953_ana_pol {
	168	u32 pol_pir_cfg;
	169	u32 pol_cir_cfg;
	170	u32 pol_mode_cfg;
	171	u32 pol_pir_state;
	172	u32 pol_cir_state;
	173	u32 reserved1[3];
	174	};
	175
	176	struct vsc9953_ana_ana_tables {
	177	u32 entry_lim[11];
	178	u32 an_moved;
	179	u32 mach_data;
	180	u32 macl_data;
	181	u32 mac_access;
	182	u32 mact_indx;
	183	u32 vlan_access;
	184	u32 vlan_tidx;
	185	};
	186
	187	struct vsc9953_ana_ana {
	188	u32 adv_learn;
	189	u32 vlan_mask;
440873df	190	u32 reserved;
6706b115 CC	191	u32 anag_efil;
	192	u32 an_events;
	193	u32 storm_limit_burst;
	194	u32 storm_limit_cfg[4];
	195	u32 isolated_prts;
	196	u32 community_ports;
	197	u32 auto_age;
	198	u32 mac_options;
	199	u32 learn_disc;
	200	u32 agen_ctrl;
	201	u32 mirror_ports;
	202	u32 emirror_ports;
	203	u32 flooding;
	204	u32 flooding_ipmc;
	205	u32 sflow_cfg[11];
	206	u32 port_mode[12];
	207	};
	208
	209	struct vsc9953_ana_pgid {
	210	u32 port_grp_id[91];
	211	};
	212
3cc8cfff	213	struct vsc9953_ana_pfc {
6706b115 CC	214	u32 pfc_cfg;
	215	u32 reserved1[15];
	216	};
	217
	218	struct vsc9953_ana_pol_misc {
	219	u32 pol_flowc[10];
	220	u32 reserved1[17];
	221	u32 pol_hyst;
	222	};
	223
3cc8cfff	224	struct vsc9953_ana_common {
6706b115 CC	225	u32 aggr_cfg;
	226	u32 cpuq_cfg;
	227	u32 cpuq_8021_cfg;
	228	u32 dscp_cfg;
	229	u32 dscp_rewr_cfg;
	230	u32 vcap_rng_type_cfg;
	231	u32 vcap_rng_val_cfg;
	232	u32 discard_cfg;
	233	u32 fid_cfg;
	234	};
	235
	236	struct vsc9953_analyzer {
	237	struct vsc9953_ana_port port[11];
	238	u32 reserved1[9536];
	239	struct vsc9953_ana_pol pol[164];
	240	struct vsc9953_ana_ana_tables ana_tables;
	241	u32 reserved2[14];
	242	struct vsc9953_ana_ana ana;
	243	u32 reserved3[22];
	244	struct vsc9953_ana_pgid port_id_tbl;
	245	u32 reserved4[549];
	246	struct vsc9953_ana_pfc pfc[10];
	247	struct vsc9953_ana_pol_misc pol_misc;
	248	u32 reserved5[196];
	249	struct vsc9953_ana_common common;
	250	};
3cc8cfff	251	/* END VSC9953 ANA structure t*/
6706b115	252
3cc8cfff	253	/* VSC9953 DEV_GMII structure */
6706b115	254
3cc8cfff	255	struct vsc9953_dev_gmii_port_mode {
6706b115 CC	256	u32 clock_cfg;
	257	u32 port_misc;
	258	u32 reserved1;
	259	u32 eee_cfg;
	260	};
	261
3cc8cfff	262	struct vsc9953_dev_gmii_mac_cfg_status {
6706b115 CC	263	u32 mac_ena_cfg;
	264	u32 mac_mode_cfg;
	265	u32 mac_maxlen_cfg;
	266	u32 mac_tags_cfg;
	267	u32 mac_adv_chk_cfg;
	268	u32 mac_ifg_cfg;
	269	u32 mac_hdx_cfg;
	270	u32 mac_fc_mac_low_cfg;
	271	u32 mac_fc_mac_high_cfg;
	272	u32 mac_sticky;
	273	};
	274
	275	struct vsc9953_dev_gmii {
	276	struct vsc9953_dev_gmii_port_mode port_mode;
	277	struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
	278	};
	279
3cc8cfff	280	/* END VSC9953 DEV_GMII structure */
6706b115	281
3cc8cfff	282	/* VSC9953 QSYS structure */
6706b115	283
3cc8cfff	284	struct vsc9953_qsys_hsch {
6706b115 CC	285	u32 cir_cfg;
	286	u32 reserved1;
	287	u32 se_cfg;
	288	u32 se_dwrr_cfg[8];
	289	u32 cir_state;
	290	u32 reserved2[20];
	291	};
	292
3cc8cfff	293	struct vsc9953_qsys_sys {
6706b115 CC	294	u32 port_mode[12];
	295	u32 switch_port_mode[11];
	296	u32 stat_cnt_cfg;
	297	u32 eee_cfg[10];
	298	u32 eee_thrs;
	299	u32 igr_no_sharing;
	300	u32 egr_no_sharing;
	301	u32 sw_status[11];
	302	u32 ext_cpu_cfg;
	303	u32 cpu_group_map;
	304	u32 reserved1[23];
	305	};
	306
3cc8cfff	307	struct vsc9953_qsys_qos_cfg {
6706b115 CC	308	u32 red_profile[16];
	309	u32 res_qos_mode;
	310	};
	311
3cc8cfff	312	struct vsc9953_qsys_drop_cfg {
6706b115 CC	313	u32 egr_drop_mode;
	314	};
	315
3cc8cfff	316	struct vsc9953_qsys_mmgt {
6706b115 CC	317	u32 eq_cntrl;
	318	u32 reserved1;
	319	};
	320
3cc8cfff	321	struct vsc9953_qsys_hsch_misc {
6706b115 CC	322	u32 hsch_misc_cfg;
	323	u32 reserved1[546];
	324	};
	325
3cc8cfff	326	struct vsc9953_qsys_res_ctrl {
6706b115 CC	327	u32 res_cfg;
	328	u32 res_stat;
	329
	330	};
	331
3cc8cfff	332	struct vsc9953_qsys_reg {
6706b115 CC	333	struct vsc9953_qsys_hsch hsch[108];
	334	struct vsc9953_qsys_sys sys;
	335	struct vsc9953_qsys_qos_cfg qos_cfg;
	336	struct vsc9953_qsys_drop_cfg drop_cfg;
	337	struct vsc9953_qsys_mmgt mmgt;
	338	struct vsc9953_qsys_hsch_misc hsch_misc;
	339	struct vsc9953_qsys_res_ctrl res_ctrl[1024];
	340	};
	341
3cc8cfff	342	/* END VSC9953 QSYS structure */
6706b115	343
3cc8cfff	344	/* VSC9953 SYS structure */
6706b115	345
86719f0c CC	346	struct vsc9953_rx_cntrs {
	347	u32 c_rx_oct;
	348	u32 c_rx_uc;
	349	u32 c_rx_mc;
	350	u32 c_rx_bc;
	351	u32 c_rx_short;
	352	u32 c_rx_frag;
	353	u32 c_rx_jabber;
	354	u32 c_rx_crc;
	355	u32 c_rx_symbol_err;
	356	u32 c_rx_sz_64;
	357	u32 c_rx_sz_65_127;
	358	u32 c_rx_sz_128_255;
	359	u32 c_rx_sz_256_511;
	360	u32 c_rx_sz_512_1023;
	361	u32 c_rx_sz_1024_1526;
	362	u32 c_rx_sz_jumbo;
	363	u32 c_rx_pause;
	364	u32 c_rx_control;
	365	u32 c_rx_long;
	366	u32 c_rx_cat_drop;
	367	u32 c_rx_red_prio_0;
	368	u32 c_rx_red_prio_1;
	369	u32 c_rx_red_prio_2;
	370	u32 c_rx_red_prio_3;
	371	u32 c_rx_red_prio_4;
	372	u32 c_rx_red_prio_5;
	373	u32 c_rx_red_prio_6;
	374	u32 c_rx_red_prio_7;
	375	u32 c_rx_yellow_prio_0;
	376	u32 c_rx_yellow_prio_1;
	377	u32 c_rx_yellow_prio_2;
	378	u32 c_rx_yellow_prio_3;
	379	u32 c_rx_yellow_prio_4;
	380	u32 c_rx_yellow_prio_5;
	381	u32 c_rx_yellow_prio_6;
	382	u32 c_rx_yellow_prio_7;
	383	u32 c_rx_green_prio_0;
	384	u32 c_rx_green_prio_1;
	385	u32 c_rx_green_prio_2;
	386	u32 c_rx_green_prio_3;
	387	u32 c_rx_green_prio_4;
	388	u32 c_rx_green_prio_5;
	389	u32 c_rx_green_prio_6;
	390	u32 c_rx_green_prio_7;
	391	u32 reserved[20];
	392	};
	393
	394	struct vsc9953_tx_cntrs {
	395	u32 c_tx_oct;
	396	u32 c_tx_uc;
	397	u32 c_tx_mc;
	398	u32 c_tx_bc;
	399	u32 c_tx_col;
	400	u32 c_tx_drop;
	401	u32 c_tx_pause;
	402	u32 c_tx_sz_64;
	403	u32 c_tx_sz_65_127;
	404	u32 c_tx_sz_128_255;
	405	u32 c_tx_sz_256_511;
	406	u32 c_tx_sz_512_1023;
	407	u32 c_tx_sz_1024_1526;
	408	u32 c_tx_sz_jumbo;
	409	u32 c_tx_yellow_prio_0;
410	u32 c_tx_yellow_prio_1;
411	u32 c_tx_yellow_prio_2;
412	u32 c_tx_yellow_prio_3;
413	u32 c_tx_yellow_prio_4;
414	u32 c_tx_yellow_prio_5;
415	u32 c_tx_yellow_prio_6;
416	u32 c_tx_yellow_prio_7;
417	u32 c_tx_green_prio_0;
418	u32 c_tx_green_prio_1;
419	u32 c_tx_green_prio_2;
420	u32 c_tx_green_prio_3;
421	u32 c_tx_green_prio_4;
422	u32 c_tx_green_prio_5;
423	u32 c_tx_green_prio_6;
424	u32 c_tx_green_prio_7;
425	u32 c_tx_aged;
426	u32 reserved[33];
427	};
428
429	struct vsc9953_drop_cntrs {
430	u32 c_dr_local;
431	u32 c_dr_tail;
432	u32 c_dr_yellow_prio_0;
433	u32 c_dr_yellow_prio_1;
434	u32 c_dr_yellow_prio_2;
435	u32 c_dr_yellow_prio_3;
436	u32 c_dr_yellow_prio_4;
437	u32 c_dr_yellow_prio_5;
438	u32 c_dr_yellow_prio_6;
439	u32 c_dr_yellow_prio_7;
440	u32 c_dr_green_prio_0;
441	u32 c_dr_green_prio_1;
442	u32 c_dr_green_prio_2;
443	u32 c_dr_green_prio_3;
444	u32 c_dr_green_prio_4;
445	u32 c_dr_green_prio_5;
446	u32 c_dr_green_prio_6;
447	u32 c_dr_green_prio_7;
448	u32 reserved[46];
449	};
450
3cc8cfff	451	struct vsc9953_sys_stat {
86719f0c CC	452	struct vsc9953_rx_cntrs rx_cntrs;
	453	struct vsc9953_tx_cntrs tx_cntrs;
	454	struct vsc9953_drop_cntrs drop_cntrs;
6706b115 CC	455	u32 reserved1[6];
	456	};
	457
3cc8cfff	458	struct vsc9953_sys_sys {
6706b115 CC	459	u32 reset_cfg;
	460	u32 reserved1;
	461	u32 vlan_etype_cfg;
	462	u32 port_mode[12];
	463	u32 front_port_mode[10];
	464	u32 frame_aging;
	465	u32 stat_cfg;
	466	u32 reserved2[50];
	467	};
	468
3cc8cfff	469	struct vsc9953_sys_pause_cfg {
6706b115 CC	470	u32 pause_cfg[11];
	471	u32 pause_tot_cfg;
	472	u32 tail_drop_level[11];
	473	u32 tot_tail_drop_lvl;
	474	u32 mac_fc_cfg[10];
	475	};
	476
3cc8cfff	477	struct vsc9953_sys_mmgt {
6706b115 CC	478	u16 free_cnt;
	479	};
	480
3cc8cfff	481	struct vsc9953_system_reg {
6706b115 CC	482	struct vsc9953_sys_stat stat;
	483	struct vsc9953_sys_sys sys;
	484	struct vsc9953_sys_pause_cfg pause_cfg;
	485	struct vsc9953_sys_mmgt mmgt;
	486	};
	487
3cc8cfff	488	/* END VSC9953 SYS structure */
6706b115	489
9de05987 CC	490	/* VSC9953 REW structure */
	491
	492	struct vsc9953_rew_port {
	493	u32 port_vlan_cfg;
	494	u32 port_tag_cfg;
	495	u32 port_port_cfg;
	496	u32 port_dscp_cfg;
	497	u32 port_pcp_dei_qos_map_cfg[16];
	498	u32 reserved[12];
	499	};
	500
	501	struct vsc9953_rew_common {
	502	u32 reserve[4];
	503	u32 dscp_remap_dp1_cfg[64];
	504	u32 dscp_remap_cfg[64];
	505	};
	506
	507	struct vsc9953_rew_reg {
	508	struct vsc9953_rew_port port[12];
	509	struct vsc9953_rew_common common;
	510	};
	511
	512	/* END VSC9953 REW structure */
6706b115	513
3cc8cfff	514	/* VSC9953 DEVCPU_GCB structure */
6706b115	515
3cc8cfff	516	struct vsc9953_chip_regs {
6706b115 CC	517	u32 chipd_id;
	518	u32 gpr;
	519	u32 soft_rst;
	520	};
	521
3cc8cfff	522	struct vsc9953_gpio {
6706b115 CC	523	u32 gpio_out_set[10];
	524	u32 gpio_out_clr[10];
	525	u32 gpio_out[10];
	526	u32 gpio_in[10];
	527	};
	528
	529	struct vsc9953_mii_mng {
	530	u32 miimstatus;
	531	u32 reserved1;
	532	u32 miimcmd;
	533	u32 miimdata;
	534	u32 miimcfg;
	535	u32 miimscan_0;
	536	u32 miimscan_1;
	537	u32 miiscan_lst_rslts;
	538	u32 miiscan_lst_rslts_valid;
	539	};
	540
3cc8cfff	541	struct vsc9953_mii_read_scan {
6706b115 CC	542	u32 mii_scan_results_sticky[2];
	543	};
	544
3cc8cfff	545	struct vsc9953_devcpu_gcb {
6706b115 CC	546	struct vsc9953_chip_regs chip_regs;
	547	struct vsc9953_gpio gpio;
	548	struct vsc9953_mii_mng mii_mng[2];
	549	struct vsc9953_mii_read_scan mii_read_scan;
	550	};
	551
3cc8cfff	552	/* END VSC9953 DEVCPU_GCB structure */
6706b115	553
3cc8cfff	554	/* VSC9953 IS* structure */
6706b115	555
3cc8cfff	556	struct vsc9953_vcap_core_cfg {
6706b115 CC	557	u32 vcap_update_ctrl;
	558	u32 vcap_mv_cfg;
	559	};
	560
3cc8cfff CC	561	struct vsc9953_vcap {
3cc8cfff CC	562	struct vsc9953_vcap_core_cfg vcap_core_cfg;
6706b115 CC	563	};
6706b115 CC	564
3cc8cfff	565	/* END VSC9953 IS* structure */
6706b115 CC	566
	567	#define VSC9953_PORT_INFO_INITIALIZER(idx) \
	568	{ \
	569	.enabled = 0, \
	570	.phyaddr = 0, \
	571	.index = idx, \
	572	.phy_regs = NULL, \
	573	.enet_if = PHY_INTERFACE_MODE_NONE, \
	574	.bus = NULL, \
	575	.phydev = NULL, \
	576	}
	577
	578	/* Structure to describe a VSC9953 port */
	579	struct vsc9953_port_info {
	580	u8 enabled;
	581	u8 phyaddr;
	582	int index;
	583	void *phy_regs;
	584	phy_interface_t enet_if;
	585	struct mii_dev *bus;
	586	struct phy_device *phydev;
	587	};
	588
	589	/* Structure to describe a VSC9953 switch */
	590	struct vsc9953_info {
3cc8cfff	591	struct vsc9953_port_info port[VSC9953_MAX_PORTS];
6706b115 CC	592	};
	593
	594	void vsc9953_init(bd_t *bis);
	595
3cc8cfff CC	596	void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
	597	void vsc9953_port_info_set_phy_address(int port_no, int address);
	598	void vsc9953_port_enable(int port_no);
	599	void vsc9953_port_disable(int port_no);
	600	void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
6706b115 CC	601
6706b115 CC	602	#endif /* _VSC9953_H_ */