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Allow dynamic initialization of thread_locals.
[thirdparty/gcc.git] / include / xtensa-config.h
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03984308 1/* Xtensa configuration settings.
d652f226 2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
fbee3d21 3 Free Software Foundation, Inc.
db94b0d8 4 Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
03984308 5
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6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
d6d47ea0 18 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
03984308
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19
20#ifndef XTENSA_CONFIG_H
21#define XTENSA_CONFIG_H
22
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23/* The macros defined here match those with the same names in the Xtensa
24 compile-time HAL (Hardware Abstraction Layer). Please refer to the
25 Xtensa System Software Reference Manual for documentation of these
26 macros. */
27
b31185fe 28#undef XCHAL_HAVE_BE
03984308 29#define XCHAL_HAVE_BE 1
b31185fe
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30
31#undef XCHAL_HAVE_DENSITY
03984308 32#define XCHAL_HAVE_DENSITY 1
b31185fe
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33
34#undef XCHAL_HAVE_CONST16
f42f5a1b 35#define XCHAL_HAVE_CONST16 0
b31185fe
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36
37#undef XCHAL_HAVE_ABS
6c2e8d1c 38#define XCHAL_HAVE_ABS 1
b31185fe
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39
40#undef XCHAL_HAVE_ADDX
6c2e8d1c 41#define XCHAL_HAVE_ADDX 1
b31185fe
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42
43#undef XCHAL_HAVE_L32R
f42f5a1b 44#define XCHAL_HAVE_L32R 1
b31185fe 45
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46#undef XSHAL_USE_ABSOLUTE_LITERALS
47#define XSHAL_USE_ABSOLUTE_LITERALS 0
48
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49#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
50#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
51
b31185fe 52#undef XCHAL_HAVE_MAC16
03984308 53#define XCHAL_HAVE_MAC16 0
b31185fe
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54
55#undef XCHAL_HAVE_MUL16
2ad646bd 56#define XCHAL_HAVE_MUL16 1
b31185fe
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57
58#undef XCHAL_HAVE_MUL32
2ad646bd 59#define XCHAL_HAVE_MUL32 1
b31185fe 60
134c8a50
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61#undef XCHAL_HAVE_MUL32_HIGH
62#define XCHAL_HAVE_MUL32_HIGH 0
63
b31185fe 64#undef XCHAL_HAVE_DIV32
2ad646bd 65#define XCHAL_HAVE_DIV32 1
b31185fe
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66
67#undef XCHAL_HAVE_NSA
03984308 68#define XCHAL_HAVE_NSA 1
b31185fe
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69
70#undef XCHAL_HAVE_MINMAX
2ad646bd 71#define XCHAL_HAVE_MINMAX 1
b31185fe
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72
73#undef XCHAL_HAVE_SEXT
2ad646bd 74#define XCHAL_HAVE_SEXT 1
b31185fe
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75
76#undef XCHAL_HAVE_LOOPS
e2fb85da 77#define XCHAL_HAVE_LOOPS 1
b31185fe 78
2a48b790 79#undef XCHAL_HAVE_THREADPTR
2ad646bd 80#define XCHAL_HAVE_THREADPTR 1
2a48b790
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81
82#undef XCHAL_HAVE_RELEASE_SYNC
2ad646bd 83#define XCHAL_HAVE_RELEASE_SYNC 1
2a48b790
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84
85#undef XCHAL_HAVE_S32C1I
2ad646bd 86#define XCHAL_HAVE_S32C1I 1
2a48b790 87
b31185fe 88#undef XCHAL_HAVE_BOOLEANS
03984308 89#define XCHAL_HAVE_BOOLEANS 0
b31185fe
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90
91#undef XCHAL_HAVE_FP
03984308 92#define XCHAL_HAVE_FP 0
b31185fe
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93
94#undef XCHAL_HAVE_FP_DIV
03984308 95#define XCHAL_HAVE_FP_DIV 0
b31185fe
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96
97#undef XCHAL_HAVE_FP_RECIP
03984308 98#define XCHAL_HAVE_FP_RECIP 0
b31185fe
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99
100#undef XCHAL_HAVE_FP_SQRT
03984308 101#define XCHAL_HAVE_FP_SQRT 0
b31185fe
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102
103#undef XCHAL_HAVE_FP_RSQRT
03984308 104#define XCHAL_HAVE_FP_RSQRT 0
b31185fe 105
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106#undef XCHAL_HAVE_DFP_accel
107#define XCHAL_HAVE_DFP_accel 0
b31185fe 108#undef XCHAL_HAVE_WINDOWED
e677f70c 109#define XCHAL_HAVE_WINDOWED 1
03984308 110
5fd38b88 111#undef XCHAL_NUM_AREGS
2ad646bd 112#define XCHAL_NUM_AREGS 32
5fd38b88 113
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114#undef XCHAL_HAVE_WIDE_BRANCHES
115#define XCHAL_HAVE_WIDE_BRANCHES 0
116
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117#undef XCHAL_HAVE_PREDICTED_BRANCHES
118#define XCHAL_HAVE_PREDICTED_BRANCHES 0
119
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120
121#undef XCHAL_ICACHE_SIZE
2ad646bd 122#define XCHAL_ICACHE_SIZE 16384
b31185fe
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123
124#undef XCHAL_DCACHE_SIZE
2ad646bd 125#define XCHAL_DCACHE_SIZE 16384
b31185fe
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126
127#undef XCHAL_ICACHE_LINESIZE
2ad646bd 128#define XCHAL_ICACHE_LINESIZE 32
b31185fe
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129
130#undef XCHAL_DCACHE_LINESIZE
2ad646bd 131#define XCHAL_DCACHE_LINESIZE 32
b31185fe
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132
133#undef XCHAL_ICACHE_LINEWIDTH
2ad646bd 134#define XCHAL_ICACHE_LINEWIDTH 5
b31185fe
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135
136#undef XCHAL_DCACHE_LINEWIDTH
2ad646bd 137#define XCHAL_DCACHE_LINEWIDTH 5
b31185fe
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138
139#undef XCHAL_DCACHE_IS_WRITEBACK
2ad646bd 140#define XCHAL_DCACHE_IS_WRITEBACK 1
03984308 141
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142
143#undef XCHAL_HAVE_MMU
03984308 144#define XCHAL_HAVE_MMU 1
b31185fe
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145
146#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
03984308
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147#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
148
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149
150#undef XCHAL_HAVE_DEBUG
e677f70c 151#define XCHAL_HAVE_DEBUG 1
b31185fe
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152
153#undef XCHAL_NUM_IBREAK
e677f70c 154#define XCHAL_NUM_IBREAK 2
b31185fe
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155
156#undef XCHAL_NUM_DBREAK
e677f70c 157#define XCHAL_NUM_DBREAK 2
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158
159#undef XCHAL_DEBUGLEVEL
2ad646bd 160#define XCHAL_DEBUGLEVEL 6
e677f70c 161
b31185fe 162
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163#undef XCHAL_MAX_INSTRUCTION_SIZE
164#define XCHAL_MAX_INSTRUCTION_SIZE 3
165
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166#undef XCHAL_INST_FETCH_WIDTH
167#define XCHAL_INST_FETCH_WIDTH 4
e677f70c 168
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169
170#undef XSHAL_ABI
171#undef XTHAL_ABI_WINDOWED
172#undef XTHAL_ABI_CALL0
173#define XSHAL_ABI XTHAL_ABI_WINDOWED
174#define XTHAL_ABI_WINDOWED 0
175#define XTHAL_ABI_CALL0 1
176
03984308 177#endif /* !XTENSA_CONFIG_H */