]> git.ipfire.org Git - thirdparty/gcc.git/blame - include/xtensa-config.h
Fix division by zero in loop splitting
[thirdparty/gcc.git] / include / xtensa-config.h
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03984308 1/* Xtensa configuration settings.
83ffe9cd 2 Copyright (C) 2001-2023 Free Software Foundation, Inc.
db94b0d8 3 Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
03984308 4
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5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
d6d47ea0 17 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
03984308
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18
19#ifndef XTENSA_CONFIG_H
20#define XTENSA_CONFIG_H
21
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22/* The macros defined here match those with the same names in the Xtensa
23 compile-time HAL (Hardware Abstraction Layer). Please refer to the
24 Xtensa System Software Reference Manual for documentation of these
25 macros. */
26
b31185fe 27#undef XCHAL_HAVE_BE
03984308 28#define XCHAL_HAVE_BE 1
b31185fe
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29
30#undef XCHAL_HAVE_DENSITY
03984308 31#define XCHAL_HAVE_DENSITY 1
b31185fe
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32
33#undef XCHAL_HAVE_CONST16
f42f5a1b 34#define XCHAL_HAVE_CONST16 0
b31185fe
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35
36#undef XCHAL_HAVE_ABS
6c2e8d1c 37#define XCHAL_HAVE_ABS 1
b31185fe
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38
39#undef XCHAL_HAVE_ADDX
6c2e8d1c 40#define XCHAL_HAVE_ADDX 1
b31185fe
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41
42#undef XCHAL_HAVE_L32R
f42f5a1b 43#define XCHAL_HAVE_L32R 1
b31185fe 44
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45#undef XSHAL_USE_ABSOLUTE_LITERALS
46#define XSHAL_USE_ABSOLUTE_LITERALS 0
47
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48#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
49#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
50
b31185fe 51#undef XCHAL_HAVE_MAC16
03984308 52#define XCHAL_HAVE_MAC16 0
b31185fe
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53
54#undef XCHAL_HAVE_MUL16
2ad646bd 55#define XCHAL_HAVE_MUL16 1
b31185fe
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56
57#undef XCHAL_HAVE_MUL32
2ad646bd 58#define XCHAL_HAVE_MUL32 1
b31185fe 59
134c8a50
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60#undef XCHAL_HAVE_MUL32_HIGH
61#define XCHAL_HAVE_MUL32_HIGH 0
62
b31185fe 63#undef XCHAL_HAVE_DIV32
2ad646bd 64#define XCHAL_HAVE_DIV32 1
b31185fe
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65
66#undef XCHAL_HAVE_NSA
03984308 67#define XCHAL_HAVE_NSA 1
b31185fe
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68
69#undef XCHAL_HAVE_MINMAX
2ad646bd 70#define XCHAL_HAVE_MINMAX 1
b31185fe
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71
72#undef XCHAL_HAVE_SEXT
2ad646bd 73#define XCHAL_HAVE_SEXT 1
b31185fe
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74
75#undef XCHAL_HAVE_LOOPS
e2fb85da 76#define XCHAL_HAVE_LOOPS 1
b31185fe 77
2a48b790 78#undef XCHAL_HAVE_THREADPTR
2ad646bd 79#define XCHAL_HAVE_THREADPTR 1
2a48b790
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80
81#undef XCHAL_HAVE_RELEASE_SYNC
2ad646bd 82#define XCHAL_HAVE_RELEASE_SYNC 1
2a48b790
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83
84#undef XCHAL_HAVE_S32C1I
2ad646bd 85#define XCHAL_HAVE_S32C1I 1
2a48b790 86
b31185fe 87#undef XCHAL_HAVE_BOOLEANS
03984308 88#define XCHAL_HAVE_BOOLEANS 0
b31185fe
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89
90#undef XCHAL_HAVE_FP
03984308 91#define XCHAL_HAVE_FP 0
b31185fe
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92
93#undef XCHAL_HAVE_FP_DIV
03984308 94#define XCHAL_HAVE_FP_DIV 0
b31185fe
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95
96#undef XCHAL_HAVE_FP_RECIP
03984308 97#define XCHAL_HAVE_FP_RECIP 0
b31185fe
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98
99#undef XCHAL_HAVE_FP_SQRT
03984308 100#define XCHAL_HAVE_FP_SQRT 0
b31185fe
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101
102#undef XCHAL_HAVE_FP_RSQRT
03984308 103#define XCHAL_HAVE_FP_RSQRT 0
b31185fe 104
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105#undef XCHAL_HAVE_DFP_accel
106#define XCHAL_HAVE_DFP_accel 0
b31185fe 107#undef XCHAL_HAVE_WINDOWED
e677f70c 108#define XCHAL_HAVE_WINDOWED 1
03984308 109
5fd38b88 110#undef XCHAL_NUM_AREGS
2ad646bd 111#define XCHAL_NUM_AREGS 32
5fd38b88 112
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113#undef XCHAL_HAVE_WIDE_BRANCHES
114#define XCHAL_HAVE_WIDE_BRANCHES 0
115
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116#undef XCHAL_HAVE_PREDICTED_BRANCHES
117#define XCHAL_HAVE_PREDICTED_BRANCHES 0
118
b31185fe
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119
120#undef XCHAL_ICACHE_SIZE
2ad646bd 121#define XCHAL_ICACHE_SIZE 16384
b31185fe
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122
123#undef XCHAL_DCACHE_SIZE
2ad646bd 124#define XCHAL_DCACHE_SIZE 16384
b31185fe
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125
126#undef XCHAL_ICACHE_LINESIZE
2ad646bd 127#define XCHAL_ICACHE_LINESIZE 32
b31185fe
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128
129#undef XCHAL_DCACHE_LINESIZE
2ad646bd 130#define XCHAL_DCACHE_LINESIZE 32
b31185fe
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131
132#undef XCHAL_ICACHE_LINEWIDTH
2ad646bd 133#define XCHAL_ICACHE_LINEWIDTH 5
b31185fe
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134
135#undef XCHAL_DCACHE_LINEWIDTH
2ad646bd 136#define XCHAL_DCACHE_LINEWIDTH 5
b31185fe
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137
138#undef XCHAL_DCACHE_IS_WRITEBACK
2ad646bd 139#define XCHAL_DCACHE_IS_WRITEBACK 1
03984308 140
b31185fe
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141
142#undef XCHAL_HAVE_MMU
03984308 143#define XCHAL_HAVE_MMU 1
b31185fe
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144
145#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
03984308
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146#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
147
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148
149#undef XCHAL_HAVE_DEBUG
e677f70c 150#define XCHAL_HAVE_DEBUG 1
b31185fe
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151
152#undef XCHAL_NUM_IBREAK
e677f70c 153#define XCHAL_NUM_IBREAK 2
b31185fe
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154
155#undef XCHAL_NUM_DBREAK
e677f70c 156#define XCHAL_NUM_DBREAK 2
b31185fe
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157
158#undef XCHAL_DEBUGLEVEL
2ad646bd 159#define XCHAL_DEBUGLEVEL 6
e677f70c 160
b31185fe 161
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162#undef XCHAL_MAX_INSTRUCTION_SIZE
163#define XCHAL_MAX_INSTRUCTION_SIZE 3
164
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165#undef XCHAL_INST_FETCH_WIDTH
166#define XCHAL_INST_FETCH_WIDTH 4
e677f70c 167
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168
169#undef XSHAL_ABI
170#undef XTHAL_ABI_WINDOWED
171#undef XTHAL_ABI_CALL0
172#define XSHAL_ABI XTHAL_ABI_WINDOWED
173#define XTHAL_ABI_WINDOWED 0
174#define XTHAL_ABI_CALL0 1
175
03984308 176#endif /* !XTENSA_CONFIG_H */