[thirdparty/pciutils.git] / lib / header.h

/*
 *	$Id: header.h,v 1.8 2002/03/30 15:39:25 mj Exp $
 *
 *	The PCI Library -- PCI Header Structure (extracted from <linux/pci.h>)
 *
 *	Copyright (c) 1997--2002 Martin Mares <mj@ucw.cz>
 *
 *	Can be freely distributed and used under the terms of the GNU GPL.
 */

/*
 * Under PCI, each device has 256 bytes of configuration address space,
 * of which the first 64 bytes are standardized as follows:
 */
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */

#define PCI_STATUS		0x06	/* 16 bits */
#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
#define  PCI_STATUS_DEVSEL_FAST	0x000	
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
#define  PCI_STATUS_DEVSEL_SLOW 0x400
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */

#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
					   revision */
#define PCI_REVISION_ID         0x08    /* Revision ID */
#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */

#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL	0
#define  PCI_HEADER_TYPE_BRIDGE 1
#define  PCI_HEADER_TYPE_CARDBUS 2

#define PCI_BIST		0x0f	/* 8 bits */
#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */

/*
 * Base addresses specify locations in memory or I/O space.
 * Decoded size can be determined by writing a value of 
 * 0xffffffff to the register, and reading it back.  Only 
 * 1 bits are decoded.
 */
#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
/* bit 1 is reserved if address_space = 1 */

/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS		0x28
#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
#define PCI_SUBSYSTEM_ID	0x2e  
#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
#define  PCI_ROM_ADDRESS_ENABLE	0x01
#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)

#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */

/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
#define PCI_IO_LIMIT		0x1d
#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */
#define  PCI_IO_RANGE_TYPE_16	0x00
#define  PCI_IO_RANGE_TYPE_32	0x01
#define  PCI_IO_RANGE_MASK	~0x0f
#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
#define PCI_MEMORY_LIMIT	0x22
#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define  PCI_MEMORY_RANGE_MASK	~0x0f
#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT	0x26
#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
#define  PCI_PREF_RANGE_TYPE_32	0x00
#define  PCI_PREF_RANGE_TYPE_64	0x01
#define  PCI_PREF_RANGE_MASK	~0x0f
#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32	0x2c
#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16	0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL	0x3e
#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */

/* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */
#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0	0x1c
#define PCI_CB_MEMORY_LIMIT_0	0x20
#define PCI_CB_MEMORY_BASE_1	0x24
#define PCI_CB_MEMORY_LIMIT_1	0x28
#define PCI_CB_IO_BASE_0	0x2c
#define PCI_CB_IO_BASE_0_HI	0x2e
#define PCI_CB_IO_LIMIT_0	0x30
#define PCI_CB_IO_LIMIT_0_HI	0x32
#define PCI_CB_IO_BASE_1	0x34
#define PCI_CB_IO_BASE_1_HI	0x36
#define PCI_CB_IO_LIMIT_1	0x38
#define PCI_CB_IO_LIMIT_1_HI	0x3a
#define  PCI_CB_IO_RANGE_MASK	~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL	0x3e
#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
#define  PCI_CB_BRIDGE_CTL_SERR		0x02
#define  PCI_CB_BRIDGE_CTL_ISA		0x04
#define  PCI_CB_BRIDGE_CTL_VGA		0x08
#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID	0x42
#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */

/* Capability lists */

#define PCI_CAP_LIST_ID		0	/* Capability ID */
#define  PCI_CAP_ID_PM		0x01	/* Power Management */
#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF		4

/* Power Management Registers */

#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version (2=PM1.1) */
#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* Clock required for PME generation */
#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization required */
#define  PCI_PM_CAP_AUX_C_MASK	0x01c0	/* Maximum aux current required in D3cold */
#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
#define  PCI_PM_CAP_PME_D0	0x0800	/* PME can be asserted from D0 */
#define  PCI_PM_CAP_PME_D1	0x1000	/* PME can be asserted from D1 */
#define  PCI_PM_CAP_PME_D2	0x2000	/* PME can be asserted from D2 */
#define  PCI_PM_CAP_PME_D3_HOT	0x4000	/* PME can be asserted from D3hot */
#define  PCI_PM_CAP_PME_D3_COLD	0x8000	/* PME can be asserted from D3cold */
#define PCI_PM_CTRL		4	/* PM control and status register */
#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* PM table data index */
#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* PM table data scaling factor */
#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions */
#define  PCI_PM_PPB_B2_B3	0x40	/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
#define  PCI_PM_BPCC_ENABLE	0x80	/* Secondary bus is power managed */
#define PCI_PM_DATA_REGISTER	7	/* PM table contents read here */
#define PCI_PM_SIZEOF		8

/* AGP registers */

#define PCI_AGP_VERSION		2	/* BCD version number */
#define PCI_AGP_RFU		3	/* Rest of capability flags */
#define PCI_AGP_STATUS		4	/* Status register */
#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
#define PCI_AGP_COMMAND		8	/* Control register */
#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
#define PCI_AGP_SIZEOF		12

/* Slot Identification */

#define PCI_SID_ESR		2	/* Expansion Slot Register */
#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */

/* Message Signalled Interrupts registers */

#define PCI_MSI_FLAGS		2	/* Various flags */
#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
#define PCI_MSI_RFU		3	/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */

/* PCI-X */
#define PCI_PCIX_COMMAND                                                2 /* Command register offset */
#define PCI_PCIX_COMMAND_DPERE                                     0x0001 /* Data Parity Error Recover Enable */
#define PCI_PCIX_COMMAND_ERO                                       0x0002 /* Enable Relaxed Ordering */
#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT                   0x000c /* Maximum Memory Read Byte Count */
#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS               0x0070  
#define PCI_PCIX_COMMAND_RESERVED                                   0xf80
#define PCI_PCIX_STATUS                                                 4 /* Status register offset */
#define PCI_PCIX_STATUS_FUNCTION                               0x00000007
#define PCI_PCIX_STATUS_DEVICE                                 0x000000f8
#define PCI_PCIX_STATUS_BUS                                    0x0000ff00
#define PCI_PCIX_STATUS_64BIT                                  0x00010000
#define PCI_PCIX_STATUS_133MHZ                                 0x00020000
#define PCI_PCIX_STATUS_SC_DISCARDED                           0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_STATUS_UNEXPECTED_SC                          0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY                      0x00100000 /* 0 = simple device, 1 = bridge device */
#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT       0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS   0x03800000
#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE      0x1c000000
#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS                       0x20000000 /* Received Split Completion Error Message */
#define PCI_PCIX_STATUS_RESERVED                               0xc0000000
#define PCI_PCIX_SIZEOF		4

/* PCI-X Bridges */
#define PCI_PCIX_BRIDGE_SEC_STATUS                                      2 /* Secondary bus status register offset */
#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT                           0x0001
#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ                          0x0002
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED                    0x0004 /* Split Completion Discarded on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC                   0x0008 /* Unexpected Split Completion on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN                      0x0010 /* Split Completion Overrun on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED           0x0020
#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ                      0x01c0
#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED                        0xfe00
#define PCI_PCIX_BRIDGE_STATUS                                          4 /* Primary bus status register offset */
#define PCI_PCIX_BRIDGE_STATUS_FUNCTION                        0x00000007
#define PCI_PCIX_BRIDGE_STATUS_DEVICE                          0x000000f8
#define PCI_PCIX_BRIDGE_STATUS_BUS                             0x0000ff00
#define PCI_PCIX_BRIDGE_STATUS_64BIT                           0x00010000
#define PCI_PCIX_BRIDGE_STATUS_133MHZ                          0x00020000
#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED                    0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC                   0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN                      0x00100000 /* Split Completion Overrun */
#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED           0x00200000
#define PCI_PCIX_BRIDGE_STATUS_RESERVED                        0xffc00000
#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL                       8 /* Upstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL                    12 /* Downstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_STR_CAPACITY                           0x0000ffff
#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT                   0xffff0000
#define PCI_PCIX_BRIDGE_SIZEOF 12

/*
 * The PCI interface treats multi-function devices as independent
 * devices.  The slot/function address of each device is encoded
 * in a single byte as follows:
 *
 *	7:3 = slot
 *	2:0 = function
 */
#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)		((devfn) & 0x07)

/* Device classes and subclasses */

#define PCI_CLASS_NOT_DEFINED		0x0000
#define PCI_CLASS_NOT_DEFINED_VGA	0x0001

#define PCI_BASE_CLASS_STORAGE		0x01
#define PCI_CLASS_STORAGE_SCSI		0x0100
#define PCI_CLASS_STORAGE_IDE		0x0101
#define PCI_CLASS_STORAGE_FLOPPY	0x0102
#define PCI_CLASS_STORAGE_IPI		0x0103
#define PCI_CLASS_STORAGE_RAID		0x0104
#define PCI_CLASS_STORAGE_OTHER		0x0180

#define PCI_BASE_CLASS_NETWORK		0x02
#define PCI_CLASS_NETWORK_ETHERNET	0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
#define PCI_CLASS_NETWORK_FDDI		0x0202
#define PCI_CLASS_NETWORK_ATM		0x0203
#define PCI_CLASS_NETWORK_OTHER		0x0280

#define PCI_BASE_CLASS_DISPLAY		0x03
#define PCI_CLASS_DISPLAY_VGA		0x0300
#define PCI_CLASS_DISPLAY_XGA		0x0301
#define PCI_CLASS_DISPLAY_OTHER		0x0380

#define PCI_BASE_CLASS_MULTIMEDIA	0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480

#define PCI_BASE_CLASS_MEMORY		0x05
#define  PCI_CLASS_MEMORY_RAM		0x0500
#define  PCI_CLASS_MEMORY_FLASH		0x0501
#define  PCI_CLASS_MEMORY_OTHER		0x0580

#define PCI_BASE_CLASS_BRIDGE		0x06
#define  PCI_CLASS_BRIDGE_HOST		0x0600
#define  PCI_CLASS_BRIDGE_ISA		0x0601
#define  PCI_CLASS_BRIDGE_EISA		0x0602
#define  PCI_CLASS_BRIDGE_MC		0x0603
#define  PCI_CLASS_BRIDGE_PCI		0x0604
#define  PCI_CLASS_BRIDGE_PCMCIA	0x0605
#define  PCI_CLASS_BRIDGE_NUBUS		0x0606
#define  PCI_CLASS_BRIDGE_CARDBUS	0x0607
#define  PCI_CLASS_BRIDGE_OTHER		0x0680

#define PCI_BASE_CLASS_COMMUNICATION	0x07
#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_OTHER	0x0780

#define PCI_BASE_CLASS_SYSTEM		0x08
#define PCI_CLASS_SYSTEM_PIC		0x0800
#define PCI_CLASS_SYSTEM_DMA		0x0801
#define PCI_CLASS_SYSTEM_TIMER		0x0802
#define PCI_CLASS_SYSTEM_RTC		0x0803
#define PCI_CLASS_SYSTEM_OTHER		0x0880

#define PCI_BASE_CLASS_INPUT		0x09
#define PCI_CLASS_INPUT_KEYBOARD	0x0900
#define PCI_CLASS_INPUT_PEN		0x0901
#define PCI_CLASS_INPUT_MOUSE		0x0902
#define PCI_CLASS_INPUT_OTHER		0x0980

#define PCI_BASE_CLASS_DOCKING		0x0a
#define PCI_CLASS_DOCKING_GENERIC	0x0a00
#define PCI_CLASS_DOCKING_OTHER		0x0a01

#define PCI_BASE_CLASS_PROCESSOR	0x0b
#define PCI_CLASS_PROCESSOR_386		0x0b00
#define PCI_CLASS_PROCESSOR_486		0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
#define PCI_CLASS_PROCESSOR_CO		0x0b40

#define PCI_BASE_CLASS_SERIAL		0x0c
#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
#define PCI_CLASS_SERIAL_ACCESS		0x0c01
#define PCI_CLASS_SERIAL_SSA		0x0c02
#define PCI_CLASS_SERIAL_USB		0x0c03
#define PCI_CLASS_SERIAL_FIBER		0x0c04

#define PCI_CLASS_OTHERS		0xff

/* Several ID's we need in the library */

#define PCI_VENDOR_ID_INTEL		0x8086
#define PCI_VENDOR_ID_COMPAQ		0x0e11
Commit	Line	Data
d6b297d0	1	/*
a27a33dd	2	* $Id: header.h,v 1.8 2002/03/30 15:39:25 mj Exp $
d6b297d0 MM	3	*
	4	* The PCI Library -- PCI Header Structure (extracted from <linux/pci.h>)
	5	*
a27a33dd	6	* Copyright (c) 1997--2002 Martin Mares <mj@ucw.cz>
d6b297d0 MM	7	*
	8	* Can be freely distributed and used under the terms of the GNU GPL.
	9	*/
	10
	11	/*
	12	* Under PCI, each device has 256 bytes of configuration address space,
	13	* of which the first 64 bytes are standardized as follows:
	14	*/
	15	#define PCI_VENDOR_ID 0x00 /* 16 bits */
	16	#define PCI_DEVICE_ID 0x02 /* 16 bits */
	17	#define PCI_COMMAND 0x04 /* 16 bits */
	18	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	19	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
	20	#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
	21	#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
	22	#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
	23	#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
	24	#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
	25	#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
	26	#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
	27	#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
	28
	29	#define PCI_STATUS 0x06 /* 16 bits */
	30	#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
	31	#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
e95c8373	32	#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
d6b297d0 MM	33	#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
	34	#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
	35	#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
	36	#define PCI_STATUS_DEVSEL_FAST 0x000
	37	#define PCI_STATUS_DEVSEL_MEDIUM 0x200
	38	#define PCI_STATUS_DEVSEL_SLOW 0x400
	39	#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
	40	#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
	41	#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
	42	#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
	43	#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
	44
	45	#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
	46	revision */
	47	#define PCI_REVISION_ID 0x08 /* Revision ID */
	48	#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
	49	#define PCI_CLASS_DEVICE 0x0a /* Device class */
	50
	51	#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
	52	#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
	53	#define PCI_HEADER_TYPE 0x0e /* 8 bits */
	54	#define PCI_HEADER_TYPE_NORMAL 0
	55	#define PCI_HEADER_TYPE_BRIDGE 1
	56	#define PCI_HEADER_TYPE_CARDBUS 2
	57
	58	#define PCI_BIST 0x0f /* 8 bits */
	59	#define PCI_BIST_CODE_MASK 0x0f /* Return result */
	60	#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
	61	#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
	62
	63	/*
	64	* Base addresses specify locations in memory or I/O space.
	65	* Decoded size can be determined by writing a value of
	66	* 0xffffffff to the register, and reading it back. Only
	67	* 1 bits are decoded.
	68	*/
	69	#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
	70	#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
	71	#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
	72	#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
	73	#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
	74	#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
	75	#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
	76	#define PCI_BASE_ADDRESS_SPACE_IO 0x01
	77	#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
	78	#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
	79	#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
e95c8373	80	#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
d6b297d0 MM	81	#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
d6b297d0 MM	82	#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
e95c8373 MM	83	#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
e95c8373 MM	84	#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
d6b297d0 MM	85	/* bit 1 is reserved if address_space = 1 */
	86
	87	/* Header type 0 (normal devices) */
	88	#define PCI_CARDBUS_CIS 0x28
	89	#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
	90	#define PCI_SUBSYSTEM_ID 0x2e
	91	#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
	92	#define PCI_ROM_ADDRESS_ENABLE 0x01
	93	#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
	94
	95	#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
	96
	97	/* 0x35-0x3b are reserved */
	98	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
	99	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
	100	#define PCI_MIN_GNT 0x3e /* 8 bits */
	101	#define PCI_MAX_LAT 0x3f /* 8 bits */
	102
	103	/* Header type 1 (PCI-to-PCI bridges) */
	104	#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
	105	#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
	106	#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
	107	#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
	108	#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
	109	#define PCI_IO_LIMIT 0x1d
	110	#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
	111	#define PCI_IO_RANGE_TYPE_16 0x00
	112	#define PCI_IO_RANGE_TYPE_32 0x01
	113	#define PCI_IO_RANGE_MASK ~0x0f
	114	#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
	115	#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
	116	#define PCI_MEMORY_LIMIT 0x22
	117	#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
	118	#define PCI_MEMORY_RANGE_MASK ~0x0f
	119	#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
	120	#define PCI_PREF_MEMORY_LIMIT 0x26
	121	#define PCI_PREF_RANGE_TYPE_MASK 0x0f
	122	#define PCI_PREF_RANGE_TYPE_32 0x00
	123	#define PCI_PREF_RANGE_TYPE_64 0x01
	124	#define PCI_PREF_RANGE_MASK ~0x0f
	125	#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
	126	#define PCI_PREF_LIMIT_UPPER32 0x2c
	127	#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
	128	#define PCI_IO_LIMIT_UPPER16 0x32
e95c8373 MM	129	/* 0x34 same as for htype 0 */
e95c8373 MM	130	/* 0x35-0x3b is reserved */
d6b297d0 MM	131	#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
	132	/* 0x3c-0x3d are same as for htype 0 */
	133	#define PCI_BRIDGE_CONTROL 0x3e
	134	#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
	135	#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
	136	#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
	137	#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
	138	#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
	139	#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
	140	#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
	141
	142	/* Header type 2 (CardBus bridges) */
	143	/* 0x14-0x15 reserved */
	144	#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
	145	#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
	146	#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
	147	#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
	148	#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
	149	#define PCI_CB_MEMORY_BASE_0 0x1c
	150	#define PCI_CB_MEMORY_LIMIT_0 0x20
	151	#define PCI_CB_MEMORY_BASE_1 0x24
	152	#define PCI_CB_MEMORY_LIMIT_1 0x28
	153	#define PCI_CB_IO_BASE_0 0x2c
	154	#define PCI_CB_IO_BASE_0_HI 0x2e
	155	#define PCI_CB_IO_LIMIT_0 0x30
	156	#define PCI_CB_IO_LIMIT_0_HI 0x32
	157	#define PCI_CB_IO_BASE_1 0x34
	158	#define PCI_CB_IO_BASE_1_HI 0x36
	159	#define PCI_CB_IO_LIMIT_1 0x38
	160	#define PCI_CB_IO_LIMIT_1_HI 0x3a
	161	#define PCI_CB_IO_RANGE_MASK ~0x03
	162	/* 0x3c-0x3d are same as for htype 0 */
	163	#define PCI_CB_BRIDGE_CONTROL 0x3e
	164	#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
	165	#define PCI_CB_BRIDGE_CTL_SERR 0x02
	166	#define PCI_CB_BRIDGE_CTL_ISA 0x04
	167	#define PCI_CB_BRIDGE_CTL_VGA 0x08
	168	#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
	169	#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
	170	#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
	171	#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
	172	#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
	173	#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
	174	#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
	175	#define PCI_CB_SUBSYSTEM_ID 0x42
	176	#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
	177	/* 0x48-0x7f reserved */
	178
	179	/* Capability lists */
e95c8373	180
d6b297d0	181	#define PCI_CAP_LIST_ID 0 /* Capability ID */
1c31d620 MM	182	#define PCI_CAP_ID_PM 0x01 /* Power Management */
1c31d620 MM	183	#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
e95c8373 MM	184	#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
	185	#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
	186	#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
	187	#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
5f5e6f64	188	#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
d6b297d0	189	#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
1c31d620 MM	190	#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
	191	#define PCI_CAP_SIZEOF 4
	192
	193	/* Power Management Registers */
	194
72b9b690 MM	195	#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
	196	#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
	197	#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
	198	#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
1c31d620 MM	199	#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
1c31d620 MM	200	#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
72b9b690 MM	201	#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
	202	#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
	203	#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
	204	#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
	205	#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
1c31d620 MM	206	#define PCI_PM_CTRL 4 /* PM control and status register */
	207	#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
	208	#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
72b9b690 MM	209	#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
72b9b690 MM	210	#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
1c31d620	211	#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
72b9b690 MM	212	#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
	213	#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
	214	#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
	215	#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
1c31d620 MM	216	#define PCI_PM_SIZEOF 8
	217
	218	/* AGP registers */
	219
	220	#define PCI_AGP_VERSION 2 /* BCD version number */
	221	#define PCI_AGP_RFU 3 /* Rest of capability flags */
	222	#define PCI_AGP_STATUS 4 /* Status register */
	223	#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
	224	#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
	225	#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
	226	#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
	227	#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
	228	#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
	229	#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
	230	#define PCI_AGP_COMMAND 8 /* Control register */
	231	#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
	232	#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
	233	#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
	234	#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
	235	#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
	236	#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
81077814 MM	237	#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
81077814 MM	238	#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
1c31d620	239	#define PCI_AGP_SIZEOF 12
d6b297d0	240
e95c8373 MM	241	/* Slot Identification */
	242
	243	#define PCI_SID_ESR 2 /* Expansion Slot Register */
	244	#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
	245	#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
	246	#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
	247
	248	/* Message Signalled Interrupts registers */
	249
	250	#define PCI_MSI_FLAGS 2 /* Various flags */
	251	#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
	252	#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
	253	#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
	254	#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
	255	#define PCI_MSI_RFU 3 /* Rest of capability flags */
	256	#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
	257	#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
	258	#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
	259	#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
	260
5f5e6f64 MM	261	/* PCI-X */
	262	#define PCI_PCIX_COMMAND 2 /* Command register offset */
	263	#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
	264	#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
	265	#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
	266	#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
	267	#define PCI_PCIX_COMMAND_RESERVED 0xf80
	268	#define PCI_PCIX_STATUS 4 /* Status register offset */
	269	#define PCI_PCIX_STATUS_FUNCTION 0x00000007
	270	#define PCI_PCIX_STATUS_DEVICE 0x000000f8
	271	#define PCI_PCIX_STATUS_BUS 0x0000ff00
	272	#define PCI_PCIX_STATUS_64BIT 0x00010000
	273	#define PCI_PCIX_STATUS_133MHZ 0x00020000
	274	#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
	275	#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
	276	#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
	277	#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
	278	#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
	279	#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
	280	#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
	281	#define PCI_PCIX_STATUS_RESERVED 0xc0000000
	282	#define PCI_PCIX_SIZEOF 4
	283
	284	/* PCI-X Bridges */
	285	#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
	286	#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
	287	#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
	288	#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
	289	#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
	290	#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
	291	#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
	292	#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
	293	#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
	294	#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
	295	#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
	296	#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
	297	#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
	298	#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
	299	#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
	300	#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
	301	#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
	302	#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
	303	#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
	304	#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
	305	#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
	306	#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
	307	#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
	308	#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
	309	#define PCI_PCIX_BRIDGE_SIZEOF 12
	310
d6b297d0 MM	311	/*
	312	* The PCI interface treats multi-function devices as independent
	313	* devices. The slot/function address of each device is encoded
	314	* in a single byte as follows:
	315	*
	316	* 7:3 = slot
	317	* 2:0 = function
	318	*/
	319	#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) \| ((func) & 0x07))
	320	#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
	321	#define PCI_FUNC(devfn) ((devfn) & 0x07)
	322
	323	/* Device classes and subclasses */
	324
	325	#define PCI_CLASS_NOT_DEFINED 0x0000
	326	#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
	327
	328	#define PCI_BASE_CLASS_STORAGE 0x01
	329	#define PCI_CLASS_STORAGE_SCSI 0x0100
	330	#define PCI_CLASS_STORAGE_IDE 0x0101
	331	#define PCI_CLASS_STORAGE_FLOPPY 0x0102
	332	#define PCI_CLASS_STORAGE_IPI 0x0103
	333	#define PCI_CLASS_STORAGE_RAID 0x0104
	334	#define PCI_CLASS_STORAGE_OTHER 0x0180
	335
	336	#define PCI_BASE_CLASS_NETWORK 0x02
	337	#define PCI_CLASS_NETWORK_ETHERNET 0x0200
	338	#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
	339	#define PCI_CLASS_NETWORK_FDDI 0x0202
	340	#define PCI_CLASS_NETWORK_ATM 0x0203
	341	#define PCI_CLASS_NETWORK_OTHER 0x0280
	342
	343	#define PCI_BASE_CLASS_DISPLAY 0x03
	344	#define PCI_CLASS_DISPLAY_VGA 0x0300
	345	#define PCI_CLASS_DISPLAY_XGA 0x0301
	346	#define PCI_CLASS_DISPLAY_OTHER 0x0380
	347
	348	#define PCI_BASE_CLASS_MULTIMEDIA 0x04
	349	#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
	350	#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
	351	#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
	352
	353	#define PCI_BASE_CLASS_MEMORY 0x05
	354	#define PCI_CLASS_MEMORY_RAM 0x0500
	355	#define PCI_CLASS_MEMORY_FLASH 0x0501
	356	#define PCI_CLASS_MEMORY_OTHER 0x0580
	357
	358	#define PCI_BASE_CLASS_BRIDGE 0x06
	359	#define PCI_CLASS_BRIDGE_HOST 0x0600
	360	#define PCI_CLASS_BRIDGE_ISA 0x0601
	361	#define PCI_CLASS_BRIDGE_EISA 0x0602
	362	#define PCI_CLASS_BRIDGE_MC 0x0603
	363	#define PCI_CLASS_BRIDGE_PCI 0x0604
	364	#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
	365	#define PCI_CLASS_BRIDGE_NUBUS 0x0606
	366	#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
	367	#define PCI_CLASS_BRIDGE_OTHER 0x0680
	368
	369	#define PCI_BASE_CLASS_COMMUNICATION 0x07
	370	#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
	371	#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
	372	#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
	373
	374	#define PCI_BASE_CLASS_SYSTEM 0x08
375	#define PCI_CLASS_SYSTEM_PIC 0x0800
376	#define PCI_CLASS_SYSTEM_DMA 0x0801
377	#define PCI_CLASS_SYSTEM_TIMER 0x0802
378	#define PCI_CLASS_SYSTEM_RTC 0x0803
379	#define PCI_CLASS_SYSTEM_OTHER 0x0880
380
381	#define PCI_BASE_CLASS_INPUT 0x09
382	#define PCI_CLASS_INPUT_KEYBOARD 0x0900
383	#define PCI_CLASS_INPUT_PEN 0x0901
384	#define PCI_CLASS_INPUT_MOUSE 0x0902
385	#define PCI_CLASS_INPUT_OTHER 0x0980
386
387	#define PCI_BASE_CLASS_DOCKING 0x0a
388	#define PCI_CLASS_DOCKING_GENERIC 0x0a00
389	#define PCI_CLASS_DOCKING_OTHER 0x0a01
390
391	#define PCI_BASE_CLASS_PROCESSOR 0x0b
392	#define PCI_CLASS_PROCESSOR_386 0x0b00
393	#define PCI_CLASS_PROCESSOR_486 0x0b01
394	#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
395	#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
396	#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
397	#define PCI_CLASS_PROCESSOR_CO 0x0b40
398
399	#define PCI_BASE_CLASS_SERIAL 0x0c
400	#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
401	#define PCI_CLASS_SERIAL_ACCESS 0x0c01
402	#define PCI_CLASS_SERIAL_SSA 0x0c02
403	#define PCI_CLASS_SERIAL_USB 0x0c03
404	#define PCI_CLASS_SERIAL_FIBER 0x0c04
405
406	#define PCI_CLASS_OTHERS 0xff
407
408	/* Several ID's we need in the library */
409
410	#define PCI_VENDOR_ID_INTEL 0x8086
411	#define PCI_VENDOR_ID_COMPAQ 0x0e11