]>
Commit | Line | Data |
---|---|---|
9304f876 | 1 | /* c-isr library stuff of Andes NDS32 cpu for GNU compiler |
99dee823 | 2 | Copyright (C) 2012-2021 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | Under Section 7 of GPL version 3, you are granted additional | |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
24 | <http://www.gnu.org/licenses/>. */ | |
25 | ||
26 | .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ | |
27 | .align 1 | |
28 | .weak _SDA_BASE_ /* For reset handler only. */ | |
29 | .weak _FP_BASE_ /* For reset handler only. */ | |
30 | .weak _nds32_init_mem /* User defined memory initialization function. */ | |
31 | .globl _start | |
32 | .globl _nds32_reset_4b | |
33 | .type _nds32_reset_4b, @function | |
34 | _nds32_reset_4b: | |
35 | _start: | |
36 | #ifdef NDS32_EXT_EX9 | |
37 | .no_ex9_begin | |
38 | #endif | |
39 | /* Handle NMI and warm boot if any of them exists. */ | |
40 | beqz $sp, 1f /* Reset, NMI or warm boot? */ | |
41 | /* Either NMI or warm boot; save all regs. */ | |
42 | ||
43 | /* Preserve registers for context-switching. */ | |
44 | #ifdef __NDS32_REDUCED_REGS__ | |
45 | /* For 16-reg mode. */ | |
46 | smw.adm $r0, [$sp], $r10, #0x0 | |
47 | smw.adm $r15, [$sp], $r15, #0xf | |
48 | #else | |
49 | /* For 32-reg mode. */ | |
50 | smw.adm $r0, [$sp], $r27, #0xf | |
51 | #endif | |
52 | #ifdef NDS32_EXT_IFC | |
53 | mfusr $r1, $IFC_LP | |
54 | smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep | |
55 | stack 8-byte alignment. */ | |
56 | #endif | |
57 | ||
58 | la $gp, _SDA_BASE_ /* Init GP for small data access. */ | |
59 | move $r0, $sp /* Init parameter. */ | |
60 | mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */ | |
61 | andi $r1, $r1, #0xf | |
62 | addi $r1, $r1, #-1 | |
63 | beqz $r1, 2f /* Warm boot if true. */ | |
64 | l.w $r15, _nds32_nmih /* Load NMI handler. */ | |
65 | j 3f | |
66 | 2: | |
67 | l.w $r15, _nds32_wrh /* Load warm boot handler. */ | |
68 | 3: | |
69 | beqz $r15, 1f /* If no handler, do cold boot. */ | |
70 | jral $r15 /* Call handler. */ | |
71 | bnez $r0, 1f /* If fail to resume, do cold boot. */ | |
72 | ||
73 | /* Restore registers for context-switching. */ | |
74 | #ifdef NDS32_EXT_IFC | |
75 | lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep | |
76 | stack 8-byte alignment. */ | |
77 | mtusr $r1, $IFC_LP | |
78 | #endif | |
79 | #ifdef __NDS32_REDUCED_REGS__ | |
80 | /* For 16-reg mode. */ | |
81 | lmw.bim $r15, [$sp], $r15, #0xf | |
82 | lmw.bim $r0, [$sp], $r10, #0x0 | |
83 | #else | |
84 | /* For 32-reg mode. */ | |
85 | lmw.bim $r0, [$sp], $r27, #0xf | |
86 | #endif | |
87 | iret /* Resume operation. */ | |
88 | ||
89 | ||
90 | 1: /* Cold boot. */ | |
91 | /* With vector ID feature, set default vector size to 4B. */ | |
92 | /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ | |
93 | mfsr $r0, $IVB | |
94 | li $r1, #0xc000 | |
95 | or $r0, $r0, $r1 | |
96 | xor $r0, $r0, $r1 | |
97 | mtsr $r0, $IVB | |
98 | dsb | |
99 | ||
100 | la $gp, _SDA_BASE_ /* Init $gp. */ | |
101 | la $fp, _FP_BASE_ /* Init $fp. */ | |
102 | la $sp, _stack /* Init $sp. */ | |
103 | #ifdef NDS32_EXT_EX9 | |
104 | /* | |
105 | * Initialize the table base of EX9 instruction | |
106 | * ex9 generation needs to disable before the ITB is set | |
107 | */ | |
108 | mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ | |
109 | srli $r0, $r0, 24 | |
110 | andi $r0, $r0, 0x1 | |
111 | beqz $r0, 4f /* Zero means HW does not support EX9. */ | |
112 | la $r0, _ITB_BASE_ /* Init $ITB. */ | |
113 | mtusr $r0, $ITB | |
114 | .no_ex9_end | |
115 | 4: | |
116 | #endif | |
117 | la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem | |
118 | may written by C language. */ | |
119 | beqz $r15, 6f | |
120 | jral $r15 | |
121 | 6: | |
122 | l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ | |
123 | jral $r15 | |
124 | /* Reset handler() should never return in a RTOS or non-OS system. | |
125 | In case it does return, an exception will be generated. | |
126 | This exception will be caught either by default break handler or by EDM. | |
127 | Default break handle may just do an infinite loop. | |
128 | EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ | |
129 | 5: | |
130 | break #0x7fff | |
131 | .size _nds32_reset_4b, .-_nds32_reset_4b |