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Commit | Line | Data |
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c7a34993 MM |
1 | /* |
2 | * The PCI Utilities -- Show Capabilities | |
3 | * | |
b47b5bd4 | 4 | * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz> |
c7a34993 MM |
5 | * |
6 | * Can be freely distributed and used under the terms of the GNU GPL. | |
7 | */ | |
8 | ||
9 | #include <stdio.h> | |
10 | #include <string.h> | |
11 | ||
12 | #include "lspci.h" | |
13 | ||
14 | static void | |
15 | cap_pm(struct device *d, int where, int cap) | |
16 | { | |
17 | int t, b; | |
18 | static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 }; | |
19 | ||
20 | printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); | |
21 | if (verbose < 2) | |
22 | return; | |
23 | printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n", | |
24 | FLAG(cap, PCI_PM_CAP_PME_CLOCK), | |
25 | FLAG(cap, PCI_PM_CAP_DSI), | |
26 | FLAG(cap, PCI_PM_CAP_D1), | |
27 | FLAG(cap, PCI_PM_CAP_D2), | |
02d761b4 | 28 | pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6], |
c7a34993 MM |
29 | FLAG(cap, PCI_PM_CAP_PME_D0), |
30 | FLAG(cap, PCI_PM_CAP_PME_D1), | |
31 | FLAG(cap, PCI_PM_CAP_PME_D2), | |
32 | FLAG(cap, PCI_PM_CAP_PME_D3_HOT), | |
33 | FLAG(cap, PCI_PM_CAP_PME_D3_COLD)); | |
34 | if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL)) | |
35 | return; | |
36 | t = get_conf_word(d, where + PCI_PM_CTRL); | |
1c702fac | 37 | printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n", |
c7a34993 | 38 | t & PCI_PM_CTRL_STATE_MASK, |
1c702fac | 39 | FLAG(t, PCI_PM_CTRL_NO_SOFT_RST), |
c7a34993 MM |
40 | FLAG(t, PCI_PM_CTRL_PME_ENABLE), |
41 | (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9, | |
42 | (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13, | |
43 | FLAG(t, PCI_PM_CTRL_PME_STATUS)); | |
44 | b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS); | |
45 | if (b) | |
46 | printf("\t\tBridge: PM%c B3%c\n", | |
47 | FLAG(t, PCI_PM_BPCC_ENABLE), | |
48 | FLAG(~t, PCI_PM_PPB_B2_B3)); | |
49 | } | |
50 | ||
51 | static void | |
52 | format_agp_rate(int rate, char *buf, int agp3) | |
53 | { | |
54 | char *c = buf; | |
55 | int i; | |
56 | ||
57 | for (i=0; i<=2; i++) | |
58 | if (rate & (1 << i)) | |
59 | { | |
60 | if (c != buf) | |
61 | *c++ = ','; | |
62 | c += sprintf(c, "x%d", 1 << (i + 2*agp3)); | |
63 | } | |
64 | if (c != buf) | |
65 | *c = 0; | |
66 | else | |
67 | strcpy(buf, "<none>"); | |
68 | } | |
69 | ||
70 | static void | |
71 | cap_agp(struct device *d, int where, int cap) | |
72 | { | |
73 | u32 t; | |
74 | char rate[16]; | |
75 | int ver, rev; | |
76 | int agp3 = 0; | |
77 | ||
78 | ver = (cap >> 4) & 0x0f; | |
79 | rev = cap & 0x0f; | |
80 | printf("AGP version %x.%x\n", ver, rev); | |
81 | if (verbose < 2) | |
82 | return; | |
83 | if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS)) | |
84 | return; | |
85 | t = get_conf_long(d, where + PCI_AGP_STATUS); | |
86 | if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3)) | |
87 | agp3 = 1; | |
88 | format_agp_rate(t & 7, rate, agp3); | |
89 | printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n", | |
90 | ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1, | |
91 | FLAG(t, PCI_AGP_STATUS_ISOCH), | |
92 | ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13), | |
93 | ((t & PCI_AGP_STATUS_CAL_MASK) >> 10), | |
94 | FLAG(t, PCI_AGP_STATUS_SBA), | |
95 | FLAG(t, PCI_AGP_STATUS_ITA_COH), | |
96 | FLAG(t, PCI_AGP_STATUS_GART64), | |
97 | FLAG(t, PCI_AGP_STATUS_HTRANS), | |
98 | FLAG(t, PCI_AGP_STATUS_64BIT), | |
99 | FLAG(t, PCI_AGP_STATUS_FW), | |
100 | FLAG(t, PCI_AGP_STATUS_AGP3), | |
101 | rate); | |
102 | t = get_conf_long(d, where + PCI_AGP_COMMAND); | |
103 | format_agp_rate(t & 7, rate, agp3); | |
104 | printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n", | |
105 | ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1, | |
106 | ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13), | |
107 | ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10), | |
108 | FLAG(t, PCI_AGP_COMMAND_SBA), | |
109 | FLAG(t, PCI_AGP_COMMAND_AGP), | |
110 | FLAG(t, PCI_AGP_COMMAND_GART64), | |
111 | FLAG(t, PCI_AGP_COMMAND_64BIT), | |
112 | FLAG(t, PCI_AGP_COMMAND_FW), | |
113 | rate); | |
114 | } | |
115 | ||
116 | static void | |
117 | cap_pcix_nobridge(struct device *d, int where) | |
118 | { | |
119 | u16 command; | |
120 | u32 status; | |
121 | static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 }; | |
122 | ||
123 | printf("PCI-X non-bridge device\n"); | |
124 | ||
125 | if (verbose < 2) | |
126 | return; | |
127 | ||
128 | if (!config_fetch(d, where + PCI_PCIX_STATUS, 4)) | |
129 | return; | |
130 | ||
131 | command = get_conf_word(d, where + PCI_PCIX_COMMAND); | |
132 | status = get_conf_long(d, where + PCI_PCIX_STATUS); | |
133 | printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n", | |
134 | FLAG(command, PCI_PCIX_COMMAND_DPERE), | |
135 | FLAG(command, PCI_PCIX_COMMAND_ERO), | |
136 | 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)), | |
137 | max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]); | |
138 | printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n", | |
02d761b4 BH |
139 | (status & PCI_PCIX_STATUS_BUS) >> 8, |
140 | (status & PCI_PCIX_STATUS_DEVICE) >> 3, | |
c7a34993 MM |
141 | (status & PCI_PCIX_STATUS_FUNCTION), |
142 | FLAG(status, PCI_PCIX_STATUS_64BIT), | |
143 | FLAG(status, PCI_PCIX_STATUS_133MHZ), | |
144 | FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), | |
145 | FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), | |
146 | ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), | |
02d761b4 BH |
147 | 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)), |
148 | max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23], | |
149 | 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)), | |
c7a34993 MM |
150 | FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS), |
151 | FLAG(status, PCI_PCIX_STATUS_266MHZ), | |
152 | FLAG(status, PCI_PCIX_STATUS_533MHZ)); | |
153 | } | |
154 | ||
155 | static void | |
156 | cap_pcix_bridge(struct device *d, int where) | |
157 | { | |
158 | static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" }; | |
159 | u16 secstatus; | |
160 | u32 status, upstcr, downstcr; | |
161 | ||
162 | printf("PCI-X bridge device\n"); | |
163 | ||
164 | if (verbose < 2) | |
165 | return; | |
166 | ||
167 | if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12)) | |
168 | return; | |
169 | ||
170 | secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS); | |
171 | printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n", | |
172 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT), | |
173 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ), | |
174 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED), | |
175 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), | |
176 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), | |
177 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), | |
02d761b4 | 178 | sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]); |
c7a34993 MM |
179 | status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); |
180 | printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n", | |
02d761b4 BH |
181 | (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8, |
182 | (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3, | |
c7a34993 MM |
183 | (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), |
184 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), | |
185 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), | |
186 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED), | |
187 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC), | |
188 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN), | |
189 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED)); | |
190 | upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL); | |
191 | printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n", | |
192 | (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), | |
193 | (upstcr >> 16) & 0xffff); | |
194 | downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL); | |
195 | printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n", | |
196 | (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), | |
197 | (downstcr >> 16) & 0xffff); | |
198 | } | |
199 | ||
200 | static void | |
201 | cap_pcix(struct device *d, int where) | |
202 | { | |
203 | switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f) | |
204 | { | |
205 | case PCI_HEADER_TYPE_NORMAL: | |
206 | cap_pcix_nobridge(d, where); | |
207 | break; | |
208 | case PCI_HEADER_TYPE_BRIDGE: | |
209 | cap_pcix_bridge(d, where); | |
210 | break; | |
211 | } | |
212 | } | |
213 | ||
214 | static inline char * | |
215 | ht_link_width(unsigned width) | |
216 | { | |
217 | static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" }; | |
218 | return widths[width]; | |
219 | } | |
220 | ||
221 | static inline char * | |
222 | ht_link_freq(unsigned freq) | |
223 | { | |
224 | static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz", | |
225 | "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" }; | |
226 | return freqs[freq]; | |
227 | } | |
228 | ||
229 | static void | |
230 | cap_ht_pri(struct device *d, int where, int cmd) | |
231 | { | |
232 | u16 lctr0, lcnf0, lctr1, lcnf1, eh; | |
233 | u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn; | |
c7a34993 MM |
234 | |
235 | printf("HyperTransport: Slave or Primary Interface\n"); | |
236 | if (verbose < 2) | |
237 | return; | |
238 | ||
239 | if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0)) | |
240 | return; | |
241 | rid = get_conf_byte(d, where + PCI_HT_PRI_RID); | |
242 | if (rid < 0x22 && rid > 0x11) | |
243 | printf("\t\t!!! Possibly incomplete decoding\n"); | |
244 | ||
0089d489 | 245 | printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c", |
c7a34993 MM |
246 | (cmd & PCI_HT_PRI_CMD_BUID), |
247 | (cmd & PCI_HT_PRI_CMD_UC) >> 5, | |
248 | FLAG(cmd, PCI_HT_PRI_CMD_MH), | |
0089d489 | 249 | FLAG(cmd, PCI_HT_PRI_CMD_DD)); |
c7a34993 | 250 | if (rid >= 0x22) |
0089d489 MM |
251 | printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL)); |
252 | printf("\n"); | |
253 | ||
254 | lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0); | |
255 | printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x", | |
c7a34993 MM |
256 | FLAG(lctr0, PCI_HT_LCTR_CFLE), |
257 | FLAG(lctr0, PCI_HT_LCTR_CST), | |
258 | FLAG(lctr0, PCI_HT_LCTR_CFE), | |
259 | FLAG(lctr0, PCI_HT_LCTR_LKFAIL), | |
260 | FLAG(lctr0, PCI_HT_LCTR_INIT), | |
261 | FLAG(lctr0, PCI_HT_LCTR_EOC), | |
262 | FLAG(lctr0, PCI_HT_LCTR_TXO), | |
0089d489 | 263 | (lctr0 & PCI_HT_LCTR_CRCERR) >> 8); |
c7a34993 | 264 | if (rid >= 0x22) |
0089d489 MM |
265 | printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", |
266 | FLAG(lctr0, PCI_HT_LCTR_ISOCEN), | |
267 | FLAG(lctr0, PCI_HT_LCTR_LSEN), | |
268 | FLAG(lctr0, PCI_HT_LCTR_EXTCTL), | |
269 | FLAG(lctr0, PCI_HT_LCTR_64B)); | |
270 | printf("\n"); | |
271 | ||
272 | lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); | |
273 | if (rid < 0x22) | |
274 | printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", | |
275 | ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), | |
276 | ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), | |
277 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), | |
278 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12)); | |
c7a34993 | 279 | else |
0089d489 MM |
280 | printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", |
281 | ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), | |
282 | FLAG(lcnf0, PCI_HT_LCNF_DFI), | |
283 | ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), | |
284 | FLAG(lcnf0, PCI_HT_LCNF_DFO), | |
285 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), | |
286 | FLAG(lcnf0, PCI_HT_LCNF_DFIE), | |
287 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), | |
288 | FLAG(lcnf0, PCI_HT_LCNF_DFOE)); | |
289 | ||
c7a34993 | 290 | lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1); |
0089d489 | 291 | printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x", |
c7a34993 MM |
292 | FLAG(lctr1, PCI_HT_LCTR_CFLE), |
293 | FLAG(lctr1, PCI_HT_LCTR_CST), | |
294 | FLAG(lctr1, PCI_HT_LCTR_CFE), | |
295 | FLAG(lctr1, PCI_HT_LCTR_LKFAIL), | |
296 | FLAG(lctr1, PCI_HT_LCTR_INIT), | |
297 | FLAG(lctr1, PCI_HT_LCTR_EOC), | |
298 | FLAG(lctr1, PCI_HT_LCTR_TXO), | |
0089d489 MM |
299 | (lctr1 & PCI_HT_LCTR_CRCERR) >> 8); |
300 | if (rid >= 0x22) | |
301 | printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", | |
c7a34993 MM |
302 | FLAG(lctr1, PCI_HT_LCTR_ISOCEN), |
303 | FLAG(lctr1, PCI_HT_LCTR_LSEN), | |
304 | FLAG(lctr1, PCI_HT_LCTR_EXTCTL), | |
305 | FLAG(lctr1, PCI_HT_LCTR_64B)); | |
0089d489 MM |
306 | printf("\n"); |
307 | ||
c7a34993 | 308 | lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1); |
0089d489 MM |
309 | if (rid < 0x22) |
310 | printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", | |
311 | ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), | |
312 | ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), | |
313 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), | |
314 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12)); | |
c7a34993 | 315 | else |
0089d489 MM |
316 | printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", |
317 | ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), | |
318 | FLAG(lcnf1, PCI_HT_LCNF_DFI), | |
319 | ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), | |
320 | FLAG(lcnf1, PCI_HT_LCNF_DFO), | |
321 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), | |
322 | FLAG(lcnf1, PCI_HT_LCNF_DFIE), | |
323 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), | |
324 | FLAG(lcnf1, PCI_HT_LCNF_DFOE)); | |
325 | ||
c7a34993 MM |
326 | printf("\t\tRevision ID: %u.%02u\n", |
327 | (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); | |
328 | if (rid < 0x22) | |
329 | return; | |
0089d489 | 330 | |
c7a34993 MM |
331 | lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0); |
332 | printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ)); | |
333 | printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
334 | FLAG(lfrer0, PCI_HT_LFRER_PROT), | |
335 | FLAG(lfrer0, PCI_HT_LFRER_OV), | |
336 | FLAG(lfrer0, PCI_HT_LFRER_EOC), | |
337 | FLAG(lfrer0, PCI_HT_LFRER_CTLT)); | |
0089d489 | 338 | |
c7a34993 MM |
339 | lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0); |
340 | printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
341 | FLAG(lfcap0, PCI_HT_LFCAP_200), | |
342 | FLAG(lfcap0, PCI_HT_LFCAP_300), | |
343 | FLAG(lfcap0, PCI_HT_LFCAP_400), | |
344 | FLAG(lfcap0, PCI_HT_LFCAP_500), | |
345 | FLAG(lfcap0, PCI_HT_LFCAP_600), | |
346 | FLAG(lfcap0, PCI_HT_LFCAP_800), | |
347 | FLAG(lfcap0, PCI_HT_LFCAP_1000), | |
348 | FLAG(lfcap0, PCI_HT_LFCAP_1200), | |
349 | FLAG(lfcap0, PCI_HT_LFCAP_1400), | |
350 | FLAG(lfcap0, PCI_HT_LFCAP_1600), | |
351 | FLAG(lfcap0, PCI_HT_LFCAP_VEND)); | |
0089d489 | 352 | |
c7a34993 MM |
353 | ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR); |
354 | printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n", | |
355 | FLAG(ftr, PCI_HT_FTR_ISOCFC), | |
356 | FLAG(ftr, PCI_HT_FTR_LDTSTOP), | |
357 | FLAG(ftr, PCI_HT_FTR_CRCTM), | |
358 | FLAG(ftr, PCI_HT_FTR_ECTLT), | |
359 | FLAG(ftr, PCI_HT_FTR_64BA), | |
360 | FLAG(ftr, PCI_HT_FTR_UIDRD)); | |
0089d489 | 361 | |
c7a34993 MM |
362 | lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1); |
363 | printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ)); | |
364 | printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
365 | FLAG(lfrer1, PCI_HT_LFRER_PROT), | |
366 | FLAG(lfrer1, PCI_HT_LFRER_OV), | |
367 | FLAG(lfrer1, PCI_HT_LFRER_EOC), | |
368 | FLAG(lfrer1, PCI_HT_LFRER_CTLT)); | |
0089d489 | 369 | |
c7a34993 MM |
370 | lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1); |
371 | printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
372 | FLAG(lfcap1, PCI_HT_LFCAP_200), | |
373 | FLAG(lfcap1, PCI_HT_LFCAP_300), | |
374 | FLAG(lfcap1, PCI_HT_LFCAP_400), | |
375 | FLAG(lfcap1, PCI_HT_LFCAP_500), | |
376 | FLAG(lfcap1, PCI_HT_LFCAP_600), | |
377 | FLAG(lfcap1, PCI_HT_LFCAP_800), | |
378 | FLAG(lfcap1, PCI_HT_LFCAP_1000), | |
379 | FLAG(lfcap1, PCI_HT_LFCAP_1200), | |
380 | FLAG(lfcap1, PCI_HT_LFCAP_1400), | |
381 | FLAG(lfcap1, PCI_HT_LFCAP_1600), | |
382 | FLAG(lfcap1, PCI_HT_LFCAP_VEND)); | |
0089d489 | 383 | |
c7a34993 MM |
384 | eh = get_conf_word(d, where + PCI_HT_PRI_EH); |
385 | printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n", | |
386 | FLAG(eh, PCI_HT_EH_PFLE), | |
387 | FLAG(eh, PCI_HT_EH_OFLE), | |
388 | FLAG(eh, PCI_HT_EH_PFE), | |
389 | FLAG(eh, PCI_HT_EH_OFE), | |
390 | FLAG(eh, PCI_HT_EH_EOCFE), | |
391 | FLAG(eh, PCI_HT_EH_RFE), | |
392 | FLAG(eh, PCI_HT_EH_CRCFE), | |
393 | FLAG(eh, PCI_HT_EH_SERRFE), | |
394 | FLAG(eh, PCI_HT_EH_CF), | |
395 | FLAG(eh, PCI_HT_EH_RE), | |
396 | FLAG(eh, PCI_HT_EH_PNFE), | |
397 | FLAG(eh, PCI_HT_EH_ONFE), | |
398 | FLAG(eh, PCI_HT_EH_EOCNFE), | |
399 | FLAG(eh, PCI_HT_EH_RNFE), | |
400 | FLAG(eh, PCI_HT_EH_CRCNFE), | |
401 | FLAG(eh, PCI_HT_EH_SERRNFE)); | |
0089d489 | 402 | |
c7a34993 MM |
403 | mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU); |
404 | mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU); | |
405 | printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu); | |
0089d489 | 406 | |
c7a34993 MM |
407 | bn = get_conf_byte(d, where + PCI_HT_PRI_BN); |
408 | printf("\t\tBus Number: %02x\n", bn); | |
409 | } | |
410 | ||
411 | static void | |
412 | cap_ht_sec(struct device *d, int where, int cmd) | |
413 | { | |
414 | u16 lctr, lcnf, ftr, eh; | |
415 | u8 rid, lfrer, lfcap, mbu, mlu; | |
416 | char *fmt; | |
417 | ||
418 | printf("HyperTransport: Host or Secondary Interface\n"); | |
419 | if (verbose < 2) | |
420 | return; | |
421 | ||
422 | if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR)) | |
423 | return; | |
424 | rid = get_conf_byte(d, where + PCI_HT_SEC_RID); | |
425 | if (rid < 0x22 && rid > 0x11) | |
426 | printf("\t\t!!! Possibly incomplete decoding\n"); | |
427 | ||
428 | if (rid >= 0x22) | |
429 | fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n"; | |
430 | else | |
431 | fmt = "\t\tCommand: WarmRst%c DblEnd%c\n"; | |
432 | printf(fmt, | |
433 | FLAG(cmd, PCI_HT_SEC_CMD_WR), | |
434 | FLAG(cmd, PCI_HT_SEC_CMD_DE), | |
435 | (cmd & PCI_HT_SEC_CMD_DN) >> 2, | |
436 | FLAG(cmd, PCI_HT_SEC_CMD_CS), | |
437 | FLAG(cmd, PCI_HT_SEC_CMD_HH), | |
438 | FLAG(cmd, PCI_HT_SEC_CMD_AS), | |
439 | FLAG(cmd, PCI_HT_SEC_CMD_HIECE), | |
440 | FLAG(cmd, PCI_HT_SEC_CMD_DUL)); | |
441 | lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR); | |
442 | if (rid >= 0x22) | |
443 | fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n"; | |
444 | else | |
445 | fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n"; | |
446 | printf(fmt, | |
447 | FLAG(lctr, PCI_HT_LCTR_CFLE), | |
448 | FLAG(lctr, PCI_HT_LCTR_CST), | |
449 | FLAG(lctr, PCI_HT_LCTR_CFE), | |
450 | FLAG(lctr, PCI_HT_LCTR_LKFAIL), | |
451 | FLAG(lctr, PCI_HT_LCTR_INIT), | |
452 | FLAG(lctr, PCI_HT_LCTR_EOC), | |
453 | FLAG(lctr, PCI_HT_LCTR_TXO), | |
454 | (lctr & PCI_HT_LCTR_CRCERR) >> 8, | |
455 | FLAG(lctr, PCI_HT_LCTR_ISOCEN), | |
456 | FLAG(lctr, PCI_HT_LCTR_LSEN), | |
457 | FLAG(lctr, PCI_HT_LCTR_EXTCTL), | |
458 | FLAG(lctr, PCI_HT_LCTR_64B)); | |
459 | lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF); | |
460 | if (rid >= 0x22) | |
461 | fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; | |
462 | else | |
463 | fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; | |
464 | printf(fmt, | |
465 | ht_link_width(lcnf & PCI_HT_LCNF_MLWI), | |
466 | ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4), | |
467 | ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8), | |
468 | ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12), | |
469 | FLAG(lcnf, PCI_HT_LCNF_DFI), | |
470 | FLAG(lcnf, PCI_HT_LCNF_DFO), | |
471 | FLAG(lcnf, PCI_HT_LCNF_DFIE), | |
472 | FLAG(lcnf, PCI_HT_LCNF_DFOE)); | |
473 | printf("\t\tRevision ID: %u.%02u\n", | |
474 | (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); | |
475 | if (rid < 0x22) | |
476 | return; | |
477 | lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER); | |
478 | printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ)); | |
479 | printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
480 | FLAG(lfrer, PCI_HT_LFRER_PROT), | |
481 | FLAG(lfrer, PCI_HT_LFRER_OV), | |
482 | FLAG(lfrer, PCI_HT_LFRER_EOC), | |
483 | FLAG(lfrer, PCI_HT_LFRER_CTLT)); | |
484 | lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP); | |
485 | printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
486 | FLAG(lfcap, PCI_HT_LFCAP_200), | |
487 | FLAG(lfcap, PCI_HT_LFCAP_300), | |
488 | FLAG(lfcap, PCI_HT_LFCAP_400), | |
489 | FLAG(lfcap, PCI_HT_LFCAP_500), | |
490 | FLAG(lfcap, PCI_HT_LFCAP_600), | |
491 | FLAG(lfcap, PCI_HT_LFCAP_800), | |
492 | FLAG(lfcap, PCI_HT_LFCAP_1000), | |
493 | FLAG(lfcap, PCI_HT_LFCAP_1200), | |
494 | FLAG(lfcap, PCI_HT_LFCAP_1400), | |
495 | FLAG(lfcap, PCI_HT_LFCAP_1600), | |
496 | FLAG(lfcap, PCI_HT_LFCAP_VEND)); | |
497 | ftr = get_conf_word(d, where + PCI_HT_SEC_FTR); | |
498 | printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n", | |
499 | FLAG(ftr, PCI_HT_FTR_ISOCFC), | |
500 | FLAG(ftr, PCI_HT_FTR_LDTSTOP), | |
501 | FLAG(ftr, PCI_HT_FTR_CRCTM), | |
502 | FLAG(ftr, PCI_HT_FTR_ECTLT), | |
503 | FLAG(ftr, PCI_HT_FTR_64BA), | |
504 | FLAG(ftr, PCI_HT_FTR_UIDRD), | |
505 | FLAG(ftr, PCI_HT_SEC_FTR_EXTRS), | |
506 | FLAG(ftr, PCI_HT_SEC_FTR_UCNFE)); | |
507 | if (ftr & PCI_HT_SEC_FTR_EXTRS) | |
508 | { | |
509 | eh = get_conf_word(d, where + PCI_HT_SEC_EH); | |
510 | printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n", | |
511 | FLAG(eh, PCI_HT_EH_PFLE), | |
512 | FLAG(eh, PCI_HT_EH_OFLE), | |
513 | FLAG(eh, PCI_HT_EH_PFE), | |
514 | FLAG(eh, PCI_HT_EH_OFE), | |
515 | FLAG(eh, PCI_HT_EH_EOCFE), | |
516 | FLAG(eh, PCI_HT_EH_RFE), | |
517 | FLAG(eh, PCI_HT_EH_CRCFE), | |
518 | FLAG(eh, PCI_HT_EH_SERRFE), | |
519 | FLAG(eh, PCI_HT_EH_CF), | |
520 | FLAG(eh, PCI_HT_EH_RE), | |
521 | FLAG(eh, PCI_HT_EH_PNFE), | |
522 | FLAG(eh, PCI_HT_EH_ONFE), | |
523 | FLAG(eh, PCI_HT_EH_EOCNFE), | |
524 | FLAG(eh, PCI_HT_EH_RNFE), | |
525 | FLAG(eh, PCI_HT_EH_CRCNFE), | |
526 | FLAG(eh, PCI_HT_EH_SERRNFE)); | |
527 | mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU); | |
528 | mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU); | |
529 | printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu); | |
530 | } | |
531 | } | |
532 | ||
533 | static void | |
534 | cap_ht(struct device *d, int where, int cmd) | |
535 | { | |
536 | int type; | |
537 | ||
538 | switch (cmd & PCI_HT_CMD_TYP_HI) | |
539 | { | |
540 | case PCI_HT_CMD_TYP_HI_PRI: | |
541 | cap_ht_pri(d, where, cmd); | |
542 | return; | |
543 | case PCI_HT_CMD_TYP_HI_SEC: | |
544 | cap_ht_sec(d, where, cmd); | |
545 | return; | |
546 | } | |
547 | ||
548 | type = cmd & PCI_HT_CMD_TYP; | |
549 | switch (type) | |
550 | { | |
551 | case PCI_HT_CMD_TYP_SW: | |
552 | printf("HyperTransport: Switch\n"); | |
553 | break; | |
554 | case PCI_HT_CMD_TYP_IDC: | |
555 | printf("HyperTransport: Interrupt Discovery and Configuration\n"); | |
556 | break; | |
557 | case PCI_HT_CMD_TYP_RID: | |
558 | printf("HyperTransport: Revision ID: %u.%02u\n", | |
559 | (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN)); | |
560 | break; | |
561 | case PCI_HT_CMD_TYP_UIDC: | |
562 | printf("HyperTransport: UnitID Clumping\n"); | |
563 | break; | |
564 | case PCI_HT_CMD_TYP_ECSA: | |
565 | printf("HyperTransport: Extended Configuration Space Access\n"); | |
566 | break; | |
567 | case PCI_HT_CMD_TYP_AM: | |
568 | printf("HyperTransport: Address Mapping\n"); | |
569 | break; | |
570 | case PCI_HT_CMD_TYP_MSIM: | |
571 | printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n", | |
572 | FLAG(cmd, PCI_HT_MSIM_CMD_EN), | |
573 | FLAG(cmd, PCI_HT_MSIM_CMD_FIXD)); | |
574 | if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD)) | |
575 | { | |
576 | u32 offl, offh; | |
577 | if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8)) | |
578 | break; | |
579 | offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO); | |
580 | offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI); | |
581 | printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff)); | |
582 | } | |
583 | break; | |
584 | case PCI_HT_CMD_TYP_DR: | |
585 | printf("HyperTransport: DirectRoute\n"); | |
586 | break; | |
587 | case PCI_HT_CMD_TYP_VCS: | |
588 | printf("HyperTransport: VCSet\n"); | |
589 | break; | |
590 | case PCI_HT_CMD_TYP_RM: | |
591 | printf("HyperTransport: Retry Mode\n"); | |
592 | break; | |
593 | case PCI_HT_CMD_TYP_X86: | |
594 | printf("HyperTransport: X86 (reserved)\n"); | |
595 | break; | |
596 | default: | |
597 | printf("HyperTransport: #%02x\n", type >> 11); | |
598 | } | |
599 | } | |
600 | ||
601 | static void | |
602 | cap_msi(struct device *d, int where, int cap) | |
603 | { | |
604 | int is64; | |
605 | u32 t; | |
606 | u16 w; | |
607 | ||
04885ef7 MW |
608 | printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n", |
609 | FLAG(cap, PCI_MSI_FLAGS_ENABLE), | |
c7a34993 MM |
610 | 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4), |
611 | 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1), | |
04885ef7 MW |
612 | FLAG(cap, PCI_MSI_FLAGS_MASK_BIT), |
613 | FLAG(cap, PCI_MSI_FLAGS_64BIT)); | |
c7a34993 MM |
614 | if (verbose < 2) |
615 | return; | |
616 | is64 = cap & PCI_MSI_FLAGS_64BIT; | |
617 | if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO)) | |
618 | return; | |
619 | printf("\t\tAddress: "); | |
620 | if (is64) | |
621 | { | |
622 | t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI); | |
623 | w = get_conf_word(d, where + PCI_MSI_DATA_64); | |
624 | printf("%08x", t); | |
625 | } | |
626 | else | |
627 | w = get_conf_word(d, where + PCI_MSI_DATA_32); | |
628 | t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO); | |
629 | printf("%08x Data: %04x\n", t, w); | |
630 | if (cap & PCI_MSI_FLAGS_MASK_BIT) | |
631 | { | |
632 | u32 mask, pending; | |
633 | ||
634 | if (is64) | |
635 | { | |
636 | if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8)) | |
637 | return; | |
638 | mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64); | |
639 | pending = get_conf_long(d, where + PCI_MSI_PENDING_64); | |
640 | } | |
641 | else | |
642 | { | |
643 | if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8)) | |
644 | return; | |
645 | mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32); | |
646 | pending = get_conf_long(d, where + PCI_MSI_PENDING_32); | |
647 | } | |
648 | printf("\t\tMasking: %08x Pending: %08x\n", mask, pending); | |
649 | } | |
650 | } | |
651 | ||
623ed0e1 BH |
652 | static int exp_downstream_port(int type) |
653 | { | |
654 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
655 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
656 | type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */ | |
657 | } | |
658 | ||
c7a34993 MM |
659 | static float power_limit(int value, int scale) |
660 | { | |
661 | static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 }; | |
662 | return value * scales[scale]; | |
663 | } | |
664 | ||
665 | static const char *latency_l0s(int value) | |
666 | { | |
667 | static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" }; | |
668 | return latencies[value]; | |
669 | } | |
670 | ||
671 | static const char *latency_l1(int value) | |
672 | { | |
673 | static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" }; | |
674 | return latencies[value]; | |
675 | } | |
676 | ||
677 | static void cap_express_dev(struct device *d, int where, int type) | |
678 | { | |
679 | u32 t; | |
680 | u16 w; | |
681 | ||
682 | t = get_conf_long(d, where + PCI_EXP_DEVCAP); | |
0dc85d67 | 683 | printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d", |
c7a34993 | 684 | 128 << (t & PCI_EXP_DEVCAP_PAYLOAD), |
0dc85d67 BH |
685 | (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1); |
686 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) | |
687 | printf(", Latency L0s %s, L1 %s", | |
c7a34993 MM |
688 | latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6), |
689 | latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9)); | |
0dc85d67 | 690 | printf("\n"); |
c7a34993 MM |
691 | printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG)); |
692 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || | |
693 | (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) | |
694 | printf(" AttnBtn%c AttnInd%c PwrInd%c", | |
695 | FLAG(t, PCI_EXP_DEVCAP_ATN_BUT), | |
696 | FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND)); | |
5d602ff4 BH |
697 | printf(" RBE%c", |
698 | FLAG(t, PCI_EXP_DEVCAP_RBE)); | |
10168b84 | 699 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) |
5d602ff4 | 700 | printf(" FLReset%c", |
c7a34993 | 701 | FLAG(t, PCI_EXP_DEVCAP_FLRESET)); |
acf56dd2 BH |
702 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || |
703 | (type == PCI_EXP_TYPE_PCI_BRIDGE)) | |
5d602ff4 | 704 | printf(" SlotPowerLimit %.3fW", |
c7a34993 MM |
705 | power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, |
706 | (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); | |
707 | printf("\n"); | |
708 | ||
709 | w = get_conf_word(d, where + PCI_EXP_DEVCTL); | |
aca48104 | 710 | printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n", |
c7a34993 MM |
711 | FLAG(w, PCI_EXP_DEVCTL_CERE), |
712 | FLAG(w, PCI_EXP_DEVCTL_NFERE), | |
713 | FLAG(w, PCI_EXP_DEVCTL_FERE), | |
714 | FLAG(w, PCI_EXP_DEVCTL_URRE)); | |
715 | printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c", | |
716 | FLAG(w, PCI_EXP_DEVCTL_RELAXED), | |
717 | FLAG(w, PCI_EXP_DEVCTL_EXT_TAG), | |
718 | FLAG(w, PCI_EXP_DEVCTL_PHANTOM), | |
719 | FLAG(w, PCI_EXP_DEVCTL_AUX_PME), | |
720 | FLAG(w, PCI_EXP_DEVCTL_NOSNOOP)); | |
77120d53 | 721 | if (type == PCI_EXP_TYPE_PCI_BRIDGE) |
c7a34993 | 722 | printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE)); |
10168b84 | 723 | if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) && |
5d602ff4 | 724 | (t & PCI_EXP_DEVCAP_FLRESET)) |
c7a34993 MM |
725 | printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET)); |
726 | printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n", | |
727 | 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5), | |
728 | 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12)); | |
729 | ||
730 | w = get_conf_word(d, where + PCI_EXP_DEVSTA); | |
aca48104 | 731 | printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n", |
c7a34993 MM |
732 | FLAG(w, PCI_EXP_DEVSTA_CED), |
733 | FLAG(w, PCI_EXP_DEVSTA_NFED), | |
734 | FLAG(w, PCI_EXP_DEVSTA_FED), | |
735 | FLAG(w, PCI_EXP_DEVSTA_URD), | |
736 | FLAG(w, PCI_EXP_DEVSTA_AUXPD), | |
737 | FLAG(w, PCI_EXP_DEVSTA_TRPND)); | |
738 | } | |
739 | ||
740 | static char *link_speed(int speed) | |
741 | { | |
742 | switch (speed) | |
743 | { | |
744 | case 1: | |
745 | return "2.5GT/s"; | |
746 | case 2: | |
747 | return "5GT/s"; | |
4dc4ff43 MM |
748 | case 3: |
749 | return "8GT/s"; | |
9628600b GS |
750 | case 4: |
751 | return "16GT/s"; | |
caca31a0 GP |
752 | case 5: |
753 | return "32GT/s"; | |
5bdf63b6 GP |
754 | case 6: |
755 | return "64GT/s"; | |
c7a34993 MM |
756 | default: |
757 | return "unknown"; | |
758 | } | |
759 | } | |
760 | ||
b47b5bd4 MM |
761 | static char *link_compare(int sta, int cap) |
762 | { | |
763 | if (sta < cap) | |
764 | return "downgraded"; | |
765 | if (sta > cap) | |
766 | return "strange"; | |
767 | return "ok"; | |
768 | } | |
769 | ||
c7a34993 MM |
770 | static char *aspm_support(int code) |
771 | { | |
772 | switch (code) | |
773 | { | |
87bc7e64 BH |
774 | case 0: |
775 | return "not supported"; | |
c7a34993 MM |
776 | case 1: |
777 | return "L0s"; | |
4dc4ff43 MM |
778 | case 2: |
779 | return "L1"; | |
c7a34993 MM |
780 | case 3: |
781 | return "L0s L1"; | |
782 | default: | |
783 | return "unknown"; | |
784 | } | |
785 | } | |
786 | ||
787 | static const char *aspm_enabled(int code) | |
788 | { | |
789 | static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" }; | |
790 | return desc[code]; | |
791 | } | |
792 | ||
793 | static void cap_express_link(struct device *d, int where, int type) | |
794 | { | |
b47b5bd4 | 795 | u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width; |
c7a34993 MM |
796 | u16 w; |
797 | ||
798 | t = get_conf_long(d, where + PCI_EXP_LNKCAP); | |
78996f1c | 799 | aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10; |
b47b5bd4 MM |
800 | cap_speed = t & PCI_EXP_LNKCAP_SPEED; |
801 | cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4; | |
78996f1c | 802 | printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s", |
c7a34993 | 803 | t >> 24, |
b47b5bd4 | 804 | link_speed(cap_speed), cap_width, |
78996f1c BH |
805 | aspm_support(aspm)); |
806 | if (aspm) | |
807 | { | |
808 | printf(", Exit Latency "); | |
809 | if (aspm & 1) | |
810 | printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12)); | |
811 | if (aspm & 2) | |
812 | printf("%sL1 %s", (aspm & 1) ? ", " : "", | |
813 | latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); | |
814 | } | |
815 | printf("\n"); | |
b7a807b4 | 816 | printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n", |
c7a34993 MM |
817 | FLAG(t, PCI_EXP_LNKCAP_CLOCKPM), |
818 | FLAG(t, PCI_EXP_LNKCAP_SURPRISE), | |
819 | FLAG(t, PCI_EXP_LNKCAP_DLLA), | |
b7a807b4 MM |
820 | FLAG(t, PCI_EXP_LNKCAP_LBNC), |
821 | FLAG(t, PCI_EXP_LNKCAP_AOC)); | |
c7a34993 MM |
822 | |
823 | w = get_conf_word(d, where + PCI_EXP_LNKCTL); | |
824 | printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); | |
825 | if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || | |
a1f57a29 | 826 | (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) |
018f413c | 827 | printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); |
8ad3c8cf | 828 | printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", |
c7a34993 | 829 | FLAG(w, PCI_EXP_LNKCTL_DISABLE), |
c7a34993 MM |
830 | FLAG(w, PCI_EXP_LNKCTL_CLOCK), |
831 | FLAG(w, PCI_EXP_LNKCTL_XSYNCH), | |
832 | FLAG(w, PCI_EXP_LNKCTL_CLOCKPM), | |
833 | FLAG(w, PCI_EXP_LNKCTL_HWAUTWD), | |
834 | FLAG(w, PCI_EXP_LNKCTL_BWMIE), | |
835 | FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); | |
836 | ||
837 | w = get_conf_word(d, where + PCI_EXP_LNKSTA); | |
b47b5bd4 MM |
838 | sta_speed = w & PCI_EXP_LNKSTA_SPEED; |
839 | sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; | |
840 | printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n", | |
841 | link_speed(sta_speed), | |
842 | link_compare(sta_speed, cap_speed), | |
843 | sta_width, | |
844 | link_compare(sta_width, cap_width)); | |
845 | printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", | |
c7a34993 MM |
846 | FLAG(w, PCI_EXP_LNKSTA_TR_ERR), |
847 | FLAG(w, PCI_EXP_LNKSTA_TRAIN), | |
848 | FLAG(w, PCI_EXP_LNKSTA_SL_CLK), | |
849 | FLAG(w, PCI_EXP_LNKSTA_DL_ACT), | |
850 | FLAG(w, PCI_EXP_LNKSTA_BWMGMT), | |
851 | FLAG(w, PCI_EXP_LNKSTA_AUTBW)); | |
852 | } | |
853 | ||
854 | static const char *indicator(int code) | |
855 | { | |
856 | static const char *names[] = { "Unknown", "On", "Blink", "Off" }; | |
857 | return names[code]; | |
858 | } | |
859 | ||
860 | static void cap_express_slot(struct device *d, int where) | |
861 | { | |
862 | u32 t; | |
863 | u16 w; | |
864 | ||
865 | t = get_conf_long(d, where + PCI_EXP_SLTCAP); | |
5f6aca18 | 866 | printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n", |
c7a34993 MM |
867 | FLAG(t, PCI_EXP_SLTCAP_ATNB), |
868 | FLAG(t, PCI_EXP_SLTCAP_PWRC), | |
869 | FLAG(t, PCI_EXP_SLTCAP_MRL), | |
870 | FLAG(t, PCI_EXP_SLTCAP_ATNI), | |
871 | FLAG(t, PCI_EXP_SLTCAP_PWRI), | |
872 | FLAG(t, PCI_EXP_SLTCAP_HPC), | |
873 | FLAG(t, PCI_EXP_SLTCAP_HPS)); | |
a242f574 | 874 | printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n", |
02d761b4 | 875 | (t & PCI_EXP_SLTCAP_PSN) >> 19, |
c7a34993 MM |
876 | power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15), |
877 | FLAG(t, PCI_EXP_SLTCAP_INTERLOCK), | |
878 | FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP)); | |
879 | ||
880 | w = get_conf_word(d, where + PCI_EXP_SLTCTL); | |
881 | printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n", | |
882 | FLAG(w, PCI_EXP_SLTCTL_ATNB), | |
883 | FLAG(w, PCI_EXP_SLTCTL_PWRF), | |
884 | FLAG(w, PCI_EXP_SLTCTL_MRLS), | |
885 | FLAG(w, PCI_EXP_SLTCTL_PRSD), | |
886 | FLAG(w, PCI_EXP_SLTCTL_CMDC), | |
887 | FLAG(w, PCI_EXP_SLTCTL_HPIE), | |
888 | FLAG(w, PCI_EXP_SLTCTL_LLCHG)); | |
889 | printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n", | |
890 | indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6), | |
891 | indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8), | |
892 | FLAG(w, PCI_EXP_SLTCTL_PWRC), | |
893 | FLAG(w, PCI_EXP_SLTCTL_INTERLOCK)); | |
894 | ||
895 | w = get_conf_word(d, where + PCI_EXP_SLTSTA); | |
896 | printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n", | |
897 | FLAG(w, PCI_EXP_SLTSTA_ATNB), | |
898 | FLAG(w, PCI_EXP_SLTSTA_PWRF), | |
899 | FLAG(w, PCI_EXP_SLTSTA_MRL_ST), | |
900 | FLAG(w, PCI_EXP_SLTSTA_CMDC), | |
901 | FLAG(w, PCI_EXP_SLTSTA_PRES), | |
902 | FLAG(w, PCI_EXP_SLTSTA_INTERLOCK)); | |
903 | printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n", | |
904 | FLAG(w, PCI_EXP_SLTSTA_MRLS), | |
905 | FLAG(w, PCI_EXP_SLTSTA_PRSD), | |
906 | FLAG(w, PCI_EXP_SLTSTA_LLCHG)); | |
907 | } | |
908 | ||
909 | static void cap_express_root(struct device *d, int where) | |
910 | { | |
e6a11bb4 BH |
911 | u32 w; |
912 | ||
913 | w = get_conf_word(d, where + PCI_EXP_RTCAP); | |
914 | printf("\t\tRootCap: CRSVisible%c\n", | |
915 | FLAG(w, PCI_EXP_RTCAP_CRSVIS)); | |
916 | ||
917 | w = get_conf_word(d, where + PCI_EXP_RTCTL); | |
c7a34993 MM |
918 | printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n", |
919 | FLAG(w, PCI_EXP_RTCTL_SECEE), | |
920 | FLAG(w, PCI_EXP_RTCTL_SENFEE), | |
921 | FLAG(w, PCI_EXP_RTCTL_SEFEE), | |
922 | FLAG(w, PCI_EXP_RTCTL_PMEIE), | |
923 | FLAG(w, PCI_EXP_RTCTL_CRSVIS)); | |
924 | ||
23c27798 | 925 | w = get_conf_long(d, where + PCI_EXP_RTSTA); |
c7a34993 MM |
926 | printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n", |
927 | w & PCI_EXP_RTSTA_PME_REQID, | |
928 | FLAG(w, PCI_EXP_RTSTA_PME_STATUS), | |
929 | FLAG(w, PCI_EXP_RTSTA_PME_PENDING)); | |
930 | } | |
931 | ||
932 | static const char *cap_express_dev2_timeout_range(int type) | |
933 | { | |
934 | /* Decode Completion Timeout Ranges. */ | |
935 | switch (type) | |
936 | { | |
937 | case 0: | |
938 | return "Not Supported"; | |
939 | case 1: | |
940 | return "Range A"; | |
941 | case 2: | |
942 | return "Range B"; | |
943 | case 3: | |
944 | return "Range AB"; | |
945 | case 6: | |
946 | return "Range BC"; | |
947 | case 7: | |
948 | return "Range ABC"; | |
949 | case 14: | |
950 | return "Range BCD"; | |
951 | case 15: | |
952 | return "Range ABCD"; | |
953 | default: | |
954 | return "Unknown"; | |
955 | } | |
956 | } | |
957 | ||
958 | static const char *cap_express_dev2_timeout_value(int type) | |
959 | { | |
960 | /* Decode Completion Timeout Value. */ | |
961 | switch (type) | |
962 | { | |
963 | case 0: | |
964 | return "50us to 50ms"; | |
965 | case 1: | |
966 | return "50us to 100us"; | |
967 | case 2: | |
968 | return "1ms to 10ms"; | |
969 | case 5: | |
970 | return "16ms to 55ms"; | |
971 | case 6: | |
972 | return "65ms to 210ms"; | |
973 | case 9: | |
974 | return "260ms to 900ms"; | |
975 | case 10: | |
976 | return "1s to 3.5s"; | |
977 | case 13: | |
978 | return "4s to 13s"; | |
979 | case 14: | |
980 | return "17s to 64s"; | |
981 | default: | |
982 | return "Unknown"; | |
983 | } | |
984 | } | |
985 | ||
d4c91e40 MW |
986 | static const char *cap_express_devcap2_obff(int obff) |
987 | { | |
988 | switch (obff) | |
989 | { | |
990 | case 1: | |
991 | return "Via message"; | |
992 | case 2: | |
993 | return "Via WAKE#"; | |
994 | case 3: | |
995 | return "Via message/WAKE#"; | |
996 | default: | |
997 | return "Not Supported"; | |
998 | } | |
999 | } | |
1000 | ||
33226851 FL |
1001 | static const char *cap_express_devcap2_epr(int epr) |
1002 | { | |
1003 | switch (epr) | |
1004 | { | |
1005 | case 1: | |
1006 | return "Dev Specific"; | |
1007 | case 2: | |
1008 | return "Form Factor Dev Specific"; | |
1009 | case 3: | |
1010 | return "Reserved"; | |
1011 | default: | |
1012 | return "Not Supported"; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | static const char *cap_express_devcap2_lncls(int lncls) | |
1017 | { | |
1018 | switch (lncls) | |
1019 | { | |
1020 | case 1: | |
1021 | return "64byte cachelines"; | |
1022 | case 2: | |
1023 | return "128byte cachelines"; | |
1024 | case 3: | |
1025 | return "Reserved"; | |
1026 | default: | |
1027 | return "Not Supported"; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | static const char *cap_express_devcap2_tphcomp(int tph) | |
1032 | { | |
1033 | switch (tph) | |
1034 | { | |
1035 | case 1: | |
018f413c | 1036 | return "TPHComp+ ExtTPHComp-"; |
33226851 FL |
1037 | case 2: |
1038 | /* Reserved; intentionally left blank */ | |
1039 | return ""; | |
1040 | case 3: | |
018f413c | 1041 | return "TPHComp+ ExtTPHComp+"; |
33226851 | 1042 | default: |
018f413c | 1043 | return "TPHComp- ExtTPHComp-"; |
33226851 FL |
1044 | } |
1045 | } | |
1046 | ||
d4c91e40 MW |
1047 | static const char *cap_express_devctl2_obff(int obff) |
1048 | { | |
1049 | switch (obff) | |
1050 | { | |
1051 | case 0: | |
1052 | return "Disabled"; | |
1053 | case 1: | |
1054 | return "Via message A"; | |
1055 | case 2: | |
1056 | return "Via message B"; | |
1057 | case 3: | |
1058 | return "Via WAKE#"; | |
1059 | default: | |
1060 | return "Unknown"; | |
1061 | } | |
1062 | } | |
1063 | ||
ad431573 SB |
1064 | static int |
1065 | device_has_memory_space_bar(struct device *d) | |
1066 | { | |
1067 | struct pci_dev *p = d->dev; | |
1068 | int i, found = 0; | |
1069 | ||
1070 | for (i=0; i<6; i++) | |
1071 | if (p->base_addr[i] && p->size[i]) | |
1072 | { | |
1073 | if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO)) | |
1074 | { | |
1075 | found = 1; | |
1076 | break; | |
1077 | } | |
1078 | } | |
1079 | return found; | |
1080 | } | |
1081 | ||
c7a34993 MM |
1082 | static void cap_express_dev2(struct device *d, int where, int type) |
1083 | { | |
1084 | u32 l; | |
1085 | u16 w; | |
5371aab4 | 1086 | int has_mem_bar = device_has_memory_space_bar(d); |
c7a34993 MM |
1087 | |
1088 | l = get_conf_long(d, where + PCI_EXP_DEVCAP2); | |
018f413c | 1089 | printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c", |
e79a4207 DL |
1090 | cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)), |
1091 | FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS), | |
33226851 FL |
1092 | FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP), |
1093 | FLAG(l, PCI_EXP_DEVCAP2_LTR)); | |
018f413c | 1094 | printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c", |
33226851 FL |
1095 | FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP), |
1096 | FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ), | |
1097 | cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)), | |
1098 | FLAG(l, PCI_EXP_DEVCAP2_EXTFMT), | |
1099 | FLAG(l, PCI_EXP_DEVCAP2_EE_TLP)); | |
1100 | ||
1101 | if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP)) | |
1102 | { | |
1103 | printf(", MaxEETLPPrefixes %d", | |
1104 | PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4); | |
1105 | } | |
1106 | ||
1107 | printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c", | |
1108 | cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)), | |
1109 | FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT)); | |
1110 | printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS)); | |
1111 | ||
1112 | if (type == PCI_EXP_TYPE_ROOT_PORT) | |
018f413c | 1113 | printf(" LN System CLS %s,", |
33226851 FL |
1114 | cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l))); |
1115 | ||
1116 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT) | |
018f413c | 1117 | printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l))); |
33226851 | 1118 | |
c7a34993 | 1119 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) |
e79a4207 | 1120 | printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI)); |
c7a34993 MM |
1121 | else |
1122 | printf("\n"); | |
ad431573 SB |
1123 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1124 | type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar) | |
1125 | { | |
c4cf2d1c | 1126 | printf("\t\t\t AtomicOpsCap:"); |
ad431573 SB |
1127 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1128 | type == PCI_EXP_TYPE_DOWNSTREAM) | |
1129 | printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING)); | |
1130 | if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar) | |
1131 | printf(" 32bit%c 64bit%c 128bitCAS%c", | |
1132 | FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP), | |
1133 | FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP), | |
1134 | FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP)); | |
1135 | printf("\n"); | |
1136 | } | |
c7a34993 MM |
1137 | |
1138 | w = get_conf_word(d, where + PCI_EXP_DEVCTL2); | |
3afdb452 | 1139 | printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,", |
e79a4207 DL |
1140 | cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)), |
1141 | FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS), | |
1142 | FLAG(w, PCI_EXP_DEVCTL2_LTR), | |
3afdb452 | 1143 | FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ), |
e79a4207 | 1144 | cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w))); |
c7a34993 | 1145 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) |
e79a4207 | 1146 | printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI)); |
c7a34993 MM |
1147 | else |
1148 | printf("\n"); | |
ad431573 SB |
1149 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1150 | type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT || | |
1151 | type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) | |
1152 | { | |
c4cf2d1c | 1153 | printf("\t\t\t AtomicOpsCtl:"); |
ad431573 SB |
1154 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT || |
1155 | type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) | |
e79a4207 | 1156 | printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN)); |
ad431573 SB |
1157 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1158 | type == PCI_EXP_TYPE_DOWNSTREAM) | |
e79a4207 | 1159 | printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK)); |
ad431573 SB |
1160 | printf("\n"); |
1161 | } | |
c7a34993 MM |
1162 | } |
1163 | ||
623ed0e1 BH |
1164 | static const char *cap_express_link2_speed_cap(int vector) |
1165 | { | |
1166 | /* | |
1167 | * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not | |
1168 | * permitted to skip support for any data rates between 2.5GT/s and the | |
1169 | * highest supported rate. | |
1170 | */ | |
1171 | if (vector & 0x60) | |
1172 | return "RsvdP"; | |
1173 | if (vector & 0x10) | |
1174 | return "2.5-32GT/s"; | |
1175 | if (vector & 0x08) | |
1176 | return "2.5-16GT/s"; | |
1177 | if (vector & 0x04) | |
1178 | return "2.5-8GT/s"; | |
1179 | if (vector & 0x02) | |
1180 | return "2.5-5GT/s"; | |
1181 | if (vector & 0x01) | |
1182 | return "2.5GT/s"; | |
1183 | ||
1184 | return "Unknown"; | |
1185 | } | |
1186 | ||
c7a34993 MM |
1187 | static const char *cap_express_link2_speed(int type) |
1188 | { | |
1189 | switch (type) | |
1190 | { | |
1191 | case 0: /* hardwire to 0 means only the 2.5GT/s is supported */ | |
1192 | case 1: | |
1193 | return "2.5GT/s"; | |
1194 | case 2: | |
1195 | return "5GT/s"; | |
4dc4ff43 MM |
1196 | case 3: |
1197 | return "8GT/s"; | |
9628600b GS |
1198 | case 4: |
1199 | return "16GT/s"; | |
caca31a0 GP |
1200 | case 5: |
1201 | return "32GT/s"; | |
5bdf63b6 GP |
1202 | case 6: |
1203 | return "64GT/s"; | |
c7a34993 MM |
1204 | default: |
1205 | return "Unknown"; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | static const char *cap_express_link2_deemphasis(int type) | |
1210 | { | |
1211 | switch (type) | |
1212 | { | |
1213 | case 0: | |
1214 | return "-6dB"; | |
1215 | case 1: | |
1216 | return "-3.5dB"; | |
1217 | default: | |
1218 | return "Unknown"; | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | static const char *cap_express_link2_transmargin(int type) | |
1223 | { | |
1224 | switch (type) | |
1225 | { | |
1226 | case 0: | |
1227 | return "Normal Operating Range"; | |
1228 | case 1: | |
1229 | return "800-1200mV(full-swing)/400-700mV(half-swing)"; | |
1230 | case 2: | |
1231 | case 3: | |
1232 | case 4: | |
1233 | case 5: | |
1234 | return "200-400mV(full-swing)/100-200mV(half-swing)"; | |
1235 | default: | |
1236 | return "Unknown"; | |
1237 | } | |
1238 | } | |
1239 | ||
623ed0e1 BH |
1240 | static const char *cap_express_link2_crosslink_res(int crosslink) |
1241 | { | |
1242 | switch (crosslink) | |
1243 | { | |
1244 | case 0: | |
1245 | return "unsupported"; | |
1246 | case 1: | |
1247 | return "Upstream Port"; | |
1248 | case 2: | |
1249 | return "Downstream Port"; | |
1250 | default: | |
1251 | return "incomplete"; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | static const char *cap_express_link2_component(int presence) | |
1256 | { | |
1257 | switch (presence) | |
1258 | { | |
1259 | case 0: | |
1260 | return "Link Down - Not Determined"; | |
1261 | case 1: | |
1262 | return "Link Down - Not Present"; | |
1263 | case 2: | |
1264 | return "Link Down - Present"; | |
1265 | case 4: | |
1266 | return "Link Up - Present"; | |
1267 | case 5: | |
1268 | return "Link Up - Present and DRS Received"; | |
1269 | default: | |
1270 | return "Reserved"; | |
1271 | } | |
1272 | } | |
1273 | ||
37f8039d | 1274 | static void cap_express_link2(struct device *d, int where, int type) |
c7a34993 | 1275 | { |
623ed0e1 | 1276 | u32 l = 0; |
c7a34993 MM |
1277 | u16 w; |
1278 | ||
37f8039d BH |
1279 | if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) && |
1280 | (d->dev->dev != 0 || d->dev->func != 0))) { | |
623ed0e1 BH |
1281 | /* Link Capabilities 2 was reserved before PCIe r3.0 */ |
1282 | l = get_conf_long(d, where + PCI_EXP_LNKCAP2); | |
1283 | if (l) { | |
1284 | printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c " | |
1285 | "Retimer%c 2Retimers%c DRS%c\n", | |
1286 | cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)), | |
1287 | FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK), | |
1288 | FLAG(l, PCI_EXP_LNKCAP2_RETIMER), | |
1289 | FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS), | |
1290 | FLAG(l, PCI_EXP_LNKCAP2_DRS)); | |
1291 | } | |
1292 | ||
37f8039d BH |
1293 | w = get_conf_word(d, where + PCI_EXP_LNKCTL2); |
1294 | printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c", | |
c7a34993 MM |
1295 | cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)), |
1296 | FLAG(w, PCI_EXP_LNKCTL2_CMPLNC), | |
37f8039d BH |
1297 | FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS)); |
1298 | if (type == PCI_EXP_TYPE_DOWNSTREAM) | |
1299 | printf(", Selectable De-emphasis: %s", | |
1300 | cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w))); | |
1301 | printf("\n" | |
1302 | "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n" | |
1303 | "\t\t\t Compliance De-emphasis: %s\n", | |
c7a34993 MM |
1304 | cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)), |
1305 | FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC), | |
1306 | FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS), | |
1307 | cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w))); | |
37f8039d | 1308 | } |
c7a34993 MM |
1309 | |
1310 | w = get_conf_word(d, where + PCI_EXP_LNKSTA2); | |
018f413c BH |
1311 | printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n" |
1312 | "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n" | |
623ed0e1 | 1313 | "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", |
4dc4ff43 MM |
1314 | cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), |
1315 | FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), | |
1316 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), | |
1317 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2), | |
1318 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3), | |
623ed0e1 BH |
1319 | FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), |
1320 | FLAG(w, PCI_EXP_LINKSTA2_RETIMER), | |
1321 | FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), | |
1322 | cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); | |
1323 | ||
1324 | if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { | |
1325 | printf(", DRS%c\n" | |
1326 | "\t\t\t DownstreamComp: %s\n", | |
1327 | FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD), | |
1328 | cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w))); | |
1329 | } else | |
1330 | printf("\n"); | |
c7a34993 MM |
1331 | } |
1332 | ||
1333 | static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) | |
1334 | { | |
1335 | /* No capabilities that require this field in PCIe rev2.0 spec. */ | |
1336 | } | |
1337 | ||
a1492b88 | 1338 | static int |
c7a34993 MM |
1339 | cap_express(struct device *d, int where, int cap) |
1340 | { | |
1341 | int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; | |
1342 | int size; | |
1343 | int slot = 0; | |
17ebd1d1 | 1344 | int link = 1; |
c7a34993 MM |
1345 | |
1346 | printf("Express "); | |
1347 | if (verbose >= 2) | |
1348 | printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS); | |
1349 | switch (type) | |
1350 | { | |
1351 | case PCI_EXP_TYPE_ENDPOINT: | |
1352 | printf("Endpoint"); | |
1353 | break; | |
1354 | case PCI_EXP_TYPE_LEG_END: | |
1355 | printf("Legacy Endpoint"); | |
1356 | break; | |
1357 | case PCI_EXP_TYPE_ROOT_PORT: | |
1358 | slot = cap & PCI_EXP_FLAGS_SLOT; | |
1359 | printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
1360 | break; | |
1361 | case PCI_EXP_TYPE_UPSTREAM: | |
1362 | printf("Upstream Port"); | |
1363 | break; | |
1364 | case PCI_EXP_TYPE_DOWNSTREAM: | |
1365 | slot = cap & PCI_EXP_FLAGS_SLOT; | |
1366 | printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
1367 | break; | |
1368 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
77120d53 | 1369 | printf("PCI-Express to PCI/PCI-X Bridge"); |
c7a34993 MM |
1370 | break; |
1371 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
f41bb847 BH |
1372 | slot = cap & PCI_EXP_FLAGS_SLOT; |
1373 | printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)", | |
1374 | FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
c7a34993 MM |
1375 | break; |
1376 | case PCI_EXP_TYPE_ROOT_INT_EP: | |
17ebd1d1 | 1377 | link = 0; |
c7a34993 MM |
1378 | printf("Root Complex Integrated Endpoint"); |
1379 | break; | |
1380 | case PCI_EXP_TYPE_ROOT_EC: | |
17ebd1d1 | 1381 | link = 0; |
c7a34993 MM |
1382 | printf("Root Complex Event Collector"); |
1383 | break; | |
1384 | default: | |
1385 | printf("Unknown type %d", type); | |
1386 | } | |
1387 | printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); | |
1388 | if (verbose < 2) | |
a1492b88 | 1389 | return type; |
c7a34993 MM |
1390 | |
1391 | size = 16; | |
1392 | if (slot) | |
1393 | size = 24; | |
7155d510 | 1394 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) |
c7a34993 MM |
1395 | size = 32; |
1396 | if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) | |
a1492b88 | 1397 | return type; |
c7a34993 MM |
1398 | |
1399 | cap_express_dev(d, where, type); | |
17ebd1d1 BH |
1400 | if (link) |
1401 | cap_express_link(d, where, type); | |
c7a34993 MM |
1402 | if (slot) |
1403 | cap_express_slot(d, where); | |
7155d510 | 1404 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) |
c7a34993 MM |
1405 | cap_express_root(d, where); |
1406 | ||
1407 | if ((cap & PCI_EXP_FLAGS_VERS) < 2) | |
a1492b88 | 1408 | return type; |
c7a34993 MM |
1409 | |
1410 | size = 16; | |
1411 | if (slot) | |
1412 | size = 24; | |
1413 | if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size)) | |
a1492b88 | 1414 | return type; |
c7a34993 MM |
1415 | |
1416 | cap_express_dev2(d, where, type); | |
17ebd1d1 BH |
1417 | if (link) |
1418 | cap_express_link2(d, where, type); | |
c7a34993 MM |
1419 | if (slot) |
1420 | cap_express_slot2(d, where); | |
a1492b88 | 1421 | return type; |
c7a34993 MM |
1422 | } |
1423 | ||
1424 | static void | |
1425 | cap_msix(struct device *d, int where, int cap) | |
1426 | { | |
1427 | u32 off; | |
1428 | ||
04885ef7 | 1429 | printf("MSI-X: Enable%c Count=%d Masked%c\n", |
c7a34993 | 1430 | FLAG(cap, PCI_MSIX_ENABLE), |
04885ef7 MW |
1431 | (cap & PCI_MSIX_TABSIZE) + 1, |
1432 | FLAG(cap, PCI_MSIX_MASK)); | |
c7a34993 MM |
1433 | if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8)) |
1434 | return; | |
1435 | ||
1436 | off = get_conf_long(d, where + PCI_MSIX_TABLE); | |
1437 | printf("\t\tVector table: BAR=%d offset=%08x\n", | |
1438 | off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); | |
1439 | off = get_conf_long(d, where + PCI_MSIX_PBA); | |
1440 | printf("\t\tPBA: BAR=%d offset=%08x\n", | |
1441 | off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); | |
1442 | } | |
1443 | ||
1444 | static void | |
1445 | cap_slotid(int cap) | |
1446 | { | |
1447 | int esr = cap & 0xff; | |
1448 | int chs = cap >> 8; | |
1449 | ||
1450 | printf("Slot ID: %d slots, First%c, chassis %02x\n", | |
1451 | esr & PCI_SID_ESR_NSLOTS, | |
1452 | FLAG(esr, PCI_SID_ESR_FIC), | |
1453 | chs); | |
1454 | } | |
1455 | ||
1456 | static void | |
1457 | cap_ssvid(struct device *d, int where) | |
1458 | { | |
1459 | u16 subsys_v, subsys_d; | |
1460 | char ssnamebuf[256]; | |
1461 | ||
1462 | if (!config_fetch(d, where, 8)) | |
1463 | return; | |
1464 | subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR); | |
1465 | subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE); | |
1466 | printf("Subsystem: %s\n", | |
1467 | pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf), | |
1468 | PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, | |
1469 | d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d)); | |
1470 | } | |
1471 | ||
1472 | static void | |
1473 | cap_debug_port(int cap) | |
1474 | { | |
1475 | int bar = cap >> 13; | |
1476 | int pos = cap & 0x1fff; | |
1477 | printf("Debug port: BAR=%d offset=%04x\n", bar, pos); | |
1478 | } | |
1479 | ||
99eb76e5 YZ |
1480 | static void |
1481 | cap_af(struct device *d, int where) | |
1482 | { | |
1483 | u8 reg; | |
1484 | ||
1485 | printf("PCI Advanced Features\n"); | |
1486 | if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3)) | |
1487 | return; | |
1488 | ||
1489 | reg = get_conf_byte(d, where + PCI_AF_CAP); | |
1490 | printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP), | |
1491 | FLAG(reg, PCI_AF_CAP_FLR)); | |
1492 | reg = get_conf_byte(d, where + PCI_AF_CTRL); | |
1493 | printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR)); | |
1494 | reg = get_conf_byte(d, where + PCI_AF_STATUS); | |
1495 | printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP)); | |
1496 | } | |
1497 | ||
be9c1b75 MM |
1498 | static void |
1499 | cap_sata_hba(struct device *d, int where, int cap) | |
1500 | { | |
1501 | u32 bars; | |
1502 | int bar; | |
1503 | ||
1504 | printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4)); | |
1505 | if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4)) | |
1506 | { | |
1507 | printf("\n"); | |
1508 | return; | |
1509 | } | |
1510 | ||
1511 | bars = get_conf_long(d, where + PCI_SATA_HBA_BARS); | |
1512 | bar = BITS(bars, 0, 4); | |
1513 | if (bar >= 4 && bar <= 9) | |
1514 | printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20)); | |
1515 | else if (bar == 15) | |
1516 | printf(" InCfgSpace\n"); | |
1517 | else | |
1518 | printf(" BAR??%d\n", bar); | |
1519 | } | |
1520 | ||
4cd841df DD |
1521 | static const char *cap_ea_property(int p, int is_secondary) |
1522 | { | |
1523 | switch (p) { | |
1524 | case 0x00: | |
1525 | return "memory space, non-prefetchable"; | |
1526 | case 0x01: | |
1527 | return "memory space, prefetchable"; | |
1528 | case 0x02: | |
1529 | return "I/O space"; | |
1530 | case 0x03: | |
1531 | return "VF memory space, prefetchable"; | |
1532 | case 0x04: | |
1533 | return "VF memory space, non-prefetchable"; | |
1534 | case 0x05: | |
1535 | return "allocation behind bridge, non-prefetchable memory"; | |
1536 | case 0x06: | |
1537 | return "allocation behind bridge, prefetchable memory"; | |
1538 | case 0x07: | |
1539 | return "allocation behind bridge, I/O space"; | |
1540 | case 0xfd: | |
1541 | return "memory space resource unavailable for use"; | |
1542 | case 0xfe: | |
1543 | return "I/O space resource unavailable for use"; | |
1544 | case 0xff: | |
1545 | if (is_secondary) | |
1546 | return "entry unavailable for use, PrimaryProperties should be used"; | |
1547 | else | |
1548 | return "entry unavailable for use"; | |
1549 | default: | |
1550 | return NULL; | |
1551 | } | |
1552 | } | |
1553 | ||
1554 | static void cap_ea(struct device *d, int where, int cap) | |
1555 | { | |
1556 | int entry; | |
1557 | int entry_base = where + 4; | |
1558 | int num_entries = BITS(cap, 0, 6); | |
1559 | u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f; | |
1560 | ||
1561 | printf("Enhanced Allocation (EA): NumEntries=%u", num_entries); | |
1562 | if (htype == PCI_HEADER_TYPE_BRIDGE) { | |
1563 | byte fixed_sub, fixed_sec; | |
1564 | ||
1565 | entry_base += 4; | |
1566 | if (!config_fetch(d, where + 4, 2)) { | |
1567 | printf("\n"); | |
1568 | return; | |
1569 | } | |
1570 | fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY); | |
1571 | fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE); | |
1572 | printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub); | |
1573 | } | |
1574 | printf("\n"); | |
1575 | if (verbose < 2) | |
1576 | return; | |
1577 | ||
1578 | for (entry = 0; entry < num_entries; entry++) { | |
1579 | int max_offset_high_pos, has_base_high, has_max_offset_high; | |
1580 | u32 entry_header; | |
1581 | u32 base, max_offset; | |
1582 | int es, bei, pp, sp; | |
1583 | const char *prop_text; | |
1584 | ||
1585 | if (!config_fetch(d, entry_base, 4)) | |
1586 | return; | |
1587 | entry_header = get_conf_long(d, entry_base); | |
1588 | es = BITS(entry_header, 0, 3); | |
1589 | bei = BITS(entry_header, 4, 4); | |
1590 | pp = BITS(entry_header, 8, 8); | |
1591 | sp = BITS(entry_header, 16, 8); | |
1592 | if (!config_fetch(d, entry_base + 4, es * 4)) | |
1593 | return; | |
1594 | printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry, | |
1595 | FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE), | |
1596 | FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es); | |
1597 | printf("\t\t\t BAR Equivalent Indicator: "); | |
1598 | switch (bei) { | |
1599 | case 0: | |
1600 | case 1: | |
1601 | case 2: | |
1602 | case 3: | |
1603 | case 4: | |
1604 | case 5: | |
1605 | printf("BAR %u", bei); | |
1606 | break; | |
1607 | case 6: | |
1608 | printf("resource behind function"); | |
1609 | break; | |
1610 | case 7: | |
1611 | printf("not indicated"); | |
1612 | break; | |
1613 | case 8: | |
1614 | printf("expansion ROM"); | |
1615 | break; | |
1616 | case 9: | |
1617 | case 10: | |
1618 | case 11: | |
1619 | case 12: | |
1620 | case 13: | |
1621 | case 14: | |
1622 | printf("VF-BAR %u", bei - 9); | |
1623 | break; | |
1624 | default: | |
1625 | printf("reserved"); | |
1626 | break; | |
1627 | } | |
1628 | printf("\n"); | |
1629 | ||
1630 | prop_text = cap_ea_property(pp, 0); | |
1631 | printf("\t\t\t PrimaryProperties: "); | |
1632 | if (prop_text) | |
1633 | printf("%s\n", prop_text); | |
1634 | else | |
1635 | printf("[%02x]\n", pp); | |
1636 | ||
1637 | prop_text = cap_ea_property(sp, 1); | |
1638 | printf("\t\t\t SecondaryProperties: "); | |
1639 | if (prop_text) | |
1640 | printf("%s\n", prop_text); | |
1641 | else | |
1642 | printf("[%02x]\n", sp); | |
1643 | ||
1644 | base = get_conf_long(d, entry_base + 4); | |
1645 | has_base_high = ((base & 2) != 0); | |
1646 | base &= ~3; | |
1647 | ||
1648 | max_offset = get_conf_long(d, entry_base + 8); | |
1649 | has_max_offset_high = ((max_offset & 2) != 0); | |
1650 | max_offset |= 3; | |
1651 | max_offset_high_pos = entry_base + 12; | |
1652 | ||
1653 | printf("\t\t\t Base: "); | |
1654 | if (has_base_high) { | |
1655 | u32 base_high = get_conf_long(d, entry_base + 12); | |
1656 | ||
1657 | printf("%x", base_high); | |
1658 | max_offset_high_pos += 4; | |
1659 | } | |
1660 | printf("%08x\n", base); | |
1661 | ||
1662 | printf("\t\t\t MaxOffset: "); | |
1663 | if (has_max_offset_high) { | |
1664 | u32 max_offset_high = get_conf_long(d, max_offset_high_pos); | |
1665 | ||
1666 | printf("%x", max_offset_high); | |
1667 | } | |
1668 | printf("%08x\n", max_offset); | |
1669 | ||
1670 | entry_base += 4 + 4 * es; | |
1671 | } | |
1672 | } | |
1673 | ||
c7a34993 | 1674 | void |
21510591 | 1675 | show_caps(struct device *d, int where) |
c7a34993 MM |
1676 | { |
1677 | int can_have_ext_caps = 0; | |
a1492b88 | 1678 | int type = -1; |
c7a34993 MM |
1679 | |
1680 | if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) | |
1681 | { | |
c7a34993 | 1682 | byte been_there[256]; |
01de4db1 | 1683 | where = get_conf_byte(d, where) & ~3; |
c7a34993 MM |
1684 | memset(been_there, 0, 256); |
1685 | while (where) | |
1686 | { | |
1687 | int id, next, cap; | |
1688 | printf("\tCapabilities: "); | |
1689 | if (!config_fetch(d, where, 4)) | |
1690 | { | |
1691 | puts("<access denied>"); | |
1692 | break; | |
1693 | } | |
1694 | id = get_conf_byte(d, where + PCI_CAP_LIST_ID); | |
1695 | next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3; | |
1696 | cap = get_conf_word(d, where + PCI_CAP_FLAGS); | |
1697 | printf("[%02x] ", where); | |
1698 | if (been_there[where]++) | |
1699 | { | |
1700 | printf("<chain looped>\n"); | |
1701 | break; | |
1702 | } | |
1703 | if (id == 0xff) | |
1704 | { | |
1705 | printf("<chain broken>\n"); | |
1706 | break; | |
1707 | } | |
1708 | switch (id) | |
1709 | { | |
c508d1c9 BH |
1710 | case PCI_CAP_ID_NULL: |
1711 | printf("Null\n"); | |
1712 | break; | |
c7a34993 MM |
1713 | case PCI_CAP_ID_PM: |
1714 | cap_pm(d, where, cap); | |
1715 | break; | |
1716 | case PCI_CAP_ID_AGP: | |
1717 | cap_agp(d, where, cap); | |
1718 | break; | |
1719 | case PCI_CAP_ID_VPD: | |
1720 | cap_vpd(d); | |
1721 | break; | |
1722 | case PCI_CAP_ID_SLOTID: | |
1723 | cap_slotid(cap); | |
1724 | break; | |
1725 | case PCI_CAP_ID_MSI: | |
1726 | cap_msi(d, where, cap); | |
1727 | break; | |
1728 | case PCI_CAP_ID_CHSWP: | |
1729 | printf("CompactPCI hot-swap <?>\n"); | |
1730 | break; | |
1731 | case PCI_CAP_ID_PCIX: | |
1732 | cap_pcix(d, where); | |
1733 | can_have_ext_caps = 1; | |
1734 | break; | |
1735 | case PCI_CAP_ID_HT: | |
1736 | cap_ht(d, where, cap); | |
1737 | break; | |
1738 | case PCI_CAP_ID_VNDR: | |
7ff8a323 | 1739 | show_vendor_caps(d, where, cap); |
c7a34993 MM |
1740 | break; |
1741 | case PCI_CAP_ID_DBG: | |
1742 | cap_debug_port(cap); | |
1743 | break; | |
1744 | case PCI_CAP_ID_CCRC: | |
1745 | printf("CompactPCI central resource control <?>\n"); | |
1746 | break; | |
1747 | case PCI_CAP_ID_HOTPLUG: | |
1748 | printf("Hot-plug capable\n"); | |
1749 | break; | |
1750 | case PCI_CAP_ID_SSVID: | |
1751 | cap_ssvid(d, where); | |
1752 | break; | |
1753 | case PCI_CAP_ID_AGP3: | |
1754 | printf("AGP3 <?>\n"); | |
1755 | break; | |
1756 | case PCI_CAP_ID_SECURE: | |
1757 | printf("Secure device <?>\n"); | |
1758 | break; | |
1759 | case PCI_CAP_ID_EXP: | |
a1492b88 | 1760 | type = cap_express(d, where, cap); |
c7a34993 MM |
1761 | can_have_ext_caps = 1; |
1762 | break; | |
1763 | case PCI_CAP_ID_MSIX: | |
1764 | cap_msix(d, where, cap); | |
1765 | break; | |
1766 | case PCI_CAP_ID_SATA: | |
be9c1b75 | 1767 | cap_sata_hba(d, where, cap); |
c7a34993 MM |
1768 | break; |
1769 | case PCI_CAP_ID_AF: | |
99eb76e5 | 1770 | cap_af(d, where); |
c7a34993 | 1771 | break; |
4cd841df DD |
1772 | case PCI_CAP_ID_EA: |
1773 | cap_ea(d, where, cap); | |
1774 | break; | |
c7a34993 | 1775 | default: |
60a45a7e | 1776 | printf("Capability ID %#02x [%04x]\n", id, cap); |
c7a34993 MM |
1777 | } |
1778 | where = next; | |
1779 | } | |
1780 | } | |
1781 | if (can_have_ext_caps) | |
a1492b88 | 1782 | show_ext_caps(d, type); |
c7a34993 | 1783 | } |