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d9dc34cd TMQMF |
1 | @node Platform, Contributors, Maintenance, Top |
2 | @c %MENU% Describe all platform-specific facilities provided | |
3 | @appendix Platform-specific facilities | |
4 | ||
5 | @Theglibc{} can provide machine-specific functionality. | |
6 | ||
7 | @menu | |
8 | * PowerPC:: Facilities Specific to the PowerPC Architecture | |
ba9e25a6 | 9 | * RISC-V:: Facilities Specific to the RISC-V Architecture |
96203980 | 10 | * X86:: Facilities Specific to the X86 Architecture |
d9dc34cd TMQMF |
11 | @end menu |
12 | ||
13 | @node PowerPC | |
14 | @appendixsec PowerPC-specific Facilities | |
15 | ||
16 | Facilities specific to PowerPC that are not specific to a particular | |
17 | operating system are declared in @file{sys/platform/ppc.h}. | |
18 | ||
19 | @deftypefun {uint64_t} __ppc_get_timebase (void) | |
e2dfb7f4 | 20 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
d9dc34cd TMQMF |
21 | Read the current value of the Time Base Register. |
22 | ||
23 | The @dfn{Time Base Register} is a 64-bit register that stores a monotonically | |
24 | incremented value updated at a system-dependent frequency that may be | |
25 | different from the processor frequency. More information is available in | |
26 | @cite{Power ISA 2.06b - Book II - Section 5.2}. | |
27 | ||
28 | @code{__ppc_get_timebase} uses the processor's time base facility directly | |
29 | without requiring assistance from the operating system, so it is very | |
30 | efficient. | |
31 | @end deftypefun | |
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32 | |
33 | @deftypefun {uint64_t} __ppc_get_timebase_freq (void) | |
e2dfb7f4 AO |
34 | @safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}} |
35 | @c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd | |
36 | @c __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd | |
37 | @c the initialization of the static timebase_freq is not exactly | |
38 | @c safe, because hp_timing_t cannot be atomically set up. | |
39 | @c syscall:get_tbfreq ok | |
40 | @c open dup @acsfd | |
41 | @c read dup ok | |
42 | @c memcpy dup ok | |
43 | @c memmem dup ok | |
44 | @c close dup @acsfd | |
8ad11b9a TMQMF |
45 | Read the current frequency at which the Time Base Register is updated. |
46 | ||
47 | This frequency is not related to the processor clock or the bus clock. | |
48 | It is also possible that this frequency is not constant. More information is | |
49 | available in @cite{Power ISA 2.06b - Book II - Section 5.2}. | |
50 | @end deftypefun | |
9323d39b EM |
51 | |
52 | The following functions provide hints about the usage of resources that are | |
53 | shared with other processors. They can be used, for example, if a program | |
54 | waiting on a lock intends to divert the shared resources to be used by other | |
55 | processors. More information is available in @cite{Power ISA 2.06b - Book II - | |
56 | Section 3.2}. | |
57 | ||
58 | @deftypefun {void} __ppc_yield (void) | |
e2dfb7f4 | 59 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
9323d39b EM |
60 | Provide a hint that performance will probably be improved if shared resources |
61 | dedicated to the executing processor are released for use by other processors. | |
62 | @end deftypefun | |
63 | ||
64 | @deftypefun {void} __ppc_mdoio (void) | |
e2dfb7f4 | 65 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
9323d39b EM |
66 | Provide a hint that performance will probably be improved if shared resources |
67 | dedicated to the executing processor are released until all outstanding storage | |
68 | accesses to caching-inhibited storage have been completed. | |
69 | @end deftypefun | |
70 | ||
71 | @deftypefun {void} __ppc_mdoom (void) | |
e2dfb7f4 | 72 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
9323d39b EM |
73 | Provide a hint that performance will probably be improved if shared resources |
74 | dedicated to the executing processor are released until all outstanding storage | |
75 | accesses to cacheable storage for which the data is not in the cache have been | |
76 | completed. | |
2b66ef5d | 77 | @end deftypefun |
d116b7c4 AZ |
78 | |
79 | @deftypefun {void} __ppc_set_ppr_med (void) | |
e2dfb7f4 | 80 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
d116b7c4 AZ |
81 | Set the Program Priority Register to medium value (default). |
82 | ||
83 | The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls | |
84 | the program's priority. By adjusting the PPR value the programmer may | |
85 | improve system throughput by causing the system resources to be used | |
86 | more efficiently, especially in contention situations. | |
87 | The three unprivileged states available are covered by the functions | |
88 | @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low) | |
89 | and @code{__ppc_set_ppc_med_low} (medium low). More information | |
90 | available in @cite{Power ISA 2.06b - Book II - Section 3.1}. | |
91 | @end deftypefun | |
92 | ||
93 | @deftypefun {void} __ppc_set_ppr_low (void) | |
e2dfb7f4 | 94 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
d116b7c4 AZ |
95 | Set the Program Priority Register to low value. |
96 | @end deftypefun | |
97 | ||
98 | @deftypefun {void} __ppc_set_ppr_med_low (void) | |
e2dfb7f4 | 99 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
d116b7c4 | 100 | Set the Program Priority Register to medium low value. |
9323d39b | 101 | @end deftypefun |
1747fcda GG |
102 | |
103 | Power ISA 2.07 extends the priorities that can be set to the Program Priority | |
104 | Register (PPR). The following functions implement the new priority levels: | |
105 | very low and medium high. | |
106 | ||
107 | @deftypefun {void} __ppc_set_ppr_very_low (void) | |
108 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} | |
109 | Set the Program Priority Register to very low value. | |
110 | @end deftypefun | |
111 | ||
112 | @deftypefun {void} __ppc_set_ppr_med_high (void) | |
113 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} | |
114 | Set the Program Priority Register to medium high value. The medium high | |
115 | priority is privileged and may only be set during certain time intervals by | |
116 | problem-state programs. If the program priority is medium high when the time | |
117 | interval expires or if an attempt is made to set the priority to medium high | |
118 | when it is not allowed, the priority is set to medium. | |
119 | @end deftypefun | |
ba9e25a6 PD |
120 | |
121 | @node RISC-V | |
122 | @appendixsec RISC-V-specific Facilities | |
123 | ||
124 | Cache management facilities specific to RISC-V systems that implement the Linux | |
125 | ABI are declared in @file{sys/cachectl.h}. | |
126 | ||
16efad51 | 127 | @deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags}) |
ba9e25a6 PD |
128 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
129 | Enforce ordering between stores and instruction cache fetches. The range of | |
130 | addresses over which ordering is enforced is specified by @var{start} and | |
131 | @var{end}. The @var{flags} argument controls the extent of this ordering, with | |
132 | the default behavior (a @var{flags} value of 0) being to enforce the fence on | |
133 | all threads in the current process. Setting the | |
134 | @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing | |
135 | ordering on only the current thread is necessary. All other flag bits are | |
136 | reserved. | |
137 | @end deftypefun | |
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138 | |
139 | @node X86 | |
140 | @appendixsec X86-specific Facilities | |
141 | ||
142 | Facilities specific to X86 that are not specific to a particular | |
143 | operating system are declared in @file{sys/platform/x86.h}. | |
144 | ||
ff6d62e9 | 145 | @deftypefun {const struct cpuid_feature *} __x86_get_cpuid_feature_leaf (unsigned int @var{leaf}) |
96203980 L |
146 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
147 | Return a pointer to x86 CPU feature structure used by query macros for x86 | |
ff6d62e9 | 148 | CPU feature @var{leaf}. |
96203980 L |
149 | @end deftypefun |
150 | ||
151 | @deftypefn Macro int HAS_CPU_FEATURE (@var{name}) | |
152 | This macro returns a nonzero value (true) if the processor has the feature | |
153 | @var{name}. | |
154 | @end deftypefn | |
155 | ||
156 | @deftypefn Macro int CPU_FEATURE_USABLE (@var{name}) | |
157 | This macro returns a nonzero value (true) if the processor has the feature | |
158 | @var{name} and the feature is supported by the operating system. | |
159 | @end deftypefn | |
160 | ||
161 | The supported processor features are: | |
162 | ||
163 | @itemize @bullet | |
164 | ||
165 | @item | |
166 | @code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities. | |
167 | ||
168 | @item | |
169 | @code{ADX} -- ADX instruction extensions. | |
170 | ||
171 | @item | |
172 | @code{APIC} -- APIC On-Chip. | |
173 | ||
174 | @item | |
175 | @code{AES} -- The AES instruction extensions. | |
176 | ||
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177 | @item |
178 | @code{AESKLE} -- AES Key Locker instructions are enabled by OS. | |
179 | ||
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180 | @item |
181 | @code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus. | |
182 | ||
183 | @item | |
184 | @code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus. | |
185 | ||
186 | @item | |
187 | @code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus. | |
188 | ||
189 | @item | |
190 | @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus. | |
191 | ||
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192 | @item |
193 | @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers. | |
194 | ||
195 | @item | |
196 | @code{AMX_INT8} -- Tile computational operations on 8-bit numbers. | |
197 | ||
198 | @item | |
199 | @code{AMX_TILE} -- Tile architecture. | |
200 | ||
201 | @item | |
202 | @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR. | |
203 | ||
204 | @item | |
205 | @code{AVX} -- The AVX instruction extensions. | |
206 | ||
207 | @item | |
208 | @code{AVX2} -- The AVX2 instruction extensions. | |
209 | ||
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210 | @item |
211 | @code{AVX_VNNI} -- The AVX-VNNI instruction extensions. | |
212 | ||
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213 | @item |
214 | @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions. | |
215 | ||
216 | @item | |
217 | @code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions. | |
218 | ||
219 | @item | |
220 | @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions. | |
221 | ||
222 | @item | |
223 | @code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions. | |
224 | ||
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225 | @item |
226 | @code{AVX512_FP16} -- The AVX512_FP16 instruction extensions. | |
227 | ||
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228 | @item |
229 | @code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions. | |
230 | ||
231 | @item | |
232 | @code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions. | |
233 | ||
234 | @item | |
235 | @code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions. | |
236 | ||
237 | @item | |
238 | @code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions. | |
239 | ||
240 | @item | |
241 | @code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction | |
242 | extensions. | |
243 | ||
244 | @item | |
245 | @code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions. | |
246 | ||
247 | @item | |
248 | @code{AVX512BW} -- The AVX512BW instruction extensions. | |
249 | ||
250 | @item | |
251 | @code{AVX512CD} -- The AVX512CD instruction extensions. | |
252 | ||
253 | @item | |
254 | @code{AVX512ER} -- The AVX512ER instruction extensions. | |
255 | ||
256 | @item | |
257 | @code{AVX512DQ} -- The AVX512DQ instruction extensions. | |
258 | ||
259 | @item | |
260 | @code{AVX512F} -- The AVX512F instruction extensions. | |
261 | ||
262 | @item | |
263 | @code{AVX512PF} -- The AVX512PF instruction extensions. | |
264 | ||
265 | @item | |
266 | @code{AVX512VL} -- The AVX512VL instruction extensions. | |
267 | ||
268 | @item | |
269 | @code{BMI1} -- BMI1 instructions. | |
270 | ||
271 | @item | |
272 | @code{BMI2} -- BMI2 instructions. | |
273 | ||
274 | @item | |
275 | @code{CLDEMOTE} -- CLDEMOTE instruction. | |
276 | ||
277 | @item | |
278 | @code{CLFLUSHOPT} -- CLFLUSHOPT instruction. | |
279 | ||
280 | @item | |
281 | @code{CLFSH} -- CLFLUSH instruction. | |
282 | ||
283 | @item | |
284 | @code{CLWB} -- CLWB instruction. | |
285 | ||
286 | @item | |
287 | @code{CMOV} -- Conditional Move instructions. | |
288 | ||
289 | @item | |
290 | @code{CMPXCHG16B} -- CMPXCHG16B instruction. | |
291 | ||
292 | @item | |
293 | @code{CNXT_ID} -- L1 Context ID. | |
294 | ||
295 | @item | |
296 | @code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR. | |
297 | ||
298 | @item | |
299 | @code{CX8} -- CMPXCHG8B instruction. | |
300 | ||
301 | @item | |
302 | @code{DCA} -- Data prefetch from a memory mapped device. | |
303 | ||
304 | @item | |
305 | @code{DE} -- Debugging Extensions. | |
306 | ||
307 | @item | |
308 | @code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values. | |
309 | ||
310 | @item | |
311 | @code{DS} -- Debug Store. | |
312 | ||
313 | @item | |
314 | @code{DS_CPL} -- CPL Qualified Debug Store. | |
315 | ||
316 | @item | |
317 | @code{DTES64} -- 64-bit DS Area. | |
318 | ||
319 | @item | |
320 | @code{EIST} -- Enhanced Intel SpeedStep technology. | |
321 | ||
322 | @item | |
323 | @code{ENQCMD} -- Enqueue Stores instructions. | |
324 | ||
325 | @item | |
326 | @code{ERMS} -- Enhanced REP MOVSB/STOSB. | |
327 | ||
328 | @item | |
329 | @code{F16C} -- 16-bit floating-point conversion instructions. | |
330 | ||
331 | @item | |
332 | @code{FMA} -- FMA extensions using YMM state. | |
333 | ||
334 | @item | |
335 | @code{FMA4} -- FMA4 instruction extensions. | |
336 | ||
337 | @item | |
338 | @code{FPU} -- X87 Floating Point Unit On-Chip. | |
339 | ||
340 | @item | |
341 | @code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions. | |
342 | ||
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343 | @item |
344 | @code{FSRCS} -- Fast Short REP CMP and SCA. | |
345 | ||
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346 | @item |
347 | @code{FSRM} -- Fast Short REP MOV. | |
348 | ||
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349 | @item |
350 | @code{FSRS} -- Fast Short REP STO. | |
351 | ||
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352 | @item |
353 | @code{FXSR} -- FXSAVE and FXRSTOR instructions. | |
354 | ||
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355 | @item |
356 | @code{FZLRM} -- Fast Zero-Length REP MOV. | |
357 | ||
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358 | @item |
359 | @code{GFNI} -- GFNI instruction extensions. | |
360 | ||
361 | @item | |
362 | @code{HLE} -- HLE instruction extensions. | |
363 | ||
364 | @item | |
365 | @code{HTT} -- Max APIC IDs reserved field is Valid. | |
366 | ||
c712401b L |
367 | @item |
368 | @code{HRESET} -- History reset. | |
369 | ||
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370 | @item |
371 | @code{HYBRID} -- Hybrid processor. | |
372 | ||
373 | @item | |
374 | @code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and | |
375 | the indirect branch predictor barrier (IBPB). | |
376 | ||
377 | @item | |
378 | @code{IBT} -- Intel Indirect Branch Tracking instruction extensions. | |
379 | ||
380 | @item | |
381 | @code{INVARIANT_TSC} -- Invariant TSC. | |
382 | ||
383 | @item | |
384 | @code{INVPCID} -- INVPCID instruction. | |
385 | ||
f2c679d4 L |
386 | @item |
387 | @code{KL} -- AES Key Locker instructions. | |
388 | ||
a2e5da2c L |
389 | @item |
390 | @code{LAM} -- Linear Address Masking. | |
391 | ||
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392 | @item |
393 | @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. | |
394 | ||
395 | @item | |
396 | @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode. | |
397 | ||
398 | @item | |
399 | @code{LM} -- Long mode. | |
400 | ||
401 | @item | |
402 | @code{LWP} -- Lightweight profiling. | |
403 | ||
404 | @item | |
405 | @code{LZCNT} -- LZCNT instruction. | |
406 | ||
407 | @item | |
408 | @code{MCA} -- Machine Check Architecture. | |
409 | ||
410 | @item | |
411 | @code{MCE} -- Machine Check Exception. | |
412 | ||
413 | @item | |
414 | @code{MD_CLEAR} -- MD_CLEAR. | |
415 | ||
416 | @item | |
417 | @code{MMX} -- Intel MMX Technology. | |
418 | ||
419 | @item | |
420 | @code{MONITOR} -- MONITOR/MWAIT instructions. | |
421 | ||
422 | @item | |
423 | @code{MOVBE} -- MOVBE instruction. | |
424 | ||
425 | @item | |
426 | @code{MOVDIRI} -- MOVDIRI instruction. | |
427 | ||
428 | @item | |
429 | @code{MOVDIR64B} -- MOVDIR64B instruction. | |
430 | ||
431 | @item | |
432 | @code{MPX} -- Intel Memory Protection Extensions. | |
433 | ||
434 | @item | |
435 | @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions. | |
436 | ||
437 | @item | |
438 | @code{MTRR} -- Memory Type Range Registers. | |
439 | ||
440 | @item | |
441 | @code{NX} -- No-execute page protection. | |
442 | ||
443 | @item | |
444 | @code{OSPKE} -- OS has set CR4.PKE to enable protection keys. | |
445 | ||
446 | @item | |
447 | @code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable | |
448 | XSETBV/XGETBV instructions to access XCR0 and to support processor | |
449 | extended state management using XSAVE/XRSTOR. | |
450 | ||
451 | @item | |
452 | @code{PAE} -- Physical Address Extension. | |
453 | ||
454 | @item | |
455 | @code{PAGE1GB} -- 1-GByte page. | |
456 | ||
457 | @item | |
458 | @code{PAT} -- Page Attribute Table. | |
459 | ||
460 | @item | |
461 | @code{PBE} -- Pending Break Enable. | |
462 | ||
463 | @item | |
464 | @code{PCID} -- Process-context identifiers. | |
465 | ||
466 | @item | |
467 | @code{PCLMULQDQ} -- PCLMULQDQ instruction. | |
468 | ||
469 | @item | |
470 | @code{PCONFIG} -- PCONFIG instruction. | |
471 | ||
472 | @item | |
473 | @code{PDCM} -- Perfmon and Debug Capability. | |
474 | ||
475 | @item | |
476 | @code{PGE} -- Page Global Bit. | |
477 | ||
478 | @item | |
479 | @code{PKS} -- Protection keys for supervisor-mode pages. | |
480 | ||
481 | @item | |
482 | @code{PKU} -- Protection keys for user-mode pages. | |
483 | ||
484 | @item | |
485 | @code{POPCNT} -- POPCNT instruction. | |
486 | ||
487 | @item | |
488 | @code{PREFETCHW} -- PREFETCHW instruction. | |
489 | ||
490 | @item | |
491 | @code{PREFETCHWT1} -- PREFETCHWT1 instruction. | |
492 | ||
493 | @item | |
494 | @code{PSE} -- Page Size Extension. | |
495 | ||
496 | @item | |
497 | @code{PSE_36} -- 36-Bit Page Size Extension. | |
498 | ||
499 | @item | |
500 | @code{PSN} -- Processor Serial Number. | |
501 | ||
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502 | @item |
503 | @code{PTWRITE} -- PTWRITE instruction. | |
504 | ||
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505 | @item |
506 | @code{RDPID} -- RDPID instruction. | |
507 | ||
508 | @item | |
509 | @code{RDRAND} -- RDRAND instruction. | |
510 | ||
511 | @item | |
512 | @code{RDSEED} -- RDSEED instruction. | |
513 | ||
514 | @item | |
515 | @code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation | |
516 | capability. | |
517 | ||
518 | @item | |
519 | @code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring | |
520 | capability. | |
521 | ||
522 | @item | |
523 | @code{RDTSCP} -- RDTSCP instruction. | |
524 | ||
525 | @item | |
526 | @code{RTM} -- RTM instruction extensions. | |
527 | ||
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528 | @item |
529 | @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable. | |
530 | ||
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531 | @item |
532 | @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug. | |
533 | ||
534 | @item | |
535 | @code{SEP} -- SYSENTER and SYSEXIT instructions. | |
536 | ||
537 | @item | |
538 | @code{SERIALIZE} -- SERIALIZE instruction. | |
539 | ||
540 | @item | |
541 | @code{SGX} -- Intel Software Guard Extensions. | |
542 | ||
543 | @item | |
544 | @code{SGX_LC} -- SGX Launch Configuration. | |
545 | ||
546 | @item | |
547 | @code{SHA} -- SHA instruction extensions. | |
548 | ||
549 | @item | |
550 | @code{SHSTK} -- Intel Shadow Stack instruction extensions. | |
551 | ||
552 | @item | |
553 | @code{SMAP} -- Supervisor-Mode Access Prevention. | |
554 | ||
555 | @item | |
556 | @code{SMEP} -- Supervisor-Mode Execution Prevention. | |
557 | ||
558 | @item | |
559 | @code{SMX} -- Safer Mode Extensions. | |
560 | ||
561 | @item | |
562 | @code{SS} -- Self Snoop. | |
563 | ||
564 | @item | |
565 | @code{SSBD} -- Speculative Store Bypass Disable (SSBD). | |
566 | ||
567 | @item | |
568 | @code{SSE} -- Streaming SIMD Extensions. | |
569 | ||
570 | @item | |
571 | @code{SSE2} -- Streaming SIMD Extensions 2. | |
572 | ||
573 | @item | |
574 | @code{SSE3} -- Streaming SIMD Extensions 3. | |
575 | ||
576 | @item | |
577 | @code{SSE4_1} -- Streaming SIMD Extensions 4.1. | |
578 | ||
579 | @item | |
580 | @code{SSE4_2} -- Streaming SIMD Extensions 4.2. | |
581 | ||
582 | @item | |
583 | @code{SSE4A} -- SSE4A instruction extensions. | |
584 | ||
585 | @item | |
586 | @code{SSSE3} -- Supplemental Streaming SIMD Extensions 3. | |
587 | ||
588 | @item | |
589 | @code{STIBP} -- Single thread indirect branch predictors (STIBP). | |
590 | ||
591 | @item | |
592 | @code{SVM} -- Secure Virtual Machine. | |
593 | ||
594 | @item | |
595 | @code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions. | |
596 | ||
597 | @item | |
598 | @code{TBM} -- Trailing bit manipulation instructions. | |
599 | ||
600 | @item | |
601 | @code{TM} -- Thermal Monitor. | |
602 | ||
603 | @item | |
604 | @code{TM2} -- Thermal Monitor 2. | |
605 | ||
606 | @item | |
607 | @code{TRACE} -- Intel Processor Trace. | |
608 | ||
609 | @item | |
610 | @code{TSC} -- Time Stamp Counter. RDTSC instruction. | |
611 | ||
612 | @item | |
613 | @code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR. | |
614 | ||
615 | @item | |
616 | @code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation | |
617 | using a TSC deadline value. | |
618 | ||
619 | @item | |
620 | @code{TSXLDTRK} -- TSXLDTRK instructions. | |
621 | ||
7674695c L |
622 | @item |
623 | @code{UINTR} -- User interrupts. | |
624 | ||
96203980 L |
625 | @item |
626 | @code{UMIP} -- User-mode instruction prevention. | |
627 | ||
628 | @item | |
629 | @code{VAES} -- VAES instruction extensions. | |
630 | ||
631 | @item | |
632 | @code{VME} -- Virtual 8086 Mode Enhancements. | |
633 | ||
634 | @item | |
635 | @code{VMX} -- Virtual Machine Extensions. | |
636 | ||
637 | @item | |
638 | @code{VPCLMULQDQ} -- VPCLMULQDQ instruction. | |
639 | ||
640 | @item | |
641 | @code{WAITPKG} -- WAITPKG instruction extensions. | |
642 | ||
643 | @item | |
644 | @code{WBNOINVD} -- WBINVD/WBNOINVD instructions. | |
645 | ||
f2c679d4 L |
646 | @item |
647 | @code{WIDE_KL} -- AES wide Key Locker instructions. | |
648 | ||
96203980 L |
649 | @item |
650 | @code{X2APIC} -- x2APIC. | |
651 | ||
652 | @item | |
653 | @code{XFD} -- Extended Feature Disable (XFD). | |
654 | ||
655 | @item | |
656 | @code{XGETBV_ECX_1} -- XGETBV with ECX = 1. | |
657 | ||
658 | @item | |
659 | @code{XOP} -- XOP instruction extensions. | |
660 | ||
661 | @item | |
662 | @code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the | |
663 | XSETBV/XGETBV instructions, and XCR0. | |
664 | ||
665 | @item | |
666 | @code{XSAVEC} -- XSAVEC instruction. | |
667 | ||
668 | @item | |
669 | @code{XSAVEOPT} -- XSAVEOPT instruction. | |
670 | ||
671 | @item | |
672 | @code{XSAVES} -- XSAVES/XRSTORS instructions. | |
673 | ||
674 | @item | |
675 | @code{XTPRUPDCTRL} -- xTPR Update Control. | |
676 | ||
677 | @end itemize | |
678 | ||
679 | You could query if a processor supports @code{AVX} with: | |
680 | ||
681 | @smallexample | |
682 | #include <sys/platform/x86.h> | |
683 | ||
684 | int | |
685 | support_avx (void) | |
686 | @{ | |
687 | return HAS_CPU_FEATURE (AVX); | |
688 | @} | |
689 | @end smallexample | |
690 | ||
691 | and if @code{AVX} is usable with: | |
692 | ||
693 | @smallexample | |
694 | #include <sys/platform/x86.h> | |
695 | ||
696 | int | |
697 | usable_avx (void) | |
698 | @{ | |
699 | return CPU_FEATURE_USABLE (AVX); | |
700 | @} | |
701 | @end smallexample |