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1 | @node Platform, Contributors, Maintenance, Top |
2 | @c %MENU% Describe all platform-specific facilities provided | |
3 | @appendix Platform-specific facilities | |
4 | ||
5 | @Theglibc{} can provide machine-specific functionality. | |
6 | ||
7 | @menu | |
8 | * PowerPC:: Facilities Specific to the PowerPC Architecture | |
ba9e25a6 | 9 | * RISC-V:: Facilities Specific to the RISC-V Architecture |
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10 | @end menu |
11 | ||
12 | @node PowerPC | |
13 | @appendixsec PowerPC-specific Facilities | |
14 | ||
15 | Facilities specific to PowerPC that are not specific to a particular | |
16 | operating system are declared in @file{sys/platform/ppc.h}. | |
17 | ||
18 | @deftypefun {uint64_t} __ppc_get_timebase (void) | |
e2dfb7f4 | 19 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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20 | Read the current value of the Time Base Register. |
21 | ||
22 | The @dfn{Time Base Register} is a 64-bit register that stores a monotonically | |
23 | incremented value updated at a system-dependent frequency that may be | |
24 | different from the processor frequency. More information is available in | |
25 | @cite{Power ISA 2.06b - Book II - Section 5.2}. | |
26 | ||
27 | @code{__ppc_get_timebase} uses the processor's time base facility directly | |
28 | without requiring assistance from the operating system, so it is very | |
29 | efficient. | |
30 | @end deftypefun | |
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31 | |
32 | @deftypefun {uint64_t} __ppc_get_timebase_freq (void) | |
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33 | @safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}} |
34 | @c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd | |
35 | @c __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd | |
36 | @c the initialization of the static timebase_freq is not exactly | |
37 | @c safe, because hp_timing_t cannot be atomically set up. | |
38 | @c syscall:get_tbfreq ok | |
39 | @c open dup @acsfd | |
40 | @c read dup ok | |
41 | @c memcpy dup ok | |
42 | @c memmem dup ok | |
43 | @c close dup @acsfd | |
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44 | Read the current frequency at which the Time Base Register is updated. |
45 | ||
46 | This frequency is not related to the processor clock or the bus clock. | |
47 | It is also possible that this frequency is not constant. More information is | |
48 | available in @cite{Power ISA 2.06b - Book II - Section 5.2}. | |
49 | @end deftypefun | |
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50 | |
51 | The following functions provide hints about the usage of resources that are | |
52 | shared with other processors. They can be used, for example, if a program | |
53 | waiting on a lock intends to divert the shared resources to be used by other | |
54 | processors. More information is available in @cite{Power ISA 2.06b - Book II - | |
55 | Section 3.2}. | |
56 | ||
57 | @deftypefun {void} __ppc_yield (void) | |
e2dfb7f4 | 58 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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59 | Provide a hint that performance will probably be improved if shared resources |
60 | dedicated to the executing processor are released for use by other processors. | |
61 | @end deftypefun | |
62 | ||
63 | @deftypefun {void} __ppc_mdoio (void) | |
e2dfb7f4 | 64 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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65 | Provide a hint that performance will probably be improved if shared resources |
66 | dedicated to the executing processor are released until all outstanding storage | |
67 | accesses to caching-inhibited storage have been completed. | |
68 | @end deftypefun | |
69 | ||
70 | @deftypefun {void} __ppc_mdoom (void) | |
e2dfb7f4 | 71 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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72 | Provide a hint that performance will probably be improved if shared resources |
73 | dedicated to the executing processor are released until all outstanding storage | |
74 | accesses to cacheable storage for which the data is not in the cache have been | |
75 | completed. | |
2b66ef5d | 76 | @end deftypefun |
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77 | |
78 | @deftypefun {void} __ppc_set_ppr_med (void) | |
e2dfb7f4 | 79 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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80 | Set the Program Priority Register to medium value (default). |
81 | ||
82 | The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls | |
83 | the program's priority. By adjusting the PPR value the programmer may | |
84 | improve system throughput by causing the system resources to be used | |
85 | more efficiently, especially in contention situations. | |
86 | The three unprivileged states available are covered by the functions | |
87 | @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low) | |
88 | and @code{__ppc_set_ppc_med_low} (medium low). More information | |
89 | available in @cite{Power ISA 2.06b - Book II - Section 3.1}. | |
90 | @end deftypefun | |
91 | ||
92 | @deftypefun {void} __ppc_set_ppr_low (void) | |
e2dfb7f4 | 93 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
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94 | Set the Program Priority Register to low value. |
95 | @end deftypefun | |
96 | ||
97 | @deftypefun {void} __ppc_set_ppr_med_low (void) | |
e2dfb7f4 | 98 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
d116b7c4 | 99 | Set the Program Priority Register to medium low value. |
9323d39b | 100 | @end deftypefun |
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101 | |
102 | Power ISA 2.07 extends the priorities that can be set to the Program Priority | |
103 | Register (PPR). The following functions implement the new priority levels: | |
104 | very low and medium high. | |
105 | ||
106 | @deftypefun {void} __ppc_set_ppr_very_low (void) | |
107 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} | |
108 | Set the Program Priority Register to very low value. | |
109 | @end deftypefun | |
110 | ||
111 | @deftypefun {void} __ppc_set_ppr_med_high (void) | |
112 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} | |
113 | Set the Program Priority Register to medium high value. The medium high | |
114 | priority is privileged and may only be set during certain time intervals by | |
115 | problem-state programs. If the program priority is medium high when the time | |
116 | interval expires or if an attempt is made to set the priority to medium high | |
117 | when it is not allowed, the priority is set to medium. | |
118 | @end deftypefun | |
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119 | |
120 | @node RISC-V | |
121 | @appendixsec RISC-V-specific Facilities | |
122 | ||
123 | Cache management facilities specific to RISC-V systems that implement the Linux | |
124 | ABI are declared in @file{sys/cachectl.h}. | |
125 | ||
16efad51 | 126 | @deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags}) |
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127 | @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} |
128 | Enforce ordering between stores and instruction cache fetches. The range of | |
129 | addresses over which ordering is enforced is specified by @var{start} and | |
130 | @var{end}. The @var{flags} argument controls the extent of this ordering, with | |
131 | the default behavior (a @var{flags} value of 0) being to enforce the fence on | |
132 | all threads in the current process. Setting the | |
133 | @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing | |
134 | ordering on only the current thread is necessary. All other flag bits are | |
135 | reserved. | |
136 | @end deftypefun |