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887e2ec9 | 1 | /* |
46f37383 | 2 | * (C) Copyright 2006-2008 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <nand.h> | |
c568f77a | 23 | #include <asm/io.h> |
887e2ec9 | 24 | |
6d0f6bcf | 25 | #define CONFIG_SYS_NAND_READ_DELAY \ |
887e2ec9 SR |
26 | { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } |
27 | ||
6d0f6bcf | 28 | static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; |
42be56f5 | 29 | |
6d0f6bcf | 30 | #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) |
46f37383 SR |
31 | /* |
32 | * NAND command for small page NAND devices (512) | |
33 | */ | |
42be56f5 | 34 | static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) |
887e2ec9 | 35 | { |
511d0c72 | 36 | struct nand_chip *this = mtd->priv; |
6d0f6bcf | 37 | int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; |
42be56f5 SR |
38 | |
39 | if (this->dev_ready) | |
c568f77a SR |
40 | while (!this->dev_ready(mtd)) |
41 | ; | |
42be56f5 | 42 | else |
6d0f6bcf | 43 | CONFIG_SYS_NAND_READ_DELAY; |
887e2ec9 SR |
44 | |
45 | /* Begin command latch cycle */ | |
4f32d776 | 46 | this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
887e2ec9 | 47 | /* Set ALE and clear CLE to start address cycle */ |
887e2ec9 | 48 | /* Column address */ |
4f32d776 SW |
49 | this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); |
50 | this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */ | |
51 | this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */ | |
6d0f6bcf | 52 | #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE |
887e2ec9 | 53 | /* One more address cycle for devices > 32MiB */ |
4f32d776 | 54 | this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */ |
887e2ec9 SR |
55 | #endif |
56 | /* Latch in address */ | |
c568f77a | 57 | this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
887e2ec9 SR |
58 | |
59 | /* | |
60 | * Wait a while for the data to be ready | |
61 | */ | |
62 | if (this->dev_ready) | |
c568f77a SR |
63 | while (!this->dev_ready(mtd)) |
64 | ; | |
887e2ec9 | 65 | else |
6d0f6bcf | 66 | CONFIG_SYS_NAND_READ_DELAY; |
887e2ec9 | 67 | |
42be56f5 SR |
68 | return 0; |
69 | } | |
46f37383 SR |
70 | #else |
71 | /* | |
72 | * NAND command for large page NAND devices (2k) | |
73 | */ | |
74 | static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) | |
75 | { | |
76 | struct nand_chip *this = mtd->priv; | |
6d0f6bcf | 77 | int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; |
46f37383 SR |
78 | |
79 | if (this->dev_ready) | |
4f32d776 SW |
80 | while (!this->dev_ready(mtd)) |
81 | ; | |
46f37383 | 82 | else |
6d0f6bcf | 83 | CONFIG_SYS_NAND_READ_DELAY; |
46f37383 SR |
84 | |
85 | /* Emulate NAND_CMD_READOOB */ | |
86 | if (cmd == NAND_CMD_READOOB) { | |
6d0f6bcf | 87 | offs += CONFIG_SYS_NAND_PAGE_SIZE; |
46f37383 SR |
88 | cmd = NAND_CMD_READ0; |
89 | } | |
90 | ||
91 | /* Begin command latch cycle */ | |
4f32d776 | 92 | this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
46f37383 | 93 | /* Set ALE and clear CLE to start address cycle */ |
46f37383 | 94 | /* Column address */ |
4f32d776 | 95 | this->cmd_ctrl(mtd, offs & 0xff, |
4b070809 | 96 | NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ |
4f32d776 | 97 | this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */ |
46f37383 | 98 | /* Row address */ |
4f32d776 SW |
99 | this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */ |
100 | this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */ | |
6d0f6bcf | 101 | #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE |
46f37383 | 102 | /* One more address cycle for devices > 128MiB */ |
4f32d776 | 103 | this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */ |
46f37383 SR |
104 | #endif |
105 | /* Latch in address */ | |
4f32d776 | 106 | this->cmd_ctrl(mtd, NAND_CMD_READSTART, |
4b070809 | 107 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
4f32d776 | 108 | this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
46f37383 SR |
109 | |
110 | /* | |
111 | * Wait a while for the data to be ready | |
112 | */ | |
113 | if (this->dev_ready) | |
4f32d776 SW |
114 | while (!this->dev_ready(mtd)) |
115 | ; | |
46f37383 | 116 | else |
6d0f6bcf | 117 | CONFIG_SYS_NAND_READ_DELAY; |
46f37383 SR |
118 | |
119 | return 0; | |
120 | } | |
121 | #endif | |
42be56f5 SR |
122 | |
123 | static int nand_is_bad_block(struct mtd_info *mtd, int block) | |
124 | { | |
125 | struct nand_chip *this = mtd->priv; | |
126 | ||
6d0f6bcf | 127 | nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); |
42be56f5 | 128 | |
887e2ec9 | 129 | /* |
10c7382b | 130 | * Read one byte |
887e2ec9 | 131 | */ |
aa646643 | 132 | if (readb(this->IO_ADDR_R) != 0xff) |
887e2ec9 SR |
133 | return 1; |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) | |
139 | { | |
511d0c72 | 140 | struct nand_chip *this = mtd->priv; |
42be56f5 SR |
141 | u_char *ecc_calc; |
142 | u_char *ecc_code; | |
143 | u_char *oob_data; | |
887e2ec9 | 144 | int i; |
6d0f6bcf JCPV |
145 | int eccsize = CONFIG_SYS_NAND_ECCSIZE; |
146 | int eccbytes = CONFIG_SYS_NAND_ECCBYTES; | |
147 | int eccsteps = CONFIG_SYS_NAND_ECCSTEPS; | |
42be56f5 SR |
148 | uint8_t *p = dst; |
149 | int stat; | |
887e2ec9 | 150 | |
42be56f5 | 151 | nand_command(mtd, block, page, 0, NAND_CMD_READ0); |
887e2ec9 | 152 | |
42be56f5 SR |
153 | /* No malloc available for now, just use some temporary locations |
154 | * in SDRAM | |
887e2ec9 | 155 | */ |
6d0f6bcf | 156 | ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000); |
42be56f5 SR |
157 | ecc_code = ecc_calc + 0x100; |
158 | oob_data = ecc_calc + 0x200; | |
159 | ||
160 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
c568f77a | 161 | this->ecc.hwctl(mtd, NAND_ECC_READ); |
42be56f5 | 162 | this->read_buf(mtd, p, eccsize); |
c568f77a | 163 | this->ecc.calculate(mtd, p, &ecc_calc[i]); |
42be56f5 | 164 | } |
6d0f6bcf | 165 | this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); |
42be56f5 SR |
166 | |
167 | /* Pick the ECC bytes out of the oob data */ | |
6d0f6bcf | 168 | for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++) |
42be56f5 SR |
169 | ecc_code[i] = oob_data[nand_ecc_pos[i]]; |
170 | ||
6d0f6bcf | 171 | eccsteps = CONFIG_SYS_NAND_ECCSTEPS; |
42be56f5 SR |
172 | p = dst; |
173 | ||
174 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
175 | /* No chance to do something with the possible error message | |
176 | * from correct_data(). We just hope that all possible errors | |
177 | * are corrected by this routine. | |
178 | */ | |
c568f77a | 179 | stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
42be56f5 | 180 | } |
887e2ec9 SR |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
aa646643 | 185 | static int nand_load(struct mtd_info *mtd, unsigned int offs, |
4b070809 | 186 | unsigned int uboot_size, uchar *dst) |
887e2ec9 | 187 | { |
aa646643 GL |
188 | unsigned int block, lastblock; |
189 | unsigned int page; | |
887e2ec9 SR |
190 | |
191 | /* | |
aa646643 | 192 | * offs has to be aligned to a page address! |
887e2ec9 | 193 | */ |
6d0f6bcf JCPV |
194 | block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; |
195 | lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; | |
196 | page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; | |
887e2ec9 | 197 | |
aa646643 | 198 | while (block <= lastblock) { |
887e2ec9 SR |
199 | if (!nand_is_bad_block(mtd, block)) { |
200 | /* | |
201 | * Skip bad blocks | |
202 | */ | |
6d0f6bcf | 203 | while (page < CONFIG_SYS_NAND_PAGE_COUNT) { |
887e2ec9 | 204 | nand_read_page(mtd, block, page, dst); |
6d0f6bcf | 205 | dst += CONFIG_SYS_NAND_PAGE_SIZE; |
aa646643 | 206 | page++; |
887e2ec9 SR |
207 | } |
208 | ||
aa646643 GL |
209 | page = 0; |
210 | } else { | |
211 | lastblock++; | |
887e2ec9 SR |
212 | } |
213 | ||
214 | block++; | |
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
64852d09 SR |
220 | /* |
221 | * The main entry for NAND booting. It's necessary that SDRAM is already | |
222 | * configured and available since this code loads the main U-Boot image | |
223 | * from NAND into SDRAM and starts it from there. | |
224 | */ | |
887e2ec9 SR |
225 | void nand_boot(void) |
226 | { | |
887e2ec9 SR |
227 | struct nand_chip nand_chip; |
228 | nand_info_t nand_info; | |
229 | int ret; | |
e4c09508 | 230 | __attribute__((noreturn)) void (*uboot)(void); |
887e2ec9 | 231 | |
887e2ec9 SR |
232 | /* |
233 | * Init board specific nand support | |
234 | */ | |
235 | nand_info.priv = &nand_chip; | |
6d0f6bcf | 236 | nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; |
887e2ec9 SR |
237 | nand_chip.dev_ready = NULL; /* preset to NULL */ |
238 | board_nand_init(&nand_chip); | |
239 | ||
aa646643 GL |
240 | if (nand_chip.select_chip) |
241 | nand_chip.select_chip(&nand_info, 0); | |
242 | ||
887e2ec9 SR |
243 | /* |
244 | * Load U-Boot image from NAND into RAM | |
245 | */ | |
6d0f6bcf JCPV |
246 | ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, |
247 | (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); | |
887e2ec9 | 248 | |
aa646643 GL |
249 | if (nand_chip.select_chip) |
250 | nand_chip.select_chip(&nand_info, -1); | |
251 | ||
887e2ec9 SR |
252 | /* |
253 | * Jump to U-Boot image | |
254 | */ | |
6d0f6bcf | 255 | uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; |
887e2ec9 SR |
256 | (*uboot)(); |
257 | } |