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781b52c5 | 1 | /* FPU control word bits. Mips version. |
568035b7 | 2 | Copyright (C) 1996-2013 Free Software Foundation, Inc. |
781b52c5 | 3 | This file is part of the GNU C Library. |
bd4c4968 | 4 | Contributed by Olaf Flebbe and Ralf Baechle. |
781b52c5 UD |
5 | |
6 | The GNU C Library is free software; you can redistribute it and/or | |
3214b89b AJ |
7 | modify it under the terms of the GNU Lesser General Public |
8 | License as published by the Free Software Foundation; either | |
9 | version 2.1 of the License, or (at your option) any later version. | |
781b52c5 UD |
10 | |
11 | The GNU C Library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
3214b89b | 14 | Lesser General Public License for more details. |
781b52c5 | 15 | |
3214b89b | 16 | You should have received a copy of the GNU Lesser General Public |
ab84e3ff PE |
17 | License along with the GNU C Library. If not, see |
18 | <http://www.gnu.org/licenses/>. */ | |
781b52c5 UD |
19 | |
20 | #ifndef _FPU_CONTROL_H | |
21 | #define _FPU_CONTROL_H | |
22 | ||
bd4c4968 | 23 | /* MIPS FPU floating point control register bits. |
781b52c5 | 24 | * |
bd4c4968 UD |
25 | * 31-25 -> floating point conditions code bits 7-1. These bits are only |
26 | * available in MIPS IV. | |
27 | * 24 -> flush denormalized results to zero instead of | |
28 | * causing unimplemented operation exception. This bit is only | |
29 | * available for MIPS III and newer. | |
30 | * 23 -> Condition bit | |
31 | * 22-18 -> reserved (read as 0, write with 0) | |
32 | * 17 -> cause bit for unimplemented operation | |
33 | * 16 -> cause bit for invalid exception | |
34 | * 15 -> cause bit for division by zero exception | |
35 | * 14 -> cause bit for overflow exception | |
36 | * 13 -> cause bit for underflow exception | |
37 | * 12 -> cause bit for inexact exception | |
38 | * 11 -> enable exception for invalid exception | |
39 | * 10 -> enable exception for division by zero exception | |
40 | * 9 -> enable exception for overflow exception | |
41 | * 8 -> enable exception for underflow exception | |
42 | * 7 -> enable exception for inexact exception | |
43 | * 6 -> flag invalid exception | |
44 | * 5 -> flag division by zero exception | |
45 | * 4 -> flag overflow exception | |
46 | * 3 -> flag underflow exception | |
47 | * 2 -> flag inexact exception | |
48 | * 1-0 -> rounding control | |
781b52c5 | 49 | * |
781b52c5 | 50 | * |
bd4c4968 UD |
51 | * Rounding Control: |
52 | * 00 - rounding to nearest (RN) | |
53 | * 01 - rounding toward zero (RZ) | |
93835354 | 54 | * 10 - rounding (up) toward plus infinity (RP) |
bd4c4968 | 55 | * 11 - rounding (down)toward minus infinity (RM) |
781b52c5 UD |
56 | */ |
57 | ||
58 | #include <features.h> | |
59 | ||
6b4d184d DJ |
60 | #ifdef __mips_soft_float |
61 | ||
62 | #define _FPU_RESERVED 0xffffffff | |
63 | #define _FPU_DEFAULT 0x00000000 | |
64 | typedef unsigned int fpu_control_t; | |
0993dd9b JM |
65 | #define _FPU_GETCW(cw) (cw) = 0 |
66 | #define _FPU_SETCW(cw) (void) (cw) | |
6b4d184d DJ |
67 | extern fpu_control_t __fpu_control; |
68 | ||
69 | #else /* __mips_soft_float */ | |
70 | ||
781b52c5 | 71 | /* masking of interrupts */ |
bd4c4968 UD |
72 | #define _FPU_MASK_V 0x0800 /* Invalid operation */ |
73 | #define _FPU_MASK_Z 0x0400 /* Division by zero */ | |
74 | #define _FPU_MASK_O 0x0200 /* Overflow */ | |
75 | #define _FPU_MASK_U 0x0100 /* Underflow */ | |
76 | #define _FPU_MASK_I 0x0080 /* Inexact operation */ | |
77 | ||
78 | /* flush denormalized numbers to zero */ | |
79 | #define _FPU_FLUSH_TZ 0x1000000 | |
781b52c5 UD |
80 | |
81 | /* rounding control */ | |
bd4c4968 | 82 | #define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */ |
781b52c5 | 83 | #define _FPU_RC_ZERO 0x1 |
bd4c4968 UD |
84 | #define _FPU_RC_UP 0x2 |
85 | #define _FPU_RC_DOWN 0x3 | |
781b52c5 | 86 | |
89570c62 | 87 | #define _FPU_RESERVED 0xfebc0000 /* Reserved bits in cw */ |
781b52c5 UD |
88 | |
89 | ||
90 | /* The fdlibm code requires strict IEEE double precision arithmetic, | |
91 | and no interrupts for exceptions, rounding to nearest. */ | |
92 | ||
1599a5f3 | 93 | #define _FPU_DEFAULT 0x00000000 |
781b52c5 UD |
94 | |
95 | /* IEEE: same as above, but exceptions */ | |
bd4c4968 | 96 | #define _FPU_IEEE 0x00000F80 |
781b52c5 UD |
97 | |
98 | /* Type of the control word. */ | |
6964aca3 | 99 | typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__))); |
781b52c5 UD |
100 | |
101 | /* Macros for accessing the hardware control word. */ | |
43301bd3 MR |
102 | extern fpu_control_t __mips_fpu_getcw (void) __THROW; |
103 | extern void __mips_fpu_setcw (fpu_control_t) __THROW; | |
104 | #ifdef __mips16 | |
105 | # define _FPU_GETCW(cw) do { (cw) = __mips_fpu_getcw (); } while (0) | |
106 | # define _FPU_SETCW(cw) __mips_fpu_setcw (cw) | |
107 | #else | |
108 | # define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw)) | |
109 | # define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw)) | |
110 | #endif | |
781b52c5 UD |
111 | |
112 | /* Default control word set at startup. */ | |
113 | extern fpu_control_t __fpu_control; | |
114 | ||
6b4d184d DJ |
115 | #endif /* __mips_soft_float */ |
116 | ||
781b52c5 | 117 | #endif /* fpu_control.h */ |