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1 | /* |
2 | * PCMCIA bridge device probe | |
3 | * | |
4 | * This file is part of the IPCop Firewall. | |
5 | * | |
6 | * IPCop is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * IPCop is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with IPCop; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * The initial developer of the original code is David A. Hinds | |
21 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds | |
22 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. | |
23 | * | |
24 | * $Id: pcmcia.h,v 1.1 2004/01/25 09:34:59 riddles Exp $ | |
25 | * | |
26 | */ | |
27 | ||
28 | #define TCIC_BASE 0x240 | |
29 | ||
30 | /* offsets of registers from TCIC_BASE */ | |
31 | #define TCIC_DATA 0x00 | |
32 | #define TCIC_ADDR 0x02 | |
33 | #define TCIC_SCTRL 0x06 | |
34 | #define TCIC_SSTAT 0x07 | |
35 | #define TCIC_MODE 0x08 | |
36 | #define TCIC_PWR 0x09 | |
37 | #define TCIC_EDC 0x0A | |
38 | #define TCIC_ICSR 0x0C | |
39 | #define TCIC_IENA 0x0D | |
40 | #define TCIC_AUX 0x0E | |
41 | ||
42 | #define TCIC_SS_SHFT 12 | |
43 | #define TCIC_SS_MASK 0x7000 | |
44 | ||
45 | /* Flags for TCIC_ADDR */ | |
46 | #define TCIC_ADR2_REG 0x8000 | |
47 | #define TCIC_ADR2_INDREG 0x0800 | |
48 | ||
49 | #define TCIC_ADDR_REG 0x80000000 | |
50 | #define TCIC_ADDR_SS_SHFT (TCIC_SS_SHFT+16) | |
51 | #define TCIC_ADDR_SS_MASK (TCIC_SS_MASK<<16) | |
52 | #define TCIC_ADDR_INDREG 0x08000000 | |
53 | #define TCIC_ADDR_IO 0x04000000 | |
54 | #define TCIC_ADDR_MASK 0x03ffffff | |
55 | ||
56 | /* Flags for TCIC_SCTRL */ | |
57 | #define TCIC_SCTRL_ENA 0x01 | |
58 | #define TCIC_SCTRL_INCMODE 0x18 | |
59 | #define TCIC_SCTRL_INCMODE_HOLD 0x00 | |
60 | #define TCIC_SCTRL_INCMODE_WORD 0x08 | |
61 | #define TCIC_SCTRL_INCMODE_REG 0x10 | |
62 | #define TCIC_SCTRL_INCMODE_AUTO 0x18 | |
63 | #define TCIC_SCTRL_EDCSUM 0x20 | |
64 | #define TCIC_SCTRL_RESET 0x80 | |
65 | ||
66 | /* Flags for TCIC_SSTAT */ | |
67 | #define TCIC_SSTAT_6US 0x01 | |
68 | #define TCIC_SSTAT_10US 0x02 | |
69 | #define TCIC_SSTAT_PROGTIME 0x04 | |
70 | #define TCIC_SSTAT_LBAT1 0x08 | |
71 | #define TCIC_SSTAT_LBAT2 0x10 | |
72 | #define TCIC_SSTAT_RDY 0x20 /* Inverted */ | |
73 | #define TCIC_SSTAT_WP 0x40 | |
74 | #define TCIC_SSTAT_CD 0x80 /* Card detect */ | |
75 | ||
76 | /* Flags for TCIC_MODE */ | |
77 | #define TCIC_MODE_PGMMASK 0x1f | |
78 | #define TCIC_MODE_NORMAL 0x00 | |
79 | #define TCIC_MODE_PGMWR 0x01 | |
80 | #define TCIC_MODE_PGMRD 0x02 | |
81 | #define TCIC_MODE_PGMCE 0x04 | |
82 | #define TCIC_MODE_PGMDBW 0x08 | |
83 | #define TCIC_MODE_PGMWORD 0x10 | |
84 | #define TCIC_MODE_AUXSEL_MASK 0xe0 | |
85 | ||
86 | /* Registers accessed through TCIC_AUX, by setting TCIC_MODE */ | |
87 | #define TCIC_AUX_TCTL (0<<5) | |
88 | #define TCIC_AUX_PCTL (1<<5) | |
89 | #define TCIC_AUX_WCTL (2<<5) | |
90 | #define TCIC_AUX_EXTERN (3<<5) | |
91 | #define TCIC_AUX_PDATA (4<<5) | |
92 | #define TCIC_AUX_SYSCFG (5<<5) | |
93 | #define TCIC_AUX_ILOCK (6<<5) | |
94 | #define TCIC_AUX_TEST (7<<5) | |
95 | ||
96 | /* Flags for TCIC_PWR */ | |
97 | #define TCIC_PWR_VCC(sock) (0x01<<(sock)) | |
98 | #define TCIC_PWR_VCC_MASK 0x03 | |
99 | #define TCIC_PWR_VPP(sock) (0x08<<(sock)) | |
100 | #define TCIC_PWR_VPP_MASK 0x18 | |
101 | #define TCIC_PWR_CLIMENA 0x40 | |
102 | #define TCIC_PWR_CLIMSTAT 0x80 | |
103 | ||
104 | /* Flags for TCIC_ICSR */ | |
105 | #define TCIC_ICSR_CLEAR 0x01 | |
106 | #define TCIC_ICSR_SET 0x02 | |
107 | #define TCIC_ICSR_JAM (TCIC_ICSR_CLEAR|TCIC_ICSR_SET) | |
108 | #define TCIC_ICSR_STOPCPU 0x04 | |
109 | #define TCIC_ICSR_ILOCK 0x08 | |
110 | #define TCIC_ICSR_PROGTIME 0x10 | |
111 | #define TCIC_ICSR_ERR 0x20 | |
112 | #define TCIC_ICSR_CDCHG 0x40 | |
113 | #define TCIC_ICSR_IOCHK 0x80 | |
114 | ||
115 | /* Flags for TCIC_IENA */ | |
116 | #define TCIC_IENA_CFG_MASK 0x03 | |
117 | #define TCIC_IENA_CFG_OFF 0x00 /* disabled */ | |
118 | #define TCIC_IENA_CFG_OD 0x01 /* active low, open drain */ | |
119 | #define TCIC_IENA_CFG_LOW 0x02 /* active low, totem pole */ | |
120 | #define TCIC_IENA_CFG_HIGH 0x03 /* active high, totem pole */ | |
121 | #define TCIC_IENA_ILOCK 0x08 | |
122 | #define TCIC_IENA_PROGTIME 0x10 | |
123 | #define TCIC_IENA_ERR 0x20 /* overcurrent or iochk */ | |
124 | #define TCIC_IENA_CDCHG 0x40 | |
125 | ||
126 | /* Flags for TCIC_AUX_WCTL */ | |
127 | #define TCIC_WAIT_COUNT_MASK 0x001f | |
128 | #define TCIC_WAIT_ASYNC 0x0020 | |
129 | #define TCIC_WAIT_SENSE 0x0040 | |
130 | #define TCIC_WAIT_SRC 0x0080 | |
131 | #define TCIC_WCTL_WR 0x0100 | |
132 | #define TCIC_WCTL_RD 0x0200 | |
133 | #define TCIC_WCTL_CE 0x0400 | |
134 | #define TCIC_WCTL_LLBAT1 0x0800 | |
135 | #define TCIC_WCTL_LLBAT2 0x1000 | |
136 | #define TCIC_WCTL_LRDY 0x2000 | |
137 | #define TCIC_WCTL_LWP 0x4000 | |
138 | #define TCIC_WCTL_LCD 0x8000 | |
139 | ||
140 | /* Flags for TCIC_AUX_SYSCFG */ | |
141 | #define TCIC_SYSCFG_IRQ_MASK 0x000f | |
142 | #define TCIC_SYSCFG_MCSFULL 0x0010 | |
143 | #define TCIC_SYSCFG_IO1723 0x0020 | |
144 | #define TCIC_SYSCFG_MCSXB 0x0040 | |
145 | #define TCIC_SYSCFG_ICSXB 0x0080 | |
146 | #define TCIC_SYSCFG_NOPDN 0x0100 | |
147 | #define TCIC_SYSCFG_MPSEL_SHFT 9 | |
148 | #define TCIC_SYSCFG_MPSEL_MASK 0x0e00 | |
149 | #define TCIC_SYSCFG_MPSENSE 0x2000 | |
150 | #define TCIC_SYSCFG_AUTOBUSY 0x4000 | |
151 | #define TCIC_SYSCFG_ACC 0x8000 | |
152 | ||
153 | #define TCIC_ILOCK_OUT 0x01 | |
154 | #define TCIC_ILOCK_SENSE 0x02 | |
155 | #define TCIC_ILOCK_CRESET 0x04 | |
156 | #define TCIC_ILOCK_CRESENA 0x08 | |
157 | #define TCIC_ILOCK_CWAIT 0x10 | |
158 | #define TCIC_ILOCK_CWAITSNS 0x20 | |
159 | #define TCIC_ILOCK_HOLD_MASK 0xc0 | |
160 | #define TCIC_ILOCK_HOLD_CCLK 0xc0 | |
161 | ||
162 | #define TCIC_ILOCKTEST_ID_SH 8 | |
163 | #define TCIC_ILOCKTEST_ID_MASK 0x7f00 | |
164 | #define TCIC_ILOCKTEST_MCIC_1 0x8000 | |
165 | ||
166 | #define TCIC_ID_DB86082 0x02 | |
167 | #define TCIC_ID_DB86082A 0x03 | |
168 | #define TCIC_ID_DB86084 0x04 | |
169 | #define TCIC_ID_DB86084A 0x08 | |
170 | #define TCIC_ID_DB86072 0x15 | |
171 | #define TCIC_ID_DB86184 0x14 | |
172 | #define TCIC_ID_DB86082B 0x17 | |
173 | ||
174 | #define TCIC_TEST_DIAG 0x8000 | |
175 | ||
176 | /* | |
177 | * Indirectly addressed registers | |
178 | */ | |
179 | ||
180 | #define TCIC_SCF1(sock) ((sock)<<3) | |
181 | #define TCIC_SCF2(sock) (((sock)<<3)+2) | |
182 | ||
183 | /* Flags for SCF1 */ | |
184 | #define TCIC_SCF1_IRQ_MASK 0x000f | |
185 | #define TCIC_SCF1_IRQ_OFF 0x0000 | |
186 | #define TCIC_SCF1_IRQOC 0x0010 | |
187 | #define TCIC_SCF1_PCVT 0x0020 | |
188 | #define TCIC_SCF1_IRDY 0x0040 | |
189 | #define TCIC_SCF1_ATA 0x0080 | |
190 | #define TCIC_SCF1_DMA_SHIFT 8 | |
191 | #define TCIC_SCF1_DMA_MASK 0x0700 | |
192 | #define TCIC_SCF1_DMA_OFF 0 | |
193 | #define TCIC_SCF1_DREQ2 2 | |
194 | #define TCIC_SCF1_IOSTS 0x0800 | |
195 | #define TCIC_SCF1_SPKR 0x1000 | |
196 | #define TCIC_SCF1_FINPACK 0x2000 | |
197 | #define TCIC_SCF1_DELWR 0x4000 | |
198 | #define TCIC_SCF1_HD7IDE 0x8000 | |
199 | ||
200 | /* Flags for SCF2 */ | |
201 | #define TCIC_SCF2_RI 0x0001 | |
202 | #define TCIC_SCF2_IDBR 0x0002 | |
203 | #define TCIC_SCF2_MDBR 0x0004 | |
204 | #define TCIC_SCF2_MLBAT1 0x0008 | |
205 | #define TCIC_SCF2_MLBAT2 0x0010 | |
206 | #define TCIC_SCF2_MRDY 0x0020 | |
207 | #define TCIC_SCF2_MWP 0x0040 | |
208 | #define TCIC_SCF2_MCD 0x0080 | |
209 | #define TCIC_SCF2_MALL 0x00f8 | |
210 | ||
211 | /* Indirect addresses for memory window registers */ | |
212 | #define TCIC_MWIN(sock,map) (0x100+(((map)+((sock)<<2))<<3)) | |
213 | #define TCIC_MBASE_X 2 | |
214 | #define TCIC_MMAP_X 4 | |
215 | #define TCIC_MCTL_X 6 | |
216 | ||
217 | #define TCIC_MBASE_4K_BIT 0x4000 | |
218 | #define TCIC_MBASE_HA_SHFT 12 | |
219 | #define TCIC_MBASE_HA_MASK 0x0fff | |
220 | ||
221 | #define TCIC_MMAP_REG 0x8000 | |
222 | #define TCIC_MMAP_CA_SHFT 12 | |
223 | #define TCIC_MMAP_CA_MASK 0x3fff | |
224 | ||
225 | #define TCIC_MCTL_WSCNT_MASK 0x001f | |
226 | #define TCIC_MCTL_WCLK 0x0020 | |
227 | #define TCIC_MCTL_WCLK_CCLK 0x0000 | |
228 | #define TCIC_MCTL_WCLK_BCLK 0x0020 | |
229 | #define TCIC_MCTL_QUIET 0x0040 | |
230 | #define TCIC_MCTL_WP 0x0080 | |
231 | #define TCIC_MCTL_ACC 0x0100 | |
232 | #define TCIC_MCTL_KE 0x0200 | |
233 | #define TCIC_MCTL_EDC 0x0400 | |
234 | #define TCIC_MCTL_B8 0x0800 | |
235 | #define TCIC_MCTL_SS_SHFT TCIC_SS_SHFT | |
236 | #define TCIC_MCTL_SS_MASK TCIC_SS_MASK | |
237 | #define TCIC_MCTL_ENA 0x8000 | |
238 | ||
239 | /* Indirect addresses for I/O window registers */ | |
240 | #define TCIC_IWIN(sock,map) (0x200+(((map)+((sock)<<1))<<2)) | |
241 | #define TCIC_IBASE_X 0 | |
242 | #define TCIC_ICTL_X 2 | |
243 | ||
244 | #define TCIC_ICTL_WSCNT_MASK TCIC_MCTL_WSCNT_MASK | |
245 | #define TCIC_ICTL_QUIET TCIC_MCTL_QUIET | |
246 | #define TCIC_ICTL_1K 0x0080 | |
247 | #define TCIC_ICTL_PASS16 0x0100 | |
248 | #define TCIC_ICTL_ACC TCIC_MCTL_ACC | |
249 | #define TCIC_ICTL_TINY 0x0200 | |
250 | #define TCIC_ICTL_B16 0x0400 | |
251 | #define TCIC_ICTL_B8 TCIC_MCTL_B8 | |
252 | #define TCIC_ICTL_BW_MASK (TCIC_ICTL_B16|TCIC_ICTL_B8) | |
253 | #define TCIC_ICTL_BW_DYN 0 | |
254 | #define TCIC_ICTL_BW_8 TCIC_ICTL_B8 | |
255 | #define TCIC_ICTL_BW_16 TCIC_ICTL_B16 | |
256 | #define TCIC_ICTL_BW_ATA (TCIC_ICTL_B16|TCIC_ICTL_B8) | |
257 | #define TCIC_ICTL_SS_SHFT TCIC_SS_SHFT | |
258 | #define TCIC_ICTL_SS_MASK TCIC_SS_MASK | |
259 | #define TCIC_ICTL_ENA TCIC_MCTL_ENA | |
260 | ||
261 | /* register definitions for the Intel 82365SL PCMCIA controller */ | |
262 | ||
263 | /* Offsets for PCIC registers */ | |
264 | #define I365_IDENT 0x00 /* Identification and revision */ | |
265 | #define I365_STATUS 0x01 /* Interface status */ | |
266 | #define I365_POWER 0x02 /* Power and RESETDRV control */ | |
267 | #define I365_INTCTL 0x03 /* Interrupt and general control */ | |
268 | #define I365_CSC 0x04 /* Card status change */ | |
269 | #define I365_CSCINT 0x05 /* Card status change interrupt control */ | |
270 | #define I365_ADDRWIN 0x06 /* Address window enable */ | |
271 | #define I365_IOCTL 0x07 /* I/O control */ | |
272 | #define I365_GENCTL 0x16 /* Card detect and general control */ | |
273 | #define I365_GBLCTL 0x1E /* Global control register */ | |
274 | ||
275 | /* Offsets for I/O and memory window registers */ | |
276 | #define I365_IO(map) (0x08+((map)<<2)) | |
277 | #define I365_MEM(map) (0x10+((map)<<3)) | |
278 | #define I365_W_START 0 | |
279 | #define I365_W_STOP 2 | |
280 | #define I365_W_OFF 4 | |
281 | ||
282 | /* Flags for I365_STATUS */ | |
283 | #define I365_CS_BVD1 0x01 | |
284 | #define I365_CS_STSCHG 0x01 | |
285 | #define I365_CS_BVD2 0x02 | |
286 | #define I365_CS_SPKR 0x02 | |
287 | #define I365_CS_DETECT 0x0C | |
288 | #define I365_CS_WRPROT 0x10 | |
289 | #define I365_CS_READY 0x20 /* Inverted */ | |
290 | #define I365_CS_POWERON 0x40 | |
291 | #define I365_CS_GPI 0x80 | |
292 | ||
293 | /* Flags for I365_POWER */ | |
294 | #define I365_PWR_OFF 0x00 /* Turn off the socket */ | |
295 | #define I365_PWR_OUT 0x80 /* Output enable */ | |
296 | #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ | |
297 | #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ | |
298 | #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ | |
299 | /* There are different layouts for B-step and DF-step chips: the B | |
300 | step has independent Vpp1/Vpp2 control, and the DF step has only | |
301 | Vpp1 control, plus 3V control */ | |
302 | #define I365_VCC_5V 0x10 /* Vcc = 5.0v */ | |
303 | #define I365_VCC_3V 0x18 /* Vcc = 3.3v */ | |
304 | #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ | |
305 | #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ | |
306 | #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ | |
307 | #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ | |
308 | #define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */ | |
309 | #define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */ | |
310 | ||
311 | /* Flags for I365_INTCTL */ | |
312 | #define I365_RING_ENA 0x80 | |
313 | #define I365_PC_RESET 0x40 | |
314 | #define I365_PC_IOCARD 0x20 | |
315 | #define I365_INTR_ENA 0x10 | |
316 | #define I365_IRQ_MASK 0x0F | |
317 | ||
318 | /* Flags for I365_CSC and I365_CSCINT*/ | |
319 | #define I365_CSC_BVD1 0x01 | |
320 | #define I365_CSC_STSCHG 0x01 | |
321 | #define I365_CSC_BVD2 0x02 | |
322 | #define I365_CSC_READY 0x04 | |
323 | #define I365_CSC_DETECT 0x08 | |
324 | #define I365_CSC_ANY 0x0F | |
325 | #define I365_CSC_GPI 0x10 | |
326 | ||
327 | /* Flags for I365_ADDRWIN */ | |
328 | #define I365_ADDR_MEMCS16 0x20 | |
329 | #define I365_ENA_IO(map) (0x40 << (map)) | |
330 | #define I365_ENA_MEM(map) (0x01 << (map)) | |
331 | ||
332 | /* Flags for I365_IOCTL */ | |
333 | #define I365_IOCTL_MASK(map) (0x0F << (map<<2)) | |
334 | #define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) | |
335 | #define I365_IOCTL_0WS(map) (0x04 << (map<<2)) | |
336 | #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) | |
337 | #define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) | |
338 | ||
339 | /* Flags for I365_GENCTL */ | |
340 | #define I365_CTL_16DELAY 0x01 | |
341 | #define I365_CTL_RESET 0x02 | |
342 | #define I365_CTL_GPI_ENA 0x04 | |
343 | #define I365_CTL_GPI_CTL 0x08 | |
344 | #define I365_CTL_RESUME 0x10 | |
345 | #define I365_CTL_SW_IRQ 0x20 | |
346 | ||
347 | /* Flags for I365_GBLCTL */ | |
348 | #define I365_GBL_PWRDOWN 0x01 | |
349 | #define I365_GBL_CSC_LEV 0x02 | |
350 | #define I365_GBL_WRBACK 0x04 | |
351 | #define I365_GBL_IRQ_0_LEV 0x08 | |
352 | #define I365_GBL_IRQ_1_LEV 0x10 | |
353 | ||
354 | /* Flags for memory window registers */ | |
355 | #define I365_MEM_16BIT 0x8000 /* In memory start high byte */ | |
356 | #define I365_MEM_0WS 0x4000 | |
357 | #define I365_MEM_WS1 0x8000 /* In memory stop high byte */ | |
358 | #define I365_MEM_WS0 0x4000 | |
359 | #define I365_MEM_WRPROT 0x8000 /* In offset high byte */ | |
360 | #define I365_MEM_REG 0x4000 | |
361 | ||
362 | #define I365_REG(slot, reg) (((slot) << 6) | (reg)) | |
363 | ||
364 | /* Default ISA interrupt mask */ | |
365 | #define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */ | |
366 | ||
367 | /* Device ID's for PCI-to-PCMCIA bridges */ | |
368 | ||
369 | #ifndef PCI_VENDOR_ID_INTEL | |
370 | #define PCI_VENDOR_ID_INTEL 0x8086 | |
371 | #endif | |
372 | #ifndef PCI_DEVICE_ID_INTEL_82092AA_0 | |
373 | #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 | |
374 | #endif | |
375 | #ifndef PCI_VENDOR_ID_OMEGA | |
376 | #define PCI_VENDOR_ID_OMEGA 0x119b | |
377 | #endif | |
378 | #ifndef PCI_DEVICE_ID_OMEGA_82C092G | |
379 | #define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 | |
380 | #endif | |
381 | ||
382 | #ifndef PCI_VENDOR_ID_CIRRUS | |
383 | #define PCI_VENDOR_ID_CIRRUS 0x1013 | |
384 | #endif | |
385 | #ifndef PCI_DEVICE_ID_CIRRUS_6729 | |
386 | #define PCI_DEVICE_ID_CIRRUS_6729 0x1100 | |
387 | #endif | |
388 | #ifndef PCI_DEVICE_ID_CIRRUS_6832 | |
389 | #define PCI_DEVICE_ID_CIRRUS_6832 0x1110 | |
390 | #endif | |
391 | ||
392 | #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ | |
393 | #define PD67_FIFO_CTL 0x17 /* FIFO control */ | |
394 | #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ | |
395 | #define PD67_CHIP_INFO 0x1f /* Chip information */ | |
396 | #define PD67_ATA_CTL 0x026 /* 6730: ATA control */ | |
397 | #define PD67_EXT_INDEX 0x2e /* Extension index */ | |
398 | #define PD67_EXT_DATA 0x2f /* Extension data */ | |
399 | ||
400 | #define pd67_ext_get(s, r) \ | |
401 | (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) | |
402 | #define pd67_ext_set(s, r, v) \ | |
403 | (i365_set(s, PD67_EXT_INDEX, r), i365_set(s, PD67_EXT_DATA, v)) | |
404 | ||
405 | /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ | |
406 | #define PD67_DATA_MASK0 0x01 /* Data mask 0 */ | |
407 | #define PD67_DATA_MASK1 0x02 /* Data mask 1 */ | |
408 | #define PD67_DMA_CTL 0x03 /* DMA control */ | |
409 | ||
410 | /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ | |
411 | #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ | |
412 | #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ | |
413 | #define PD67_EXTERN_DATA 0x0a | |
414 | #define PD67_EXT_CTL_2 0x0b | |
415 | #define PD67_MISC_CTL_3 0x25 | |
416 | #define PD67_SMB_PWR_CTL 0x26 | |
417 | ||
418 | /* I/O window address offset */ | |
419 | #define PD67_IO_OFF(w) (0x36+((w)<<1)) | |
420 | ||
421 | /* Timing register sets */ | |
422 | #define PD67_TIME_SETUP(n) (0x3a + 3*(n)) | |
423 | #define PD67_TIME_CMD(n) (0x3b + 3*(n)) | |
424 | #define PD67_TIME_RECOV(n) (0x3c + 3*(n)) | |
425 | ||
426 | /* Flags for PD67_MISC_CTL_1 */ | |
427 | #define PD67_MC1_5V_DET 0x01 /* 5v detect */ | |
428 | #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ | |
429 | #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ | |
430 | #define PD67_MC1_PULSE_MGMT 0x04 | |
431 | #define PD67_MC1_PULSE_IRQ 0x08 | |
432 | #define PD67_MC1_SPKR_ENA 0x10 | |
433 | #define PD67_MC1_INPACK_ENA 0x80 | |
434 | ||
435 | /* Flags for PD67_FIFO_CTL */ | |
436 | #define PD67_FIFO_EMPTY 0x80 | |
437 | ||
438 | /* Flags for PD67_MISC_CTL_2 */ | |
439 | #define PD67_MC2_FREQ_BYPASS 0x01 | |
440 | #define PD67_MC2_DYNAMIC_MODE 0x02 | |
441 | #define PD67_MC2_SUSPEND 0x04 | |
442 | #define PD67_MC2_5V_CORE 0x08 | |
443 | #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ | |
444 | #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ | |
445 | #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ | |
446 | #define PD67_MC2_DMA_MODE 0x40 | |
447 | #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ | |
448 | ||
449 | /* Flags for PD67_CHIP_INFO */ | |
450 | #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ | |
451 | #define PD67_INFO_CHIP_ID 0xc0 | |
452 | #define PD67_INFO_REV 0x1c | |
453 | ||
454 | /* Fields in PD67_TIME_* registers */ | |
455 | #define PD67_TIME_SCALE 0xc0 | |
456 | #define PD67_TIME_SCALE_1 0x00 | |
457 | #define PD67_TIME_SCALE_16 0x40 | |
458 | #define PD67_TIME_SCALE_256 0x80 | |
459 | #define PD67_TIME_SCALE_4096 0xc0 | |
460 | #define PD67_TIME_MULT 0x3f | |
461 | ||
462 | /* Fields in PD67_DMA_CTL */ | |
463 | #define PD67_DMA_MODE 0xc0 | |
464 | #define PD67_DMA_OFF 0x00 | |
465 | #define PD67_DMA_DREQ_INPACK 0x40 | |
466 | #define PD67_DMA_DREQ_WP 0x80 | |
467 | #define PD67_DMA_DREQ_BVD2 0xc0 | |
468 | #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ | |
469 | ||
470 | /* Fields in PD67_EXT_CTL_1 */ | |
471 | #define PD67_EC1_VCC_PWR_LOCK 0x01 | |
472 | #define PD67_EC1_AUTO_PWR_CLEAR 0x02 | |
473 | #define PD67_EC1_LED_ENA 0x04 | |
474 | #define PD67_EC1_INV_CARD_IRQ 0x08 | |
475 | #define PD67_EC1_INV_MGMT_IRQ 0x10 | |
476 | #define PD67_EC1_PULLUP_CTL 0x20 | |
477 | ||
478 | /* Fields in PD67_EXTERN_DATA */ | |
479 | #define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) | |
480 | #define PD67_EXD_VS2(s) (0x02 << ((s)<<1)) | |
481 | ||
482 | /* Fields in PD67_EXT_CTL_2 */ | |
483 | #define PD67_EC2_GPSTB_TOTEM 0x04 | |
484 | #define PD67_EC2_GPSTB_IOR 0x08 | |
485 | #define PD67_EC2_GPSTB_IOW 0x10 | |
486 | #define PD67_EC2_GPSTB_HIGH 0x20 | |
487 | ||
488 | /* Fields in PD67_MISC_CTL_3 */ | |
489 | #define PD67_MC3_IRQ_MASK 0x03 | |
490 | #define PD67_MC3_IRQ_PCPCI 0x00 | |
491 | #define PD67_MC3_IRQ_EXTERN 0x01 | |
492 | #define PD67_MC3_IRQ_PCIWAY 0x02 | |
493 | #define PD67_MC3_IRQ_PCI 0x03 | |
494 | #define PD67_MC3_PWR_MASK 0x0c | |
495 | #define PD67_MC3_PWR_SERIAL 0x00 | |
496 | #define PD67_MC3_PWR_TI2202 0x08 | |
497 | #define PD67_MC3_PWR_SMB 0x0c | |
498 | ||
499 | /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ | |
500 | ||
501 | /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ | |
502 | #define PD68_PCI_SPACE 0x22 | |
503 | #define PD68_PCCARD_SPACE 0x23 | |
504 | #define PD68_WINDOW_TYPE 0x24 | |
505 | #define PD68_EXT_CSC 0x2e | |
506 | #define PD68_MISC_CTL_4 0x2f | |
507 | #define PD68_MISC_CTL_5 0x30 | |
508 | #define PD68_MISC_CTL_6 0x31 | |
509 | ||
510 | /* Extra flags in PD67_MISC_CTL_3 */ | |
511 | #define PD68_MC3_HW_SUSP 0x10 | |
512 | #define PD68_MC3_MM_EXPAND 0x40 | |
513 | #define PD68_MC3_MM_ARM 0x80 | |
514 | ||
515 | /* Bridge Control Register */ | |
516 | #define PD6832_BCR_MGMT_IRQ_ENA 0x0800 | |
517 | ||
518 | /* Socket Number Register */ | |
519 | #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ | |
520 | ||
521 | /* Data structure for tracking vendor-specific state */ | |
522 | typedef struct cirrus_state_t { | |
523 | u_char misc1; /* PD67_MISC_CTL_1 */ | |
524 | u_char misc2; /* PD67_MISC_CTL_2 */ | |
525 | u_char ectl1; /* PD67_EXT_CTL_1 */ | |
526 | u_char timer[6]; /* PD67_TIME_* */ | |
527 | } cirrus_state_t; | |
528 | ||
529 | #define CIRRUS_PCIC_ID \ | |
530 | IS_PD6729, IS_PD6730, IS_PD6832 | |
531 | ||
532 | #define CIRRUS_PCIC_INFO \ | |
533 | { "Cirrus PD6729", IS_CIRRUS|IS_PCI, ID(CIRRUS, 6729) }, \ | |
534 | { "Cirrus PD6730", IS_CIRRUS|IS_PCI, PCI_VENDOR_ID_CIRRUS, -1 }, \ | |
535 | { "Cirrus PD6832", IS_CIRRUS|IS_CARDBUS, ID(CIRRUS, 6832) } | |
536 | ||
537 | /* Special bit in I365_IDENT used for Vadem chip detection */ | |
538 | #define I365_IDENT_VADEM 0x08 | |
539 | ||
540 | /* Special definitions in I365_POWER */ | |
541 | #define VG468_VPP2_MASK 0x0c | |
542 | #define VG468_VPP2_5V 0x04 | |
543 | #define VG468_VPP2_12V 0x08 | |
544 | ||
545 | /* Unique Vadem registers */ | |
546 | #define VG469_VSENSE 0x1f /* Card voltage sense */ | |
547 | #define VG469_VSELECT 0x2f /* Card voltage select */ | |
548 | #define VG468_CTL 0x38 /* Control register */ | |
549 | #define VG468_TIMER 0x39 /* Timer control */ | |
550 | #define VG468_MISC 0x3a /* Miscellaneous */ | |
551 | #define VG468_GPIO_CFG 0x3b /* GPIO configuration */ | |
552 | #define VG469_EXT_MODE 0x3c /* Extended mode register */ | |
553 | #define VG468_SELECT 0x3d /* Programmable chip select */ | |
554 | #define VG468_SELECT_CFG 0x3e /* Chip select configuration */ | |
555 | #define VG468_ATA 0x3f /* ATA control */ | |
556 | ||
557 | /* Flags for VG469_VSENSE */ | |
558 | #define VG469_VSENSE_A_VS1 0x01 | |
559 | #define VG469_VSENSE_A_VS2 0x02 | |
560 | #define VG469_VSENSE_B_VS1 0x04 | |
561 | #define VG469_VSENSE_B_VS2 0x08 | |
562 | ||
563 | /* Flags for VG469_VSELECT */ | |
564 | #define VG469_VSEL_VCC 0x03 | |
565 | #define VG469_VSEL_5V 0x00 | |
566 | #define VG469_VSEL_3V 0x03 | |
567 | #define VG469_VSEL_MAX 0x0c | |
568 | #define VG469_VSEL_EXT_STAT 0x10 | |
569 | #define VG469_VSEL_EXT_BUS 0x20 | |
570 | #define VG469_VSEL_MIXED 0x40 | |
571 | #define VG469_VSEL_ISA 0x80 | |
572 | ||
573 | /* Flags for VG468_CTL */ | |
574 | #define VG468_CTL_SLOW 0x01 /* 600ns memory timing */ | |
575 | #define VG468_CTL_ASYNC 0x02 /* Asynchronous bus clocking */ | |
576 | #define VG468_CTL_TSSI 0x08 /* Tri-state some outputs */ | |
577 | #define VG468_CTL_DELAY 0x10 /* Card detect debounce */ | |
578 | #define VG468_CTL_INPACK 0x20 /* Obey INPACK signal? */ | |
579 | #define VG468_CTL_POLARITY 0x40 /* VCCEN polarity */ | |
580 | #define VG468_CTL_COMPAT 0x80 /* Compatibility stuff */ | |
581 | ||
582 | #define VG469_CTL_WS_COMPAT 0x04 /* Wait state compatibility */ | |
583 | #define VG469_CTL_STRETCH 0x10 /* LED stretch */ | |
584 | ||
585 | /* Flags for VG468_TIMER */ | |
586 | #define VG468_TIMER_ZEROPWR 0x10 /* Zero power control */ | |
587 | #define VG468_TIMER_SIGEN 0x20 /* Power up */ | |
588 | #define VG468_TIMER_STATUS 0x40 /* Activity timer status */ | |
589 | #define VG468_TIMER_RES 0x80 /* Timer resolution */ | |
590 | #define VG468_TIMER_MASK 0x0f /* Activity timer timeout */ | |
591 | ||
592 | /* Flags for VG468_MISC */ | |
593 | #define VG468_MISC_GPIO 0x04 /* General-purpose IO */ | |
594 | #define VG468_MISC_DMAWSB 0x08 /* DMA wait state control */ | |
595 | #define VG469_MISC_LEDENA 0x10 /* LED enable */ | |
596 | #define VG468_MISC_VADEMREV 0x40 /* Vadem revision control */ | |
597 | #define VG468_MISC_UNLOCK 0x80 /* Unique register lock */ | |
598 | ||
599 | /* Flags for VG469_EXT_MODE_A */ | |
600 | #define VG469_MODE_VPPST 0x03 /* Vpp steering control */ | |
601 | #define VG469_MODE_INT_SENSE 0x04 /* Internal voltage sense */ | |
602 | #define VG469_MODE_CABLE 0x08 | |
603 | #define VG469_MODE_COMPAT 0x10 /* i82365sl B or DF step */ | |
604 | #define VG469_MODE_TEST 0x20 | |
605 | #define VG469_MODE_RIO 0x40 /* Steer RIO to INTR? */ | |
606 | ||
607 | /* Flags for VG469_EXT_MODE_B */ | |
608 | #define VG469_MODE_B_3V 0x01 /* 3.3v for socket B */ | |
609 | ||
610 | /* Data structure for tracking vendor-specific state */ | |
611 | typedef struct vg46x_state_t { | |
612 | u_char ctl; /* VG468_CTL */ | |
613 | u_char ema; /* VG468_EXT_MODE_A */ | |
614 | } vg46x_state_t; |