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Commit | Line | Data |
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30bf8c66 AF |
1 | From 77e3b7f055f824e4d6587faa73bd4aacd0c307e8 Mon Sep 17 00:00:00 2001 |
2 | From: hayeswang <hayeswang@realtek.com> | |
3 | Date: Wed, 9 Jul 2014 14:52:51 +0800 | |
4 | Subject: [PATCH] r8169: disable L23 | |
5 | ||
6 | For RTL8411, RTL8111G, RTL8402, RTL8105, and RTL8106, disable the feature | |
7 | of entering the L2/L3 link state of the PCIe. When the nic starts the process | |
8 | of entering the L2/L3 link state and the PCI reset occurs before the work | |
9 | is finished, the work would be queued and continue after the next the PCI | |
10 | reset occurs. This causes the device stays in L2/L3 link state, and the system | |
11 | couldn't find the device. | |
12 | ||
13 | Signed-off-by: Hayes Wang <hayeswang@realtek.com> | |
14 | Acked-by: Francois Romieu <romieu@fr.zoreil.com> | |
15 | Signed-off-by: David S. Miller <davem@davemloft.net> | |
16 | --- | |
17 | drivers/net/ethernet/realtek/r8169.c | 25 +++++++++++++++++++++++++ | |
18 | 1 file changed, 25 insertions(+) | |
19 | ||
20 | diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c | |
21 | index 3ff7bc3..b94f658 100644 | |
22 | --- a/drivers/net/ethernet/realtek/r8169.c | |
23 | +++ b/drivers/net/ethernet/realtek/r8169.c | |
24 | @@ -538,6 +538,7 @@ enum rtl_register_content { | |
25 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
26 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
27 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ | |
28 | + Rdy_to_L23 = (1 << 1), /* L23 Enable */ | |
29 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ | |
30 | ||
31 | /* Config4 register */ | |
32 | @@ -4897,6 +4898,21 @@ static void rtl_enable_clock_request(struct pci_dev *pdev) | |
33 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
34 | } | |
35 | ||
36 | +static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable) | |
37 | +{ | |
38 | + void __iomem *ioaddr = tp->mmio_addr; | |
39 | + u8 data; | |
40 | + | |
41 | + data = RTL_R8(Config3); | |
42 | + | |
43 | + if (enable) | |
44 | + data |= Rdy_to_L23; | |
45 | + else | |
46 | + data &= ~Rdy_to_L23; | |
47 | + | |
48 | + RTL_W8(Config3, data); | |
49 | +} | |
50 | + | |
51 | #define R8168_CPCMD_QUIRK_MASK (\ | |
52 | EnableBist | \ | |
53 | Mac_dbgo_oe | \ | |
54 | @@ -5246,6 +5262,7 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp) | |
55 | }; | |
56 | ||
57 | rtl_hw_start_8168f(tp); | |
58 | + rtl_pcie_state_l2l3_enable(tp, false); | |
59 | ||
60 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); | |
61 | ||
62 | @@ -5284,6 +5301,8 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) | |
63 | ||
64 | rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); | |
65 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
66 | + | |
67 | + rtl_pcie_state_l2l3_enable(tp, false); | |
68 | } | |
69 | ||
70 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) | |
71 | @@ -5536,6 +5555,8 @@ static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) | |
72 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
73 | ||
74 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); | |
75 | + | |
76 | + rtl_pcie_state_l2l3_enable(tp, false); | |
77 | } | |
78 | ||
79 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) | |
80 | @@ -5571,6 +5592,8 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp) | |
81 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
82 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
83 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); | |
84 | + | |
85 | + rtl_pcie_state_l2l3_enable(tp, false); | |
86 | } | |
87 | ||
88 | static void rtl_hw_start_8106(struct rtl8169_private *tp) | |
89 | @@ -5583,6 +5606,8 @@ static void rtl_hw_start_8106(struct rtl8169_private *tp) | |
90 | RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); | |
91 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
92 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
93 | + | |
94 | + rtl_pcie_state_l2l3_enable(tp, false); | |
95 | } | |
96 | ||
97 | static void rtl_hw_start_8101(struct net_device *dev) | |
98 | -- | |
99 | 1.8.5.2 | |
100 |