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00e5a55c BS |
1 | Commit-Id: f231e0a5a2d01da40515c24f1daa689fe8cfd8d7 |
2 | From: Divy Le Ray <divy@chelsio.com> | |
3 | Date: Wed, 8 Oct 2008 17:39:00 -0700 | |
4 | Acked-by: Karsten Keil <kkeil@novell.com> | |
5 | Subject: [PATCH] cxgb3: More flexible support for PHY interrupts. | |
6 | Reference: bnc#446739 | |
7 | ||
8 | Do not require PHY interrupts to be connected to GPIs in ascending order. | |
9 | Base interrupt availability both on PHYs supporting them and on GPIs being | |
10 | hooked up. Allows boards to specify interrupt GPIs though the PHYs don't | |
11 | use them. | |
12 | ||
13 | Remove spurious PHY interrupts due to clearing T3DBG interrupts before | |
14 | setting their polarity. | |
15 | ||
16 | Signed-off-by: Divy Le Ray <divy@chelsio.com> | |
17 | Signed-off-by: David S. Miller <davem@davemloft.net> | |
18 | ||
19 | diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h | |
20 | index e83a360..75b5ee6 100644 | |
21 | --- a/drivers/net/cxgb3/common.h | |
22 | +++ b/drivers/net/cxgb3/common.h | |
23 | @@ -194,7 +194,7 @@ struct adapter_info { | |
24 | unsigned char nports; /* # of ports */ | |
25 | unsigned char phy_base_addr; /* MDIO PHY base address */ | |
26 | unsigned int gpio_out; /* GPIO output settings */ | |
27 | - unsigned int gpio_intr; /* GPIO IRQ enable mask */ | |
28 | + unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ | |
29 | unsigned long caps; /* adapter capabilities */ | |
30 | const struct mdio_ops *mdio_ops; /* MDIO operations */ | |
31 | const char *desc; /* product description */ | |
32 | @@ -517,7 +517,7 @@ enum { | |
33 | MAC_RXFIFO_SIZE = 32768 | |
34 | }; | |
35 | ||
36 | -/* IEEE 802.3ae specified MDIO devices */ | |
37 | +/* IEEE 802.3 specified MDIO devices */ | |
38 | enum { | |
39 | MDIO_DEV_PMA_PMD = 1, | |
40 | MDIO_DEV_WIS = 2, | |
41 | diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h | |
42 | index 4bda27c..a035d5c 100644 | |
43 | --- a/drivers/net/cxgb3/regs.h | |
44 | +++ b/drivers/net/cxgb3/regs.h | |
45 | @@ -573,6 +573,10 @@ | |
46 | #define V_GPIO10(x) ((x) << S_GPIO10) | |
47 | #define F_GPIO10 V_GPIO10(1U) | |
48 | ||
49 | +#define S_GPIO9 9 | |
50 | +#define V_GPIO9(x) ((x) << S_GPIO9) | |
51 | +#define F_GPIO9 V_GPIO9(1U) | |
52 | + | |
53 | #define S_GPIO7 7 | |
54 | #define V_GPIO7(x) ((x) << S_GPIO7) | |
55 | #define F_GPIO7 V_GPIO7(1U) | |
56 | diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c | |
57 | index f7ced32..bfce761 100644 | |
58 | --- a/drivers/net/cxgb3/t3_hw.c | |
59 | +++ b/drivers/net/cxgb3/t3_hw.c | |
60 | @@ -445,24 +445,22 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex) | |
61 | static const struct adapter_info t3_adap_info[] = { | |
62 | {2, 0, | |
63 | F_GPIO2_OEN | F_GPIO4_OEN | | |
64 | - F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, | |
65 | - 0, | |
66 | + F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, | |
67 | &mi1_mdio_ops, "Chelsio PE9000"}, | |
68 | {2, 0, | |
69 | F_GPIO2_OEN | F_GPIO4_OEN | | |
70 | - F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, | |
71 | - 0, | |
72 | + F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, | |
73 | &mi1_mdio_ops, "Chelsio T302"}, | |
74 | {1, 0, | |
75 | F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | | |
76 | F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, | |
77 | - 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, | |
78 | + { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, | |
79 | &mi1_mdio_ext_ops, "Chelsio T310"}, | |
80 | {2, 0, | |
81 | F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | | |
82 | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | | |
83 | - F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0, | |
84 | - SUPPORTED_10000baseT_Full | SUPPORTED_AUI, | |
85 | + F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, | |
86 | + { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, | |
87 | &mi1_mdio_ext_ops, "Chelsio T320"}, | |
88 | }; | |
89 | ||
90 | @@ -1684,19 +1682,15 @@ static int mac_intr_handler(struct adapter *adap, unsigned int idx) | |
91 | */ | |
92 | int t3_phy_intr_handler(struct adapter *adapter) | |
93 | { | |
94 | - u32 mask, gpi = adapter_info(adapter)->gpio_intr; | |
95 | u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); | |
96 | ||
97 | for_each_port(adapter, i) { | |
98 | struct port_info *p = adap2pinfo(adapter, i); | |
99 | ||
100 | - mask = gpi - (gpi & (gpi - 1)); | |
101 | - gpi -= mask; | |
102 | - | |
103 | if (!(p->phy.caps & SUPPORTED_IRQ)) | |
104 | continue; | |
105 | ||
106 | - if (cause & mask) { | |
107 | + if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { | |
108 | int phy_cause = p->phy.ops->intr_handler(&p->phy); | |
109 | ||
110 | if (phy_cause & cphy_cause_link_change) | |
111 | @@ -1765,6 +1759,17 @@ int t3_slow_intr_handler(struct adapter *adapter) | |
112 | return 1; | |
113 | } | |
114 | ||
115 | +static unsigned int calc_gpio_intr(struct adapter *adap) | |
116 | +{ | |
117 | + unsigned int i, gpi_intr = 0; | |
118 | + | |
119 | + for_each_port(adap, i) | |
120 | + if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) && | |
121 | + adapter_info(adap)->gpio_intr[i]) | |
122 | + gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i]; | |
123 | + return gpi_intr; | |
124 | +} | |
125 | + | |
126 | /** | |
127 | * t3_intr_enable - enable interrupts | |
128 | * @adapter: the adapter whose interrupts should be enabled | |
129 | @@ -1807,10 +1812,8 @@ void t3_intr_enable(struct adapter *adapter) | |
130 | t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); | |
131 | } | |
132 | ||
133 | - t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, | |
134 | - adapter_info(adapter)->gpio_intr); | |
135 | - t3_write_reg(adapter, A_T3DBG_INT_ENABLE, | |
136 | - adapter_info(adapter)->gpio_intr); | |
137 | + t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); | |
138 | + | |
139 | if (is_pcie(adapter)) | |
140 | t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); | |
141 | else | |
142 | @@ -3331,6 +3334,8 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) | |
143 | init_hw_for_avail_ports(adapter, adapter->params.nports); | |
144 | t3_sge_init(adapter, &adapter->params.sge); | |
145 | ||
146 | + t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); | |
147 | + | |
148 | t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); | |
149 | t3_write_reg(adapter, A_CIM_BOOT_CFG, | |
150 | V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); |