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Commit | Line | Data |
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2cb7cef9 BS |
1 | From: Suresh Siddha <suresh.b.siddha@intel.com> |
2 | Subject: x64, x2apic/intr-remap: move IOMMU_WAIT_OP() macro to intel-iommu.h | |
3 | References: fate #303948 and fate #303984 | |
4 | Patch-Mainline: queued for .28 | |
5 | Commit-ID: cf1337f0447e5be8e66daa944f0ea3bcac2b6179 | |
6 | ||
7 | Signed-off-by: Thomas Renninger <trenn@suse.de> | |
8 | ||
9 | move IOMMU_WAIT_OP() macro to header file. | |
10 | ||
11 | This will be used by both DMA-remapping and Intr-remapping. | |
12 | ||
13 | Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> | |
14 | Cc: akpm@linux-foundation.org | |
15 | Cc: arjan@linux.intel.com | |
16 | Cc: andi@firstfloor.org | |
17 | Cc: ebiederm@xmission.com | |
18 | Cc: jbarnes@virtuousgeek.org | |
19 | Cc: steiner@sgi.com | |
20 | Signed-off-by: Ingo Molnar <mingo@elte.hu> | |
21 | ||
22 | --- | |
23 | drivers/pci/intel-iommu.c | 15 --------------- | |
24 | drivers/pci/intel-iommu.h | 15 +++++++++++++++ | |
25 | 2 files changed, 15 insertions(+), 15 deletions(-) | |
26 | ||
27 | --- a/drivers/pci/intel-iommu.c | |
28 | +++ b/drivers/pci/intel-iommu.c | |
29 | @@ -49,8 +49,6 @@ | |
30 | ||
31 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
32 | ||
33 | -#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */ | |
34 | - | |
35 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) | |
36 | ||
37 | ||
38 | @@ -488,19 +486,6 @@ static int iommu_alloc_root_entry(struct | |
39 | return 0; | |
40 | } | |
41 | ||
42 | -#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | |
43 | -{\ | |
44 | - cycles_t start_time = get_cycles();\ | |
45 | - while (1) {\ | |
46 | - sts = op (iommu->reg + offset);\ | |
47 | - if (cond)\ | |
48 | - break;\ | |
49 | - if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ | |
50 | - panic("DMAR hardware is malfunctioning\n");\ | |
51 | - cpu_relax();\ | |
52 | - }\ | |
53 | -} | |
54 | - | |
55 | static void iommu_set_root_entry(struct intel_iommu *iommu) | |
56 | { | |
57 | void *addr; | |
58 | --- a/drivers/pci/intel-iommu.h | |
59 | +++ b/drivers/pci/intel-iommu.h | |
60 | @@ -177,6 +177,21 @@ static inline void dmar_writeq(void __io | |
61 | #define dma_frcd_source_id(c) (c & 0xffff) | |
62 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ | |
63 | ||
64 | +#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */ | |
65 | + | |
66 | +#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | |
67 | +{\ | |
68 | + cycles_t start_time = get_cycles();\ | |
69 | + while (1) {\ | |
70 | + sts = op (iommu->reg + offset);\ | |
71 | + if (cond)\ | |
72 | + break;\ | |
73 | + if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ | |
74 | + panic("DMAR hardware is malfunctioning\n");\ | |
75 | + cpu_relax();\ | |
76 | + }\ | |
77 | +} | |
78 | + | |
79 | struct intel_iommu { | |
80 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
81 | u64 cap; |