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Commit | Line | Data |
---|---|---|
2cb7cef9 BS |
1 | From: Suresh Siddha <suresh.b.siddha@intel.com> |
2 | Subject: x64, x2apic/intr-remap: cpuid bits for x2apic feature | |
3 | References: fate #303948 and fate #303984 | |
4 | Patch-Mainline: queued for .28 | |
5 | Commit-ID: 32e1d0a0651004f5fe47f85a2a5c725ad579a90c | |
6 | ||
7 | Signed-off-by: Thomas Renninger <trenn@suse.de> | |
8 | ||
9 | cpuid feature for x2apic. | |
10 | ||
11 | Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> | |
12 | Cc: akpm@linux-foundation.org | |
13 | Cc: arjan@linux.intel.com | |
14 | Cc: andi@firstfloor.org | |
15 | Cc: ebiederm@xmission.com | |
16 | Cc: jbarnes@virtuousgeek.org | |
17 | Cc: steiner@sgi.com | |
18 | Signed-off-by: Ingo Molnar <mingo@elte.hu> | |
19 | ||
20 | --- | |
21 | arch/x86/kernel/cpu/feature_names.c | 2 +- | |
22 | include/asm-x86/cpufeature.h | 2 ++ | |
23 | 2 files changed, 3 insertions(+), 1 deletion(-) | |
24 | ||
25 | --- a/arch/x86/kernel/cpu/feature_names.c | |
26 | +++ b/arch/x86/kernel/cpu/feature_names.c | |
27 | @@ -46,7 +46,7 @@ const char * const x86_cap_flags[NCAPINT | |
28 | /* Intel-defined (#2) */ | |
29 | "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est", | |
30 | "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL, | |
31 | - NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt", | |
32 | + NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt", | |
33 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
34 | ||
35 | /* VIA/Cyrix/Centaur-defined */ | |
36 | --- a/include/asm-x86/cpufeature.h | |
37 | +++ b/include/asm-x86/cpufeature.h | |
38 | @@ -94,6 +94,7 @@ | |
39 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ | |
40 | #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ | |
41 | #define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */ | |
42 | +#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ | |
43 | ||
44 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
45 | #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ | |
46 | @@ -193,6 +194,7 @@ extern const char * const x86_power_flag | |
47 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) | |
48 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) | |
49 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) | |
50 | +#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) | |
51 | ||
52 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) | |
53 | # define cpu_has_invlpg 1 |