]> git.ipfire.org Git - thirdparty/glibc.git/blame - sysdeps/aarch64/fpu/bits/math-vector.h
aarch64: Add vector implementations of tan routines
[thirdparty/glibc.git] / sysdeps / aarch64 / fpu / bits / math-vector.h
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1/* Platform-specific SIMD declarations of math functions.
2
3 Copyright (C) 2023 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
10
11 The GNU C Library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
15
16 You should have received a copy of the GNU Lesser General Public
17 License along with the GNU C Library; if not, see
18 <https://www.gnu.org/licenses/>. */
19
20#ifndef _MATH_H
21# error "Never include <bits/math-vector.h> directly;\
22 include <math.h> instead."
23#endif
24
25/* Get default empty definitions for simd declarations. */
26#include <bits/libm-simd-decl-stubs.h>
27
28#if __GNUC_PREREQ(9, 0)
29# define __ADVSIMD_VEC_MATH_SUPPORTED
30typedef __Float32x4_t __f32x4_t;
31typedef __Float64x2_t __f64x2_t;
32#elif __glibc_clang_prereq(8, 0)
33# define __ADVSIMD_VEC_MATH_SUPPORTED
34typedef __attribute__ ((__neon_vector_type__ (4))) float __f32x4_t;
35typedef __attribute__ ((__neon_vector_type__ (2))) double __f64x2_t;
36#endif
37
38#if __GNUC_PREREQ(10, 0) || __glibc_clang_prereq(11, 0)
39# define __SVE_VEC_MATH_SUPPORTED
40typedef __SVFloat32_t __sv_f32_t;
41typedef __SVFloat64_t __sv_f64_t;
42typedef __SVBool_t __sv_bool_t;
43#endif
44
45/* If vector types and vector PCS are unsupported in the working
46 compiler, no choice but to omit vector math declarations. */
47
48#ifdef __ADVSIMD_VEC_MATH_SUPPORTED
49
50# define __vpcs __attribute__ ((__aarch64_vector_pcs__))
51
52__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
4a9392ff 53__vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t);
78c01a5c 54__vpcs __f32x4_t _ZGVnN4v_logf (__f32x4_t);
3bb1af20 55__vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t);
f554334c 56__vpcs __f32x4_t _ZGVnN4v_tanf (__f32x4_t);
3bb1af20 57
cd94326a 58__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
4a9392ff 59__vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t);
78c01a5c 60__vpcs __f64x2_t _ZGVnN2v_log (__f64x2_t);
3bb1af20 61__vpcs __f64x2_t _ZGVnN2v_sin (__f64x2_t);
f554334c 62__vpcs __f64x2_t _ZGVnN2v_tan (__f64x2_t);
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63
64# undef __ADVSIMD_VEC_MATH_SUPPORTED
65#endif /* __ADVSIMD_VEC_MATH_SUPPORTED */
66
67#ifdef __SVE_VEC_MATH_SUPPORTED
68
69__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
4a9392ff 70__sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t);
78c01a5c 71__sv_f32_t _ZGVsMxv_logf (__sv_f32_t, __sv_bool_t);
3bb1af20 72__sv_f32_t _ZGVsMxv_sinf (__sv_f32_t, __sv_bool_t);
f554334c 73__sv_f32_t _ZGVsMxv_tanf (__sv_f32_t, __sv_bool_t);
3bb1af20 74
cd94326a 75__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
4a9392ff 76__sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t);
78c01a5c 77__sv_f64_t _ZGVsMxv_log (__sv_f64_t, __sv_bool_t);
3bb1af20 78__sv_f64_t _ZGVsMxv_sin (__sv_f64_t, __sv_bool_t);
f554334c 79__sv_f64_t _ZGVsMxv_tan (__sv_f64_t, __sv_bool_t);
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80
81# undef __SVE_VEC_MATH_SUPPORTED
82#endif /* __SVE_VEC_MATH_SUPPORTED */