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04277e02 | 1 | /* Copyright (C) 1996-2019 Free Software Foundation, Inc. |
554066b8 MS |
2 | |
3 | This file is part of the GNU C Library. | |
4 | ||
5 | The GNU C Library is free software; you can redistribute it and/or | |
6 | modify it under the terms of the GNU Lesser General Public License as | |
7 | published by the Free Software Foundation; either version 2.1 of the | |
8 | License, or (at your option) any later version. | |
9 | ||
10 | The GNU C Library is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | Lesser General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU Lesser General Public | |
16 | License along with the GNU C Library; if not, see | |
17 | <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #ifndef _AARCH64_FPU_CONTROL_H | |
20 | #define _AARCH64_FPU_CONTROL_H | |
21 | ||
0c8a67a5 | 22 | #include <features.h> |
4f5b921e | 23 | |
554066b8 MS |
24 | /* Macros for accessing the FPCR and FPSR. */ |
25 | ||
3f8d9d58 WD |
26 | #if __GNUC_PREREQ (6,0) |
27 | # define _FPU_GETCW(fpcr) (fpcr = __builtin_aarch64_get_fpcr ()) | |
28 | # define _FPU_SETCW(fpcr) __builtin_aarch64_set_fpcr (fpcr) | |
29 | # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) | |
30 | # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) | |
31 | #else | |
32 | # define _FPU_GETCW(fpcr) \ | |
554066b8 MS |
33 | __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) |
34 | ||
3f8d9d58 | 35 | # define _FPU_SETCW(fpcr) \ |
a88dadbe | 36 | __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) |
554066b8 | 37 | |
3f8d9d58 | 38 | # define _FPU_GETFPSR(fpsr) \ |
554066b8 MS |
39 | __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) |
40 | ||
3f8d9d58 | 41 | # define _FPU_SETFPSR(fpsr) \ |
554066b8 | 42 | __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) |
3f8d9d58 | 43 | #endif |
554066b8 MS |
44 | |
45 | /* Reserved bits should be preserved when modifying register | |
46 | contents. These two masks indicate which bits in each of FPCR and | |
47 | FPSR should not be changed. */ | |
48 | ||
49 | #define _FPU_RESERVED 0xfe0fe0ff | |
50 | #define _FPU_FPSR_RESERVED 0x0fffffe0 | |
51 | ||
52 | #define _FPU_DEFAULT 0x00000000 | |
53 | #define _FPU_FPSR_DEFAULT 0x00000000 | |
54 | ||
55 | /* Layout of FPCR and FPSR: | |
56 | ||
57 | | | | | | | | | | |
58 | 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 | |
59 | s s s s s s s s s s s | |
60 | c c c c c c c c c c c c | |
61 | N Z C V Q A D F R R S S S L L L I U U I U O D I I U U I U O D I | |
62 | C H N Z M M T T B E E E D N N X F F Z O D N N X F F Z O | |
63 | P O O R R Z N N N E K K E E E E E C K K C C C C C | |
64 | D D I I P | |
65 | E E D D | |
66 | E E | |
67 | */ | |
196f456b MS |
68 | |
69 | #define _FPU_FPCR_RM_MASK 0xc00000 | |
70 | ||
554066b8 MS |
71 | #define _FPU_FPCR_MASK_IXE 0x1000 |
72 | #define _FPU_FPCR_MASK_UFE 0x0800 | |
73 | #define _FPU_FPCR_MASK_OFE 0x0400 | |
74 | #define _FPU_FPCR_MASK_DZE 0x0200 | |
75 | #define _FPU_FPCR_MASK_IOE 0x0100 | |
76 | ||
77 | #define _FPU_FPCR_IEEE \ | |
78 | (_FPU_DEFAULT | _FPU_FPCR_MASK_IXE | \ | |
79 | _FPU_FPCR_MASK_UFE | _FPU_FPCR_MASK_OFE | \ | |
80 | _FPU_FPCR_MASK_DZE | _FPU_FPCR_MASK_IOE) | |
81 | ||
82 | #define _FPU_FPSR_IEEE 0 | |
83 | ||
84 | typedef unsigned int fpu_control_t; | |
85 | typedef unsigned int fpu_fpsr_t; | |
86 | ||
87 | /* Default control word set at startup. */ | |
88 | extern fpu_control_t __fpu_control; | |
89 | ||
90 | #endif |