]> git.ipfire.org Git - thirdparty/glibc.git/blame - sysdeps/hppa/fpu/bits/fenv.h
x86: Add seperate non-temporal tunable for memset
[thirdparty/glibc.git] / sysdeps / hppa / fpu / bits / fenv.h
CommitLineData
dff8da6b 1/* Copyright (C) 2000-2024 Free Software Foundation, Inc.
fb0f0053 2 This file is part of the GNU C Library.
fb0f0053
UD
3
4 The GNU C Library is free software; you can redistribute it and/or
3214b89b
AJ
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
fb0f0053
UD
8
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3214b89b 12 Lesser General Public License for more details.
fb0f0053 13
3214b89b 14 You should have received a copy of the GNU Lesser General Public
ab84e3ff 15 License along with the GNU C Library. If not, see
5a82c748 16 <https://www.gnu.org/licenses/>. */
fb0f0053
UD
17
18#ifndef _FENV_H
19# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
20#endif
21
22/* Define bits representing the exception. We use the values of the
23 appropriate enable bits in the FPU status word (which,
24 coincidentally, are the same as the flag bits, but shifted right by
25 27 bits). */
26enum
27{
fbeafede
JM
28 FE_INVALID =
29#define FE_INVALID (1<<4) /* V */
30 FE_INVALID,
31 FE_DIVBYZERO =
32#define FE_DIVBYZERO (1<<3) /* Z */
33 FE_DIVBYZERO,
34 FE_OVERFLOW =
35#define FE_OVERFLOW (1<<2) /* O */
36 FE_OVERFLOW,
37 FE_UNDERFLOW =
38#define FE_UNDERFLOW (1<<1) /* U */
39 FE_UNDERFLOW,
40 FE_INEXACT =
41#define FE_INEXACT (1<<0) /* I */
42 FE_INEXACT,
fb0f0053
UD
43};
44
45#define FE_ALL_EXCEPT \
46 (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
47
48/* The PA-RISC FPU supports all of the four defined rounding modes.
49 We use the values of the RM field in the floating point status
50 register for the appropriate macros. */
51enum
52 {
fbeafede
JM
53 FE_TONEAREST =
54#define FE_TONEAREST (0 << 9)
55 FE_TONEAREST,
56 FE_TOWARDZERO =
57#define FE_TOWARDZERO (1 << 9)
58 FE_TOWARDZERO,
59 FE_UPWARD =
60#define FE_UPWARD (2 << 9)
61 FE_UPWARD,
62 FE_DOWNWARD =
63#define FE_DOWNWARD (3 << 9)
64 FE_DOWNWARD,
fb0f0053
UD
65 };
66
67/* Type representing exception flags. */
68typedef unsigned int fexcept_t;
69
70/* Type representing floating-point environment. This structure
71 corresponds to the layout of the status and exception words in the
48dcf1c5
CD
72 register file. The exception registers are never saved/stored by
73 userspace. This structure is also not correctly aligned ever, in
74 an ABI error we left out __aligned(8) and subsequently all of our
75 fenv functions must accept unaligned input, align the input, and
5556231d 76 then use assembly to store fr0. This is a performance hit, but
48dcf1c5 77 means the ABI is stable. */
fb0f0053
UD
78typedef struct
79{
80 unsigned int __status_word;
81 unsigned int __exception[7];
82} fenv_t;
83
84/* If the default argument is used we use this value. */
acfa885f 85#define FE_DFL_ENV ((const fenv_t *) -1)
fb0f0053
UD
86
87#ifdef __USE_GNU
88/* Floating-point environment where none of the exceptions are masked. */
acfa885f 89# define FE_NOMASK_ENV ((const fenv_t *) -2)
fb0f0053 90#endif
ec94343f 91
42cc619d 92#if __GLIBC_USE (IEC_60559_BFP_EXT_C23)
ec94343f
JM
93/* Type representing floating-point control modes. */
94typedef unsigned int femode_t;
95
96/* Default floating-point control modes. */
97# define FE_DFL_MODE ((const femode_t *) -1L)
98#endif