projects / thirdparty / glibc.git / blame
| Commit | Line | Data |
|---|---|---|
| c42d5e98 DM |
1 | /* Round float to int floating-point values without generating |
| 2 | an inexact exception, sparc32 v9 vis3 version. | |
| 3 | ||
| 581c785b | 4 | Copyright (C) 2013-2022 Free Software Foundation, Inc. |
| c42d5e98 | 5 | This file is part of the GNU C Library. |
| c42d5e98 DM |
6 | |
| 7 | The GNU C Library is free software; you can redistribute it and/or | |
| 8 | modify it under the terms of the GNU Lesser General Public | |
| 9 | License as published by the Free Software Foundation; either | |
| 10 | version 2.1 of the License, or (at your option) any later version. | |
| 11 | ||
| 12 | The GNU C Library is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | Lesser General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU Lesser General Public | |
| 18 | License along with the GNU C Library; if not, see | |
| 5a82c748 | 19 | <https://www.gnu.org/licenses/>. */ |
| c42d5e98 DM |
20 | |
| 21 | #include <sysdep.h> | |
| 22 | #include <math_ldbl_opt.h> | |
| 23 | ||
| 24 | /* We pop constants into the FPU registers using the incoming | |
| 25 | argument stack slots, since this avoid having to use any PIC | |
| 26 | references. We also thus avoid having to allocate a register | |
| 27 | window. | |
| 28 | ||
| 29 | VIS instructions are used to facilitate the formation of | |
| 30 | easier constants, and the propagation of the sign bit. */ | |
| 31 | ||
| 32 | #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ | |
| 33 | ||
| 34 | #define ZERO %f10 /* 0.0 */ | |
| 35 | #define SIGN_BIT %f12 /* -0.0 */ | |
| 36 | ||
| 37 | ENTRY (__nearbyint_vis3) | |
| 3ef3f1b9 DM |
38 | sllx %o0, 32, %o0 |
| 39 | or %o0, %o1, %o0 | |
| 40 | movxtod %o0, %f0 | |
| 2cbec365 | 41 | fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ |
| c42d5e98 DM |
42 | st %fsr, [%sp + 88] |
| 43 | sethi %hi(TWO_FIFTYTWO), %o2 | |
| 44 | sethi %hi(0xf8003e0), %o5 | |
| 45 | ld [%sp + 88], %o4 | |
| c42d5e98 | 46 | or %o5, %lo(0xf8003e0), %o5 |
| c42d5e98 DM |
47 | andn %o4, %o5, %o4 |
| 48 | fzero ZERO | |
| 49 | st %o4, [%sp + 80] | |
| 50 | sllx %o2, 32, %o2 | |
| 51 | fnegd ZERO, SIGN_BIT | |
| 52 | ld [%sp + 80], %fsr | |
| 53 | movxtod %o2, %f16 | |
| 54 | fabsd %f0, %f14 | |
| 55 | fcmpd %fcc3, %f14, %f16 | |
| 56 | fmovduge %fcc3, ZERO, %f16 | |
| 57 | fand %f0, SIGN_BIT, SIGN_BIT | |
| 58 | for %f16, SIGN_BIT, %f16 | |
| 59 | faddd %f0, %f16, %f6 | |
| 60 | fsubd %f6, %f16, %f0 | |
| 61 | fabsd %f0, %f0 | |
| 62 | for %f0, SIGN_BIT, %f0 | |
| 63 | retl | |
| 64 | ld [%sp + 88], %fsr | |
| 65 | END (__nearbyint_vis3) |