[thirdparty/glibc.git] / sysdeps / x86_64 / bits / atomic.h

/* Copyright (C) 2002, 2003, 2004, 2006 Free Software Foundation, Inc.
   This file is part of the GNU C Library.
   Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with the GNU C Library; if not, write to the Free
   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
   02111-1307 USA.  */

#include <stdint.h>
#include <tls.h>	/* For tcbhead_t.  */


typedef int8_t atomic8_t;
typedef uint8_t uatomic8_t;
typedef int_fast8_t atomic_fast8_t;
typedef uint_fast8_t uatomic_fast8_t;

typedef int16_t atomic16_t;
typedef uint16_t uatomic16_t;
typedef int_fast16_t atomic_fast16_t;
typedef uint_fast16_t uatomic_fast16_t;

typedef int32_t atomic32_t;
typedef uint32_t uatomic32_t;
typedef int_fast32_t atomic_fast32_t;
typedef uint_fast32_t uatomic_fast32_t;

typedef int64_t atomic64_t;
typedef uint64_t uatomic64_t;
typedef int_fast64_t atomic_fast64_t;
typedef uint_fast64_t uatomic_fast64_t;

typedef intptr_t atomicptr_t;
typedef uintptr_t uatomicptr_t;
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;


#ifndef LOCK_PREFIX
# ifdef UP
#  define LOCK_PREFIX	/* nothing */
# else
#  define LOCK_PREFIX "lock;"
# endif
#endif


#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
     __asm __volatile (LOCK_PREFIX "cmpxchgb %b2, %1"			      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "q" (newval), "m" (*mem), "0" (oldval));	      \
     ret; })

#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
     __asm __volatile (LOCK_PREFIX "cmpxchgw %w2, %1"			      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "r" (newval), "m" (*mem), "0" (oldval));	      \
     ret; })

#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
     __asm __volatile (LOCK_PREFIX "cmpxchgl %2, %1"			      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "r" (newval), "m" (*mem), "0" (oldval));	      \
     ret; })

#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
     __asm __volatile (LOCK_PREFIX "cmpxchgq %q2, %1"			      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "r" ((long int) (newval)), "m" (*mem),		      \
			 "0" ((long int) (oldval)));			      \
     ret; })


#define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
    __asm __volatile ("cmpl $0, %%fs:%P5\n\t"				      \
		      "je 0f\n\t"					      \
		      "lock\n"						      \
		       "0:\tcmpxchgb %b2, %1"				      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "q" (newval), "m" (*mem), "0" (oldval),	      \
			 "i" (offsetof (tcbhead_t, multiple_threads)));	      \
     ret; })

#define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
    __asm __volatile ("cmpl $0, %%fs:%P5\n\t"				      \
		      "je 0f\n\t"					      \
		      "lock\n"						      \
		       "0:\tcmpxchgw %w2, %1"				      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "q" (newval), "m" (*mem), "0" (oldval),	      \
			 "i" (offsetof (tcbhead_t, multiple_threads)));	      \
     ret; })

#define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
    __asm __volatile ("cmpl $0, %%fs:%P5\n\t"				      \
		      "je 0f\n\t"					      \
		      "lock\n"						      \
		       "0:\tcmpxchgl %2, %1"				      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "q" (newval), "m" (*mem), "0" (oldval),	      \
			 "i" (offsetof (tcbhead_t, multiple_threads)));	      \
     ret; })

#define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
  ({ __typeof (*mem) ret;						      \
     __asm __volatile ("cmpl $0, %%fs:%P5\n\t"				      \
		       "je 0f\n\t"					      \
		       "lock\n"						      \
		       "0:\tcmpxchgq %q2, %1"				      \
		       : "=a" (ret), "=m" (*mem)			      \
		       : "q" ((long int) (newval)), "m" (*mem),		      \
			 "0" ((long int)oldval),			      \
			 "i" (offsetof (tcbhead_t, multiple_threads)));	      \
     ret; })


/* Note that we need no lock prefix.  */
#define atomic_exchange_acq(mem, newvalue) \
  ({ __typeof (*mem) result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile ("xchgb %b0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (newvalue), "m" (*mem));			      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile ("xchgw %w0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (newvalue), "m" (*mem));			      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile ("xchgl %0, %1"					      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (newvalue), "m" (*mem));			      \
     else								      \
       __asm __volatile ("xchgq %q0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" ((long) (newvalue)), "m" (*mem));	      \
     result; })


#define __arch_exchange_and_add_body(lock, mem, value)			      \
  ({ __typeof (*mem) result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (lock "xaddb %b0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (value), "m" (*mem),			      \
			   "i" (offsetof (tcbhead_t, multiple_threads)));     \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (lock "xaddw %w0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (value), "m" (*mem),			      \
			   "i" (offsetof (tcbhead_t, multiple_threads)));     \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (lock "xaddl %0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" (value), "m" (*mem),			      \
			   "i" (offsetof (tcbhead_t, multiple_threads)));     \
     else								      \
       __asm __volatile (lock "xaddq %q0, %1"				      \
			 : "=r" (result), "=m" (*mem)			      \
			 : "0" ((long) (value)), "m" (*mem),		      \
			   "i" (offsetof (tcbhead_t, multiple_threads)));     \
     result; })

#define atomic_exchange_and_add(mem, value) \
  __arch_exchange_and_add_body (LOCK_PREFIX, mem, value)

#define __arch_exchange_and_add_cprefix \
  "cmpl $0, %%fs:%P4\n\tje 0f\n\tlock\n0:\t"

#define catomic_exchange_and_add(mem, value) \
  __arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, mem, value)


#define __arch_add_body(lock, pfx, mem, value)				      \
  do {									      \
    if (__builtin_constant_p (value) && (value) == 1)			      \
      pfx##_increment (mem);						      \
    else if (__builtin_constant_p (value) && (value) == -1)		      \
      pfx##_decrement (mem);						      \
    else if (sizeof (*mem) == 1)					      \
      __asm __volatile (lock "addb %b1, %0"				      \
			: "=m" (*mem)					      \
			: "ir" (value), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (lock "addw %w1, %0"				      \
			: "=m" (*mem)					      \
			: "ir" (value), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (lock "addl %1, %0"				      \
			: "=m" (*mem)					      \
			: "ir" (value), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else								      \
      __asm __volatile (lock "addq %q1, %0"				      \
			: "=m" (*mem)					      \
			: "ir" ((long) (value)), "m" (*mem),		      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
  } while (0)

#define atomic_add(mem, value) \
  __arch_add_body (LOCK_PREFIX, atomic, mem, value)

#define __arch_add_cprefix \
  "cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"

#define catomic_add(mem, value) \
  __arch_add_body (__arch_add_cprefix, catomic, mem, value)


#define atomic_add_negative(mem, value) \
  ({ unsigned char __result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else								      \
       __asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" ((long) (value)), "m" (*mem));		      \
     __result; })


#define atomic_add_zero(mem, value) \
  ({ unsigned char __result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" (value), "m" (*mem));			      \
     else								      \
       __asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "ir" ((long) (value)), "m" (*mem));		      \
     __result; })


#define __arch_increment_body(lock, mem) \
  do {									      \
    if (sizeof (*mem) == 1)						      \
      __asm __volatile (lock "incb %b0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (lock "incw %w0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (lock "incl %0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else								      \
      __asm __volatile (lock "incq %q0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
  } while (0)

#define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, mem)

#define __arch_increment_cprefix \
  "cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"

#define catomic_increment(mem) \
  __arch_increment_body (__arch_increment_cprefix, mem)


#define atomic_increment_and_test(mem) \
  ({ unsigned char __result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (LOCK_PREFIX "incb %b0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (LOCK_PREFIX "incw %w0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (LOCK_PREFIX "incl %0; sete %1"			      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else								      \
       __asm __volatile (LOCK_PREFIX "incq %q0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     __result; })


#define __arch_decrement_body(lock, mem) \
  do {									      \
    if (sizeof (*mem) == 1)						      \
      __asm __volatile (lock "decb %b0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (lock "decw %w0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (lock "decl %0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else								      \
      __asm __volatile (lock "decq %q0"					      \
			: "=m" (*mem)					      \
			: "m" (*mem),					      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
  } while (0)

#define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, mem)

#define __arch_decrement_cprefix \
  "cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"

#define catomic_decrement(mem) \
  __arch_decrement_body (__arch_decrement_cprefix, mem)


#define atomic_decrement_and_test(mem) \
  ({ unsigned char __result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (LOCK_PREFIX "decb %b0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (LOCK_PREFIX "decw %w0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (LOCK_PREFIX "decl %0; sete %1"			      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     else								      \
       __asm __volatile (LOCK_PREFIX "decq %q0; sete %1"		      \
			 : "=m" (*mem), "=qm" (__result)		      \
			 : "m" (*mem));					      \
     __result; })


#define atomic_bit_set(mem, bit) \
  do {									      \
    if (sizeof (*mem) == 1)						      \
      __asm __volatile (LOCK_PREFIX "orb %b2, %0"			      \
			: "=m" (*mem)					      \
			: "m" (*mem), "ir" (1L << (bit)));		      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (LOCK_PREFIX "orw %w2, %0"			      \
			: "=m" (*mem)					      \
			: "m" (*mem), "ir" (1L << (bit)));		      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (LOCK_PREFIX "orl %2, %0"			      \
			: "=m" (*mem)					      \
			: "m" (*mem), "ir" (1L << (bit)));		      \
    else if (__builtin_constant_p (bit) && (bit) < 32)			      \
      __asm __volatile (LOCK_PREFIX "orq %2, %0"			      \
			: "=m" (*mem)					      \
			: "m" (*mem), "i" (1L << (bit)));		      \
    else								      \
      __asm __volatile (LOCK_PREFIX "orq %q2, %0"			      \
			: "=m" (*mem)					      \
			: "m" (*mem), "r" (1UL << (bit)));		      \
  } while (0)


#define atomic_bit_test_set(mem, bit) \
  ({ unsigned char __result;						      \
     if (sizeof (*mem) == 1)						      \
       __asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0"		      \
			 : "=q" (__result), "=m" (*mem)			      \
			 : "m" (*mem), "ir" (bit));			      \
     else if (sizeof (*mem) == 2)					      \
       __asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0"		      \
			 : "=q" (__result), "=m" (*mem)			      \
			 : "m" (*mem), "ir" (bit));			      \
     else if (sizeof (*mem) == 4)					      \
       __asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0"		      \
			 : "=q" (__result), "=m" (*mem)			      \
			 : "m" (*mem), "ir" (bit));			      \
     else							      	      \
       __asm __volatile (LOCK_PREFIX "btsq %3, %1; setc %0"		      \
			 : "=q" (__result), "=m" (*mem)			      \
			 : "m" (*mem), "ir" (bit));			      \
     __result; })


#define atomic_delay() asm ("rep; nop")


#define atomic_and(mem, mask) \
  do {									      \
    if (sizeof (*mem) == 1)						      \
      __asm __volatile (LOCK_PREFIX "andb %1, %b0"			      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem));			      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (LOCK_PREFIX "andw %1, %w0"			      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem));			      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (LOCK_PREFIX "andl %1, %0"			      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem));			      \
    else								      \
      __asm __volatile (LOCK_PREFIX "andq %1, %q0"			      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem));			      \
  } while (0)


#define __arch_or_body(lock, mem, mask)					      \
  do {									      \
    if (sizeof (*mem) == 1)						      \
      __asm __volatile (lock "orb %1, %b0"				      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 2)					      \
      __asm __volatile (lock "orw %1, %w0"				      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else if (sizeof (*mem) == 4)					      \
      __asm __volatile (lock "orl %1, %0"				      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
    else								      \
      __asm __volatile (lock "orq %1, %q0"				      \
			: "=m" (*mem)					      \
			: "ir" (mask), "m" (*mem),			      \
			  "i" (offsetof (tcbhead_t, multiple_threads)));      \
  } while (0)

#define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask)

#define __arch_or_cprefix \
  "cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"

#define catomic_or(mem, mask) __arch_or_body (__arch_or_cprefix, mem, mask)
Commit	Line	Data
11bf311e	1	/* Copyright (C) 2002, 2003, 2004, 2006 Free Software Foundation, Inc.
c10c099c UD	2	This file is part of the GNU C Library.
	3	Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
	4
	5	The GNU C Library is free software; you can redistribute it and/or
	6	modify it under the terms of the GNU Lesser General Public
	7	License as published by the Free Software Foundation; either
	8	version 2.1 of the License, or (at your option) any later version.
	9
	10	The GNU C Library is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	Lesser General Public License for more details.
	14
	15	You should have received a copy of the GNU Lesser General Public
	16	License along with the GNU C Library; if not, write to the Free
	17	Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
	18	02111-1307 USA. */
	19
	20	#include <stdint.h>
11bf311e	21	#include <tls.h> /* For tcbhead_t. */
c10c099c UD	22
	23
	24	typedef int8_t atomic8_t;
	25	typedef uint8_t uatomic8_t;
	26	typedef int_fast8_t atomic_fast8_t;
	27	typedef uint_fast8_t uatomic_fast8_t;
	28
	29	typedef int16_t atomic16_t;
	30	typedef uint16_t uatomic16_t;
	31	typedef int_fast16_t atomic_fast16_t;
	32	typedef uint_fast16_t uatomic_fast16_t;
	33
	34	typedef int32_t atomic32_t;
	35	typedef uint32_t uatomic32_t;
	36	typedef int_fast32_t atomic_fast32_t;
	37	typedef uint_fast32_t uatomic_fast32_t;
	38
	39	typedef int64_t atomic64_t;
	40	typedef uint64_t uatomic64_t;
	41	typedef int_fast64_t atomic_fast64_t;
	42	typedef uint_fast64_t uatomic_fast64_t;
	43
	44	typedef intptr_t atomicptr_t;
	45	typedef uintptr_t uatomicptr_t;
	46	typedef intmax_t atomic_max_t;
	47	typedef uintmax_t uatomic_max_t;
	48
	49
bd4f43b4	50	#ifndef LOCK_PREFIX
c10c099c	51	# ifdef UP
bd4f43b4	52	# define LOCK_PREFIX /* nothing */
c10c099c	53	# else
bd4f43b4	54	# define LOCK_PREFIX "lock;"
c10c099c UD	55	# endif
	56	#endif
	57
	58
5a3ab2fc UD	59	#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
5a3ab2fc UD	60	({ __typeof (*mem) ret; \
bd4f43b4	61	__asm __volatile (LOCK_PREFIX "cmpxchgb %b2, %1" \
c10c099c	62	: "=a" (ret), "=m" (*mem) \
abfd53d1	63	: "q" (newval), "m" (*mem), "0" (oldval)); \
c10c099c UD	64	ret; })
c10c099c UD	65
5a3ab2fc UD	66	#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
5a3ab2fc UD	67	({ __typeof (*mem) ret; \
bd4f43b4	68	__asm __volatile (LOCK_PREFIX "cmpxchgw %w2, %1" \
c10c099c	69	: "=a" (ret), "=m" (*mem) \
abfd53d1	70	: "r" (newval), "m" (*mem), "0" (oldval)); \
c10c099c UD	71	ret; })
c10c099c UD	72
5a3ab2fc UD	73	#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
5a3ab2fc UD	74	({ __typeof (*mem) ret; \
bd4f43b4	75	__asm __volatile (LOCK_PREFIX "cmpxchgl %2, %1" \
c10c099c	76	: "=a" (ret), "=m" (*mem) \
abfd53d1	77	: "r" (newval), "m" (*mem), "0" (oldval)); \
c10c099c UD	78	ret; })
c10c099c UD	79
5a3ab2fc UD	80	#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
5a3ab2fc UD	81	({ __typeof (*mem) ret; \
bd4f43b4	82	__asm __volatile (LOCK_PREFIX "cmpxchgq %q2, %1" \
c10c099c	83	: "=a" (ret), "=m" (*mem) \
11bf311e UD	84	: "r" ((long int) (newval)), "m" (*mem), \
	85	"0" ((long int) (oldval))); \
	86	ret; })
	87
	88
	89	#define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \
	90	({ __typeof (*mem) ret; \
	91	__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
	92	"je 0f\n\t" \
	93	"lock\n" \
	94	"0:\tcmpxchgb %b2, %1" \
	95	: "=a" (ret), "=m" (*mem) \
	96	: "q" (newval), "m" (*mem), "0" (oldval), \
	97	"i" (offsetof (tcbhead_t, multiple_threads))); \
	98	ret; })
	99
	100	#define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \
	101	({ __typeof (*mem) ret; \
	102	__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
	103	"je 0f\n\t" \
	104	"lock\n" \
	105	"0:\tcmpxchgw %w2, %1" \
	106	: "=a" (ret), "=m" (*mem) \
	107	: "q" (newval), "m" (*mem), "0" (oldval), \
	108	"i" (offsetof (tcbhead_t, multiple_threads))); \
	109	ret; })
	110
	111	#define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \
	112	({ __typeof (*mem) ret; \
	113	__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
	114	"je 0f\n\t" \
	115	"lock\n" \
	116	"0:\tcmpxchgl %2, %1" \
	117	: "=a" (ret), "=m" (*mem) \
	118	: "q" (newval), "m" (*mem), "0" (oldval), \
	119	"i" (offsetof (tcbhead_t, multiple_threads))); \
	120	ret; })
	121
	122	#define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
	123	({ __typeof (*mem) ret; \
	124	__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
	125	"je 0f\n\t" \
	126	"lock\n" \
	127	"0:\tcmpxchgq %q2, %1" \
	128	: "=a" (ret), "=m" (*mem) \
	129	: "q" ((long int) (newval)), "m" (*mem), \
	130	"0" ((long int)oldval), \
	131	"i" (offsetof (tcbhead_t, multiple_threads))); \
8099361e UD	132	ret; })
	133
	134
f79466a8	135	/* Note that we need no lock prefix. */
949ec764	136	#define atomic_exchange_acq(mem, newvalue) \
f79466a8 UD	137	({ __typeof (*mem) result; \
	138	if (sizeof (*mem) == 1) \
	139	__asm __volatile ("xchgb %b0, %1" \
	140	: "=r" (result), "=m" (*mem) \
abfd53d1	141	: "0" (newvalue), "m" (*mem)); \
f79466a8 UD	142	else if (sizeof (*mem) == 2) \
	143	__asm __volatile ("xchgw %w0, %1" \
	144	: "=r" (result), "=m" (*mem) \
abfd53d1	145	: "0" (newvalue), "m" (*mem)); \
f79466a8 UD	146	else if (sizeof (*mem) == 4) \
	147	__asm __volatile ("xchgl %0, %1" \
	148	: "=r" (result), "=m" (*mem) \
abfd53d1	149	: "0" (newvalue), "m" (*mem)); \
f79466a8 UD	150	else \
	151	__asm __volatile ("xchgq %q0, %1" \
	152	: "=r" (result), "=m" (*mem) \
859e708f	153	: "0" ((long) (newvalue)), "m" (*mem)); \
f79466a8 UD	154	result; })
	155
	156
11bf311e	157	#define __arch_exchange_and_add_body(lock, mem, value) \
c10c099c UD	158	({ __typeof (*mem) result; \
c10c099c UD	159	if (sizeof (*mem) == 1) \
11bf311e	160	__asm __volatile (lock "xaddb %b0, %1" \
c10c099c	161	: "=r" (result), "=m" (*mem) \
11bf311e UD	162	: "0" (value), "m" (*mem), \
11bf311e UD	163	"i" (offsetof (tcbhead_t, multiple_threads))); \
c10c099c	164	else if (sizeof (*mem) == 2) \
11bf311e	165	__asm __volatile (lock "xaddw %w0, %1" \
c10c099c	166	: "=r" (result), "=m" (*mem) \
11bf311e UD	167	: "0" (value), "m" (*mem), \
11bf311e UD	168	"i" (offsetof (tcbhead_t, multiple_threads))); \
c10c099c	169	else if (sizeof (*mem) == 4) \
11bf311e	170	__asm __volatile (lock "xaddl %0, %1" \
c10c099c	171	: "=r" (result), "=m" (*mem) \
11bf311e UD	172	: "0" (value), "m" (*mem), \
11bf311e UD	173	"i" (offsetof (tcbhead_t, multiple_threads))); \
c10c099c	174	else \
11bf311e	175	__asm __volatile (lock "xaddq %q0, %1" \
c10c099c	176	: "=r" (result), "=m" (*mem) \
11bf311e UD	177	: "0" ((long) (value)), "m" (*mem), \
11bf311e UD	178	"i" (offsetof (tcbhead_t, multiple_threads))); \
c10c099c UD	179	result; })
c10c099c UD	180
11bf311e UD	181	#define atomic_exchange_and_add(mem, value) \
	182	__arch_exchange_and_add_body (LOCK_PREFIX, mem, value)
	183
	184	#define __arch_exchange_and_add_cprefix \
	185	"cmpl $0, %%fs:%P4\n\tje 0f\n\tlock\n0:\t"
	186
	187	#define catomic_exchange_and_add(mem, value) \
	188	__arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, mem, value)
	189
	190
	191	#define __arch_add_body(lock, pfx, mem, value) \
	192	do { \
	193	if (__builtin_constant_p (value) && (value) == 1) \
	194	pfx##_increment (mem); \
	195	else if (__builtin_constant_p (value) && (value) == -1) \
	196	pfx##_decrement (mem); \
	197	else if (sizeof (*mem) == 1) \
	198	__asm __volatile (lock "addb %b1, %0" \
	199	: "=m" (*mem) \
	200	: "ir" (value), "m" (*mem), \
	201	"i" (offsetof (tcbhead_t, multiple_threads))); \
	202	else if (sizeof (*mem) == 2) \
	203	__asm __volatile (lock "addw %w1, %0" \
	204	: "=m" (*mem) \
	205	: "ir" (value), "m" (*mem), \
	206	"i" (offsetof (tcbhead_t, multiple_threads))); \
	207	else if (sizeof (*mem) == 4) \
	208	__asm __volatile (lock "addl %1, %0" \
	209	: "=m" (*mem) \
	210	: "ir" (value), "m" (*mem), \
	211	"i" (offsetof (tcbhead_t, multiple_threads))); \
	212	else \
	213	__asm __volatile (lock "addq %q1, %0" \
	214	: "=m" (*mem) \
	215	: "ir" ((long) (value)), "m" (*mem), \
	216	"i" (offsetof (tcbhead_t, multiple_threads))); \
	217	} while (0)
c10c099c UD	218
c10c099c UD	219	#define atomic_add(mem, value) \
11bf311e UD	220	__arch_add_body (LOCK_PREFIX, atomic, mem, value)
	221
	222	#define __arch_add_cprefix \
	223	"cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"
	224
	225	#define catomic_add(mem, value) \
	226	__arch_add_body (__arch_add_cprefix, catomic, mem, value)
c10c099c UD	227
	228
	229	#define atomic_add_negative(mem, value) \
	230	({ unsigned char __result; \
	231	if (sizeof (*mem) == 1) \
bd4f43b4	232	__asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1" \
c10c099c	233	: "=m" (*mem), "=qm" (__result) \
abfd53d1	234	: "ir" (value), "m" (*mem)); \
c10c099c	235	else if (sizeof (*mem) == 2) \
bd4f43b4	236	__asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1" \
c10c099c	237	: "=m" (*mem), "=qm" (__result) \
abfd53d1	238	: "ir" (value), "m" (*mem)); \
c10c099c	239	else if (sizeof (*mem) == 4) \
bd4f43b4	240	__asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1" \
c10c099c	241	: "=m" (*mem), "=qm" (__result) \
abfd53d1	242	: "ir" (value), "m" (*mem)); \
c10c099c	243	else \
bd4f43b4	244	__asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1" \
c10c099c	245	: "=m" (*mem), "=qm" (__result) \
859e708f	246	: "ir" ((long) (value)), "m" (*mem)); \
c10c099c UD	247	__result; })
	248
	249
	250	#define atomic_add_zero(mem, value) \
	251	({ unsigned char __result; \
	252	if (sizeof (*mem) == 1) \
bd4f43b4	253	__asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1" \
c10c099c	254	: "=m" (*mem), "=qm" (__result) \
abfd53d1	255	: "ir" (value), "m" (*mem)); \
c10c099c	256	else if (sizeof (*mem) == 2) \
bd4f43b4	257	__asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1" \
c10c099c	258	: "=m" (*mem), "=qm" (__result) \
abfd53d1	259	: "ir" (value), "m" (*mem)); \
c10c099c	260	else if (sizeof (*mem) == 4) \
bd4f43b4	261	__asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1" \
c10c099c	262	: "=m" (*mem), "=qm" (__result) \
abfd53d1	263	: "ir" (value), "m" (*mem)); \
c10c099c	264	else \
bd4f43b4	265	__asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1" \
c10c099c	266	: "=m" (*mem), "=qm" (__result) \
859e708f	267	: "ir" ((long) (value)), "m" (*mem)); \
c10c099c UD	268	__result; })
	269
	270
11bf311e UD	271	#define __arch_increment_body(lock, mem) \
	272	do { \
	273	if (sizeof (*mem) == 1) \
	274	__asm __volatile (lock "incb %b0" \
	275	: "=m" (*mem) \
	276	: "m" (*mem), \
	277	"i" (offsetof (tcbhead_t, multiple_threads))); \
	278	else if (sizeof (*mem) == 2) \
	279	__asm __volatile (lock "incw %w0" \
	280	: "=m" (*mem) \
	281	: "m" (*mem), \
	282	"i" (offsetof (tcbhead_t, multiple_threads))); \
	283	else if (sizeof (*mem) == 4) \
	284	__asm __volatile (lock "incl %0" \
	285	: "=m" (*mem) \
	286	: "m" (*mem), \
	287	"i" (offsetof (tcbhead_t, multiple_threads))); \
	288	else \
	289	__asm __volatile (lock "incq %q0" \
	290	: "=m" (*mem) \
	291	: "m" (*mem), \
	292	"i" (offsetof (tcbhead_t, multiple_threads))); \
	293	} while (0)
	294
	295	#define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, mem)
	296
	297	#define __arch_increment_cprefix \
	298	"cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"
	299
	300	#define catomic_increment(mem) \
	301	__arch_increment_body (__arch_increment_cprefix, mem)
8099361e	302
c10c099c UD	303
	304	#define atomic_increment_and_test(mem) \
	305	({ unsigned char __result; \
	306	if (sizeof (*mem) == 1) \
bd4f43b4	307	__asm __volatile (LOCK_PREFIX "incb %b0; sete %1" \
c10c099c	308	: "=m" (*mem), "=qm" (__result) \
abfd53d1	309	: "m" (*mem)); \
c10c099c	310	else if (sizeof (*mem) == 2) \
bd4f43b4	311	__asm __volatile (LOCK_PREFIX "incw %w0; sete %1" \
c10c099c	312	: "=m" (*mem), "=qm" (__result) \
abfd53d1	313	: "m" (*mem)); \
c10c099c	314	else if (sizeof (*mem) == 4) \
bd4f43b4	315	__asm __volatile (LOCK_PREFIX "incl %0; sete %1" \
c10c099c	316	: "=m" (*mem), "=qm" (__result) \
abfd53d1	317	: "m" (*mem)); \
c10c099c	318	else \
bd4f43b4	319	__asm __volatile (LOCK_PREFIX "incq %q0; sete %1" \
c10c099c	320	: "=m" (*mem), "=qm" (__result) \
abfd53d1	321	: "m" (*mem)); \
c10c099c UD	322	__result; })
	323
	324
11bf311e UD	325	#define __arch_decrement_body(lock, mem) \
	326	do { \
	327	if (sizeof (*mem) == 1) \
	328	__asm __volatile (lock "decb %b0" \
	329	: "=m" (*mem) \
	330	: "m" (*mem), \
	331	"i" (offsetof (tcbhead_t, multiple_threads))); \
	332	else if (sizeof (*mem) == 2) \
	333	__asm __volatile (lock "decw %w0" \
	334	: "=m" (*mem) \
	335	: "m" (*mem), \
	336	"i" (offsetof (tcbhead_t, multiple_threads))); \
	337	else if (sizeof (*mem) == 4) \
	338	__asm __volatile (lock "decl %0" \
	339	: "=m" (*mem) \
	340	: "m" (*mem), \
	341	"i" (offsetof (tcbhead_t, multiple_threads))); \
	342	else \
	343	__asm __volatile (lock "decq %q0" \
	344	: "=m" (*mem) \
	345	: "m" (*mem), \
	346	"i" (offsetof (tcbhead_t, multiple_threads))); \
	347	} while (0)
	348
	349	#define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, mem)
	350
	351	#define __arch_decrement_cprefix \
	352	"cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"
	353
	354	#define catomic_decrement(mem) \
	355	__arch_decrement_body (__arch_decrement_cprefix, mem)
8099361e	356
c10c099c UD	357
	358	#define atomic_decrement_and_test(mem) \
	359	({ unsigned char __result; \
	360	if (sizeof (*mem) == 1) \
bd4f43b4	361	__asm __volatile (LOCK_PREFIX "decb %b0; sete %1" \
c10c099c	362	: "=m" (*mem), "=qm" (__result) \
abfd53d1	363	: "m" (*mem)); \
c10c099c	364	else if (sizeof (*mem) == 2) \
bd4f43b4	365	__asm __volatile (LOCK_PREFIX "decw %w0; sete %1" \
c10c099c	366	: "=m" (*mem), "=qm" (__result) \
abfd53d1	367	: "m" (*mem)); \
c10c099c	368	else if (sizeof (*mem) == 4) \
bd4f43b4	369	__asm __volatile (LOCK_PREFIX "decl %0; sete %1" \
c10c099c	370	: "=m" (*mem), "=qm" (__result) \
abfd53d1	371	: "m" (*mem)); \
c10c099c	372	else \
bd4f43b4	373	__asm __volatile (LOCK_PREFIX "decq %q0; sete %1" \
c10c099c	374	: "=m" (*mem), "=qm" (__result) \
abfd53d1	375	: "m" (*mem)); \
c10c099c UD	376	__result; })
	377
	378
	379	#define atomic_bit_set(mem, bit) \
11bf311e UD	380	do { \
	381	if (sizeof (*mem) == 1) \
	382	__asm __volatile (LOCK_PREFIX "orb %b2, %0" \
	383	: "=m" (*mem) \
	384	: "m" (*mem), "ir" (1L << (bit))); \
	385	else if (sizeof (*mem) == 2) \
	386	__asm __volatile (LOCK_PREFIX "orw %w2, %0" \
	387	: "=m" (*mem) \
	388	: "m" (*mem), "ir" (1L << (bit))); \
	389	else if (sizeof (*mem) == 4) \
	390	__asm __volatile (LOCK_PREFIX "orl %2, %0" \
	391	: "=m" (*mem) \
	392	: "m" (*mem), "ir" (1L << (bit))); \
	393	else if (__builtin_constant_p (bit) && (bit) < 32) \
	394	__asm __volatile (LOCK_PREFIX "orq %2, %0" \
	395	: "=m" (*mem) \
	396	: "m" (*mem), "i" (1L << (bit))); \
	397	else \
	398	__asm __volatile (LOCK_PREFIX "orq %q2, %0" \
	399	: "=m" (*mem) \
	400	: "m" (*mem), "r" (1UL << (bit))); \
	401	} while (0)
c10c099c UD	402
	403
	404	#define atomic_bit_test_set(mem, bit) \
	405	({ unsigned char __result; \
	406	if (sizeof (*mem) == 1) \
bd4f43b4	407	__asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0" \
c10c099c	408	: "=q" (__result), "=m" (*mem) \
002ff853	409	: "m" (*mem), "ir" (bit)); \
c10c099c	410	else if (sizeof (*mem) == 2) \
bd4f43b4	411	__asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0" \
c10c099c	412	: "=q" (__result), "=m" (*mem) \
002ff853	413	: "m" (*mem), "ir" (bit)); \
c10c099c	414	else if (sizeof (*mem) == 4) \
bd4f43b4	415	__asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0" \
c10c099c	416	: "=q" (__result), "=m" (*mem) \
002ff853	417	: "m" (*mem), "ir" (bit)); \
c10c099c	418	else \
bd4f43b4	419	__asm __volatile (LOCK_PREFIX "btsq %3, %1; setc %0" \
c10c099c	420	: "=q" (__result), "=m" (*mem) \
002ff853	421	: "m" (*mem), "ir" (bit)); \
c10c099c	422	__result; })
f377d022 UD	423
	424
	425	#define atomic_delay() asm ("rep; nop")
11bf311e UD	426
	427
	428	#define atomic_and(mem, mask) \
	429	do { \
	430	if (sizeof (*mem) == 1) \
	431	__asm __volatile (LOCK_PREFIX "andb %1, %b0" \
	432	: "=m" (*mem) \
	433	: "ir" (mask), "m" (*mem)); \
	434	else if (sizeof (*mem) == 2) \
	435	__asm __volatile (LOCK_PREFIX "andw %1, %w0" \
	436	: "=m" (*mem) \
	437	: "ir" (mask), "m" (*mem)); \
	438	else if (sizeof (*mem) == 4) \
	439	__asm __volatile (LOCK_PREFIX "andl %1, %0" \
	440	: "=m" (*mem) \
	441	: "ir" (mask), "m" (*mem)); \
	442	else \
	443	__asm __volatile (LOCK_PREFIX "andq %1, %q0" \
	444	: "=m" (*mem) \
	445	: "ir" (mask), "m" (*mem)); \
	446	} while (0)
	447
	448
	449	#define __arch_or_body(lock, mem, mask) \
	450	do { \
	451	if (sizeof (*mem) == 1) \
	452	__asm __volatile (lock "orb %1, %b0" \
	453	: "=m" (*mem) \
	454	: "ir" (mask), "m" (*mem), \
	455	"i" (offsetof (tcbhead_t, multiple_threads))); \
	456	else if (sizeof (*mem) == 2) \
	457	__asm __volatile (lock "orw %1, %w0" \
	458	: "=m" (*mem) \
	459	: "ir" (mask), "m" (*mem), \
	460	"i" (offsetof (tcbhead_t, multiple_threads))); \
	461	else if (sizeof (*mem) == 4) \
	462	__asm __volatile (lock "orl %1, %0" \
	463	: "=m" (*mem) \
	464	: "ir" (mask), "m" (*mem), \
	465	"i" (offsetof (tcbhead_t, multiple_threads))); \
	466	else \
	467	__asm __volatile (lock "orq %1, %q0" \
	468	: "=m" (*mem) \
	469	: "ir" (mask), "m" (*mem), \
	470	"i" (offsetof (tcbhead_t, multiple_threads))); \
	471	} while (0)
	472
	473	#define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask)
	474
	475	#define __arch_or_cprefix \
	476	"cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"
	477
	478	#define catomic_or(mem, mask) __arch_or_body (__arch_or_cprefix, mem, mask)