[thirdparty/u-boot.git] / tools / prelink-riscv.inc

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Andes Technology
 * Chih-Mao Chen <cmchen@andestech.com>
 *
 * Statically process runtime relocations on RISC-V ELF images
 * so that it can be directly executed when loaded at LMA
 * without fixup. Both RV32 and RV64 are supported.
 */

#define CONCAT_IMPL(x, y) x##y
#define CONCAT(x, y) CONCAT_IMPL(x, y)
#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)

#define prelink_bonn    CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
#define uintnn_t        CONCAT3(uint, PRELINK_INC_BITS, _t)
#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
#define Elf_Ehdr        CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
#define Elf_Phdr        CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
#define Elf_Rela        CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
#define Elf_Sym         CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
#define Elf_Dyn         CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
#define Elf_Addr        CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
#define ELF_R_TYPE      CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
#define ELF_R_SYM       CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)

static void *get_offset_bonn(void *data, Elf_Phdr *phdrs, size_t phnum, Elf_Addr addr)
{
	Elf_Phdr *p;

	for (p = phdrs; p < phdrs + phnum; ++p)
		if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
			return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));

	return NULL;
}

static void prelink_bonn(void *data)
{
	Elf_Ehdr *ehdr = data;
	Elf_Phdr *p;
	Elf_Dyn *dyn;
	Elf_Rela *r;

	if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
		die("Machine type is not RISC-V");

	Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);

	Elf_Dyn *dyns = NULL;
	for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
		if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
			dyns = data + targetnn_to_cpu(p->p_offset);
			break;
		}
	}

	if (dyns == NULL)
		die("No dynamic section found");

	Elf_Rela *rela_dyn = NULL;
	size_t rela_count = 0;
	Elf_Sym *dynsym = NULL;
	for (dyn = dyns; ; ++dyn) {
		if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
			break;
		else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
			rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
		else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
			rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
		else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
			dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));

	}

	if (rela_dyn == NULL)
		die("No .rela.dyn found");

	if (dynsym == NULL)
		die("No .dynsym found");

	for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
		void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));

		if (buf == NULL)
			continue;

		if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
			*((uintnn_t *)buf) = r->r_addend;
		else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
			*((uint32_t *)buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
		else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
			*((uint64_t *)buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
	}
}

#undef prelink_bonn
#undef uintnn_t
#undef get_offset_bonn
#undef Elf_Ehdr
#undef Elf_Phdr
#undef Elf_Rela
#undef Elf_Sym
#undef Elf_Dyn
#undef Elf_Addr
#undef ELF_R_TYPE
#undef ELF_R_SYM
#undef target16_to_cpu
#undef target32_to_cpu
#undef target64_to_cpu
#undef targetnn_to_cpu
#undef cpu_to_target32
#undef cpu_to_target64

#undef CONCAT_IMPL
#undef CONCAT
#undef CONCAT3
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
42ac26f2 RC	2	/*
	3	* Copyright (C) 2017 Andes Technology
	4	* Chih-Mao Chen <cmchen@andestech.com>
	5	*
42ac26f2 RC	6	* Statically process runtime relocations on RISC-V ELF images
	7	* so that it can be directly executed when loaded at LMA
	8	* without fixup. Both RV32 and RV64 are supported.
	9	*/
	10
	11	#define CONCAT_IMPL(x, y) x##y
	12	#define CONCAT(x, y) CONCAT_IMPL(x, y)
	13	#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
	14
4539926a	15	#define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
42ac26f2	16	#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
4539926a	17	#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
42ac26f2 RC	18	#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
	19	#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
	20	#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
	21	#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
	22	#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
	23	#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
	24	#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
	25	#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
4539926a MC	26	#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
	27	#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
	28	#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
	29	#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
71bdfcb2 MC	30	#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
71bdfcb2 MC	31	#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
42ac26f2	32
fb3cc482	33	static void get_offset_bonn(void data, Elf_Phdr *phdrs, size_t phnum, Elf_Addr addr)
42ac26f2 RC	34	{
	35	Elf_Phdr *p;
	36
	37	for (p = phdrs; p < phdrs + phnum; ++p)
4539926a MC	38	if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
4539926a MC	39	return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
42ac26f2 RC	40
	41	return NULL;
	42	}
	43
4539926a	44	static void prelink_bonn(void *data)
42ac26f2 RC	45	{
	46	Elf_Ehdr *ehdr = data;
	47	Elf_Phdr *p;
	48	Elf_Dyn *dyn;
	49	Elf_Rela *r;
	50
4539926a	51	if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
42ac26f2 RC	52	die("Machine type is not RISC-V");
42ac26f2 RC	53
4539926a	54	Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
42ac26f2 RC	55
42ac26f2 RC	56	Elf_Dyn *dyns = NULL;
4539926a MC	57	for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
	58	if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
	59	dyns = data + targetnn_to_cpu(p->p_offset);
42ac26f2 RC	60	break;
	61	}
	62	}
	63
	64	if (dyns == NULL)
	65	die("No dynamic section found");
	66
	67	Elf_Rela *rela_dyn = NULL;
	68	size_t rela_count = 0;
	69	Elf_Sym *dynsym = NULL;
fb3cc482	70	for (dyn = dyns; ; ++dyn) {
4539926a	71	if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
42ac26f2	72	break;
4539926a MC	73	else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
	74	rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
	75	else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
fb3cc482	76	rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
4539926a MC	77	else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
4539926a MC	78	dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
42ac26f2 RC	79
	80	}
	81
	82	if (rela_dyn == NULL)
	83	die("No .rela.dyn found");
	84
	85	if (dynsym == NULL)
	86	die("No .dynsym found");
	87
	88	for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
4539926a	89	void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
42ac26f2 RC	90
	91	if (buf == NULL)
	92	continue;
	93
4539926a	94	if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
fb3cc482	95	((uintnn_t )buf) = r->r_addend;
4539926a	96	else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
fb3cc482	97	((uint32_t )buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
4539926a	98	else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
fb3cc482	99	((uint64_t )buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
42ac26f2 RC	100	}
	101	}
	102
4539926a	103	#undef prelink_bonn
42ac26f2	104	#undef uintnn_t
4539926a	105	#undef get_offset_bonn
42ac26f2 RC	106	#undef Elf_Ehdr
	107	#undef Elf_Phdr
	108	#undef Elf_Rela
	109	#undef Elf_Sym
	110	#undef Elf_Dyn
	111	#undef Elf_Addr
	112	#undef ELF_R_TYPE
	113	#undef ELF_R_SYM
4539926a MC	114	#undef target16_to_cpu
	115	#undef target32_to_cpu
	116	#undef target64_to_cpu
	117	#undef targetnn_to_cpu
71bdfcb2 MC	118	#undef cpu_to_target32
71bdfcb2 MC	119	#undef cpu_to_target64
42ac26f2 RC	120
	121	#undef CONCAT_IMPL
	122	#undef CONCAT
	123	#undef CONCAT3