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1 | ;; Arm M-profile Vector Extension Machine Description | |
2 | ;; Copyright (C) 2019-2020 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but | |
12 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | ;; General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32") | |
21 | (V2DI "u64")]) | |
22 | (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) | |
23 | (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) | |
24 | (define_mode_iterator MVE_0 [V8HF V4SF]) | |
25 | (define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI]) | |
26 | (define_mode_iterator MVE_3 [V16QI V8HI]) | |
27 | (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) | |
28 | (define_mode_iterator MVE_5 [V8HI V4SI]) | |
29 | ||
30 | (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F | |
31 | VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F | |
32 | VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S | |
33 | VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S | |
34 | VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U | |
35 | VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S | |
36 | VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S | |
37 | VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S | |
38 | VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S | |
39 | VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U | |
40 | VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT | |
41 | VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F | |
42 | VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U | |
43 | VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S | |
44 | VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S | |
45 | VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S | |
46 | VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S | |
47 | VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S | |
48 | VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S | |
49 | VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S | |
50 | VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S | |
51 | VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S | |
52 | VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S | |
53 | VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S | |
54 | VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U | |
55 | VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U | |
56 | VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U | |
57 | VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U | |
58 | VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U | |
59 | VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U | |
60 | VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U | |
61 | VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U | |
62 | VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U | |
63 | VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S | |
64 | VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S | |
65 | VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S | |
66 | VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S | |
67 | VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S | |
68 | VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S | |
69 | VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F | |
70 | VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F | |
71 | VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F | |
72 | VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F | |
73 | VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F | |
74 | VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F | |
75 | VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F | |
76 | VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U | |
77 | VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M | |
78 | VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32 | |
79 | VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S | |
80 | VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S | |
81 | VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S | |
82 | VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U | |
83 | VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S | |
84 | VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S | |
85 | VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S | |
86 | VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S | |
87 | VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P | |
88 | VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F | |
89 | VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U | |
90 | VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S | |
91 | VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U | |
92 | VRMLALDAVHAQ_U]) | |
93 | ||
94 | (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") | |
95 | (V8HF "V8HI") (V4SF "V4SI")]) | |
96 | ||
97 | (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") | |
98 | (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") | |
99 | (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") | |
100 | (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") | |
101 | (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") | |
102 | (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") | |
103 | (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") | |
104 | (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u") | |
105 | (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s") | |
106 | (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") | |
107 | (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") | |
108 | (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") | |
109 | (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u") | |
110 | (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") | |
111 | (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u") | |
112 | (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s") | |
113 | (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s") | |
114 | (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s") | |
115 | (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u") | |
116 | (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s") | |
117 | (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u") | |
118 | (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s") | |
119 | (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") | |
120 | (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") | |
121 | (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") | |
122 | (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") | |
123 | (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") | |
124 | (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") | |
125 | (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") | |
126 | (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u") | |
127 | (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s") | |
128 | (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u") | |
129 | (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s") | |
130 | (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u") | |
131 | (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s") | |
132 | (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s") | |
133 | (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u") | |
134 | (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s") | |
135 | (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u") | |
136 | (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s") | |
137 | (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u") | |
138 | (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s") | |
139 | (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u") | |
140 | (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s") | |
141 | (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u") | |
142 | (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s") | |
143 | (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u") | |
144 | (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") | |
145 | (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u") | |
146 | (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u") | |
147 | (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s") | |
148 | (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u") | |
149 | (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u") | |
150 | (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") | |
151 | (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s") | |
152 | (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u") | |
153 | (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u") | |
154 | (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s") | |
155 | (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s") | |
156 | (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u") | |
157 | (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s") | |
158 | (VSHLCQ_U "u")]) | |
159 | ||
160 | (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") | |
161 | (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") | |
162 | (VCTP32Q_M "32") (VCTP64Q_M "64")]) | |
163 | (define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") | |
164 | (V4SI "mve_imm_32")]) | |
165 | (define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) | |
166 | (define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")]) | |
167 | ||
168 | (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) | |
169 | (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) | |
170 | (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) | |
171 | (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) | |
172 | (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) | |
173 | (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) | |
174 | (define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) | |
175 | (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) | |
176 | (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) | |
177 | (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) | |
178 | (define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S]) | |
179 | (define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U]) | |
180 | (define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S]) | |
181 | (define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U]) | |
182 | (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) | |
183 | (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) | |
184 | (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) | |
185 | (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) | |
186 | (define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M]) | |
187 | (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) | |
188 | (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) | |
189 | (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) | |
190 | (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) | |
191 | (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U]) | |
192 | (define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S]) | |
193 | (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U]) | |
194 | (define_int_iterator VABDQ [VABDQ_S VABDQ_U]) | |
195 | (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U]) | |
196 | (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U]) | |
197 | (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S]) | |
198 | (define_int_iterator VANDQ [VANDQ_U VANDQ_S]) | |
199 | (define_int_iterator VBICQ [VBICQ_S VBICQ_U]) | |
200 | (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S]) | |
201 | (define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U]) | |
202 | (define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) | |
203 | (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) | |
204 | (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) | |
205 | (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) | |
206 | (define_int_iterator VEORQ [VEORQ_U VEORQ_S]) | |
207 | (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) | |
208 | (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) | |
209 | (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) | |
210 | (define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S]) | |
211 | (define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S]) | |
212 | (define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S]) | |
213 | (define_int_iterator VMINQ [VMINQ_S VMINQ_U]) | |
214 | (define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S]) | |
215 | (define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S]) | |
216 | (define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U]) | |
217 | (define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S]) | |
218 | (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S]) | |
219 | (define_int_iterator VMULQ [VMULQ_U VMULQ_S]) | |
220 | (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S]) | |
221 | (define_int_iterator VORNQ [VORNQ_U VORNQ_S]) | |
222 | (define_int_iterator VORRQ [VORRQ_S VORRQ_U]) | |
223 | (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S]) | |
224 | (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U]) | |
225 | (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U]) | |
226 | (define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U]) | |
227 | (define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U]) | |
228 | (define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U]) | |
229 | (define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S]) | |
230 | (define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S]) | |
231 | (define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U]) | |
232 | (define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U]) | |
233 | (define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U]) | |
234 | (define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U]) | |
235 | (define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S]) | |
236 | (define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U]) | |
237 | (define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S]) | |
238 | (define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U]) | |
239 | (define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U]) | |
240 | (define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U]) | |
241 | (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U]) | |
242 | (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U]) | |
243 | (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S]) | |
244 | (define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S]) | |
245 | (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S]) | |
246 | (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) | |
247 | (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) | |
248 | (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S]) | |
249 | (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S]) | |
250 | (define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U]) | |
251 | (define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S]) | |
252 | (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) | |
253 | (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U]) | |
254 | (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U]) | |
255 | (define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U]) | |
256 | (define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S]) | |
257 | (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U]) | |
258 | (define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U]) | |
259 | (define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U]) | |
260 | ||
261 | (define_insn "*mve_mov<mode>" | |
262 | [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") | |
263 | (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Usi,r,Dm,w"))] | |
264 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
265 | { | |
266 | if (which_alternative == 3 || which_alternative == 6) | |
267 | { | |
268 | int width, is_valid; | |
269 | static char templ[40]; | |
270 | ||
271 | is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode, | |
272 | &operands[1], &width); | |
273 | ||
274 | gcc_assert (is_valid != 0); | |
275 | ||
276 | if (width == 0) | |
277 | return "vmov.f32\t%q0, %1 @ <mode>"; | |
278 | else | |
279 | sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width); | |
280 | return templ; | |
281 | } | |
282 | switch (which_alternative) | |
283 | { | |
284 | case 0: | |
285 | return "vmov\t%q0, %q1"; | |
286 | case 1: | |
287 | return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1"; | |
288 | case 2: | |
289 | return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1"; | |
290 | case 4: | |
291 | if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode)) | |
292 | || (MEM_P (operands[1]) | |
293 | && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF)) | |
294 | return output_move_neon (operands); | |
295 | else | |
296 | return "vldrb.8 %q0, %E1"; | |
297 | case 5: | |
298 | return output_move_neon (operands); | |
299 | case 7: | |
300 | return "vstrb.8 %q1, %E0"; | |
301 | default: | |
302 | gcc_unreachable (); | |
303 | return ""; | |
304 | } | |
305 | } | |
306 | [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store") | |
307 | (set_attr "length" "4,8,8,4,8,8,4,4") | |
308 | (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") | |
309 | (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) | |
310 | ||
311 | (define_insn "*mve_mov<mode>" | |
312 | [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w") | |
313 | (vec_duplicate:MVE_types | |
314 | (match_operand:SI 1 "nonmemory_operand" "r,i")))] | |
315 | "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" | |
316 | { | |
317 | if (which_alternative == 0) | |
318 | return "vdup.<V_sz_elem>\t%q0, %1"; | |
319 | return "vmov.<V_sz_elem>\t%q0, %1"; | |
320 | } | |
321 | [(set_attr "length" "4,4") | |
322 | (set_attr "type" "mve_move,mve_move")]) | |
323 | ||
324 | ;; | |
325 | ;; [vst4q]) | |
326 | ;; | |
327 | (define_insn "mve_vst4q<mode>" | |
328 | [(set (match_operand:XI 0 "neon_struct_operand" "=Um") | |
329 | (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") | |
330 | (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | |
331 | VST4Q)) | |
332 | ] | |
333 | "TARGET_HAVE_MVE" | |
334 | { | |
335 | rtx ops[6]; | |
336 | int regno = REGNO (operands[1]); | |
337 | ops[0] = gen_rtx_REG (TImode, regno); | |
338 | ops[1] = gen_rtx_REG (TImode, regno+4); | |
339 | ops[2] = gen_rtx_REG (TImode, regno+8); | |
340 | ops[3] = gen_rtx_REG (TImode, regno+12); | |
341 | rtx reg = operands[0]; | |
342 | while (reg && !REG_P (reg)) | |
343 | reg = XEXP (reg, 0); | |
344 | gcc_assert (REG_P (reg)); | |
345 | ops[4] = reg; | |
346 | ops[5] = operands[0]; | |
347 | /* Here in first three instructions data is stored to ops[4]'s location but | |
348 | in the fourth instruction data is stored to operands[0], this is to | |
349 | support the writeback. */ | |
350 | output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
351 | "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
352 | "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" | |
353 | "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); | |
354 | return ""; | |
355 | } | |
356 | [(set_attr "length" "16")]) | |
357 | ||
358 | ;; | |
359 | ;; [vrndxq_f]) | |
360 | ;; | |
361 | (define_insn "mve_vrndxq_f<mode>" | |
362 | [ | |
363 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
364 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
365 | VRNDXQ_F)) | |
366 | ] | |
367 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
368 | "vrintx.f%#<V_sz_elem> %q0, %q1" | |
369 | [(set_attr "type" "mve_move") | |
370 | ]) | |
371 | ||
372 | ;; | |
373 | ;; [vrndq_f]) | |
374 | ;; | |
375 | (define_insn "mve_vrndq_f<mode>" | |
376 | [ | |
377 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
378 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
379 | VRNDQ_F)) | |
380 | ] | |
381 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
382 | "vrintz.f%#<V_sz_elem> %q0, %q1" | |
383 | [(set_attr "type" "mve_move") | |
384 | ]) | |
385 | ||
386 | ;; | |
387 | ;; [vrndpq_f]) | |
388 | ;; | |
389 | (define_insn "mve_vrndpq_f<mode>" | |
390 | [ | |
391 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
392 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
393 | VRNDPQ_F)) | |
394 | ] | |
395 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
396 | "vrintp.f%#<V_sz_elem> %q0, %q1" | |
397 | [(set_attr "type" "mve_move") | |
398 | ]) | |
399 | ||
400 | ;; | |
401 | ;; [vrndnq_f]) | |
402 | ;; | |
403 | (define_insn "mve_vrndnq_f<mode>" | |
404 | [ | |
405 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
406 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
407 | VRNDNQ_F)) | |
408 | ] | |
409 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
410 | "vrintn.f%#<V_sz_elem> %q0, %q1" | |
411 | [(set_attr "type" "mve_move") | |
412 | ]) | |
413 | ||
414 | ;; | |
415 | ;; [vrndmq_f]) | |
416 | ;; | |
417 | (define_insn "mve_vrndmq_f<mode>" | |
418 | [ | |
419 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
420 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
421 | VRNDMQ_F)) | |
422 | ] | |
423 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
424 | "vrintm.f%#<V_sz_elem> %q0, %q1" | |
425 | [(set_attr "type" "mve_move") | |
426 | ]) | |
427 | ||
428 | ;; | |
429 | ;; [vrndaq_f]) | |
430 | ;; | |
431 | (define_insn "mve_vrndaq_f<mode>" | |
432 | [ | |
433 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
434 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
435 | VRNDAQ_F)) | |
436 | ] | |
437 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
438 | "vrinta.f%#<V_sz_elem> %q0, %q1" | |
439 | [(set_attr "type" "mve_move") | |
440 | ]) | |
441 | ||
442 | ;; | |
443 | ;; [vrev64q_f]) | |
444 | ;; | |
445 | (define_insn "mve_vrev64q_f<mode>" | |
446 | [ | |
447 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
448 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
449 | VREV64Q_F)) | |
450 | ] | |
451 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
452 | "vrev64.%#<V_sz_elem> %q0, %q1" | |
453 | [(set_attr "type" "mve_move") | |
454 | ]) | |
455 | ||
456 | ;; | |
457 | ;; [vnegq_f]) | |
458 | ;; | |
459 | (define_insn "mve_vnegq_f<mode>" | |
460 | [ | |
461 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
462 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
463 | VNEGQ_F)) | |
464 | ] | |
465 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
466 | "vneg.f%#<V_sz_elem> %q0, %q1" | |
467 | [(set_attr "type" "mve_move") | |
468 | ]) | |
469 | ||
470 | ;; | |
471 | ;; [vdupq_n_f]) | |
472 | ;; | |
473 | (define_insn "mve_vdupq_n_f<mode>" | |
474 | [ | |
475 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
476 | (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
477 | VDUPQ_N_F)) | |
478 | ] | |
479 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
480 | "vdup.%#<V_sz_elem> %q0, %1" | |
481 | [(set_attr "type" "mve_move") | |
482 | ]) | |
483 | ||
484 | ;; | |
485 | ;; [vabsq_f]) | |
486 | ;; | |
487 | (define_insn "mve_vabsq_f<mode>" | |
488 | [ | |
489 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
490 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] | |
491 | VABSQ_F)) | |
492 | ] | |
493 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
494 | "vabs.f%#<V_sz_elem> %q0, %q1" | |
495 | [(set_attr "type" "mve_move") | |
496 | ]) | |
497 | ||
498 | ;; | |
499 | ;; [vrev32q_f]) | |
500 | ;; | |
501 | (define_insn "mve_vrev32q_fv8hf" | |
502 | [ | |
503 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
504 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
505 | VREV32Q_F)) | |
506 | ] | |
507 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
508 | "vrev32.16 %q0, %q1" | |
509 | [(set_attr "type" "mve_move") | |
510 | ]) | |
511 | ;; | |
512 | ;; [vcvttq_f32_f16]) | |
513 | ;; | |
514 | (define_insn "mve_vcvttq_f32_f16v4sf" | |
515 | [ | |
516 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
517 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
518 | VCVTTQ_F32_F16)) | |
519 | ] | |
520 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
521 | "vcvtt.f32.f16 %q0, %q1" | |
522 | [(set_attr "type" "mve_move") | |
523 | ]) | |
524 | ||
525 | ;; | |
526 | ;; [vcvtbq_f32_f16]) | |
527 | ;; | |
528 | (define_insn "mve_vcvtbq_f32_f16v4sf" | |
529 | [ | |
530 | (set (match_operand:V4SF 0 "s_register_operand" "=w") | |
531 | (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] | |
532 | VCVTBQ_F32_F16)) | |
533 | ] | |
534 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
535 | "vcvtb.f32.f16 %q0, %q1" | |
536 | [(set_attr "type" "mve_move") | |
537 | ]) | |
538 | ||
539 | ;; | |
540 | ;; [vcvtq_to_f_s, vcvtq_to_f_u]) | |
541 | ;; | |
542 | (define_insn "mve_vcvtq_to_f_<supf><mode>" | |
543 | [ | |
544 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
545 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
546 | VCVTQ_TO_F)) | |
547 | ] | |
548 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
549 | "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1" | |
550 | [(set_attr "type" "mve_move") | |
551 | ]) | |
552 | ||
553 | ;; | |
554 | ;; [vrev64q_u, vrev64q_s]) | |
555 | ;; | |
556 | (define_insn "mve_vrev64q_<supf><mode>" | |
557 | [ | |
558 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
559 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
560 | VREV64Q)) | |
561 | ] | |
562 | "TARGET_HAVE_MVE" | |
563 | "vrev64.%#<V_sz_elem> %q0, %q1" | |
564 | [(set_attr "type" "mve_move") | |
565 | ]) | |
566 | ||
567 | ;; | |
568 | ;; [vcvtq_from_f_s, vcvtq_from_f_u]) | |
569 | ;; | |
570 | (define_insn "mve_vcvtq_from_f_<supf><mode>" | |
571 | [ | |
572 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
573 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
574 | VCVTQ_FROM_F)) | |
575 | ] | |
576 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
577 | "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
578 | [(set_attr "type" "mve_move") | |
579 | ]) | |
580 | ;; [vqnegq_s]) | |
581 | ;; | |
582 | (define_insn "mve_vqnegq_s<mode>" | |
583 | [ | |
584 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
585 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
586 | VQNEGQ_S)) | |
587 | ] | |
588 | "TARGET_HAVE_MVE" | |
589 | "vqneg.s%#<V_sz_elem> %q0, %q1" | |
590 | [(set_attr "type" "mve_move") | |
591 | ]) | |
592 | ||
593 | ;; | |
594 | ;; [vqabsq_s]) | |
595 | ;; | |
596 | (define_insn "mve_vqabsq_s<mode>" | |
597 | [ | |
598 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
599 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
600 | VQABSQ_S)) | |
601 | ] | |
602 | "TARGET_HAVE_MVE" | |
603 | "vqabs.s%#<V_sz_elem> %q0, %q1" | |
604 | [(set_attr "type" "mve_move") | |
605 | ]) | |
606 | ||
607 | ;; | |
608 | ;; [vnegq_s]) | |
609 | ;; | |
610 | (define_insn "mve_vnegq_s<mode>" | |
611 | [ | |
612 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
613 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
614 | VNEGQ_S)) | |
615 | ] | |
616 | "TARGET_HAVE_MVE" | |
617 | "vneg.s%#<V_sz_elem> %q0, %q1" | |
618 | [(set_attr "type" "mve_move") | |
619 | ]) | |
620 | ||
621 | ;; | |
622 | ;; [vmvnq_u, vmvnq_s]) | |
623 | ;; | |
624 | (define_insn "mve_vmvnq_<supf><mode>" | |
625 | [ | |
626 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
627 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
628 | VMVNQ)) | |
629 | ] | |
630 | "TARGET_HAVE_MVE" | |
631 | "vmvn %q0, %q1" | |
632 | [(set_attr "type" "mve_move") | |
633 | ]) | |
634 | ||
635 | ;; | |
636 | ;; [vdupq_n_u, vdupq_n_s]) | |
637 | ;; | |
638 | (define_insn "mve_vdupq_n_<supf><mode>" | |
639 | [ | |
640 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
641 | (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")] | |
642 | VDUPQ_N)) | |
643 | ] | |
644 | "TARGET_HAVE_MVE" | |
645 | "vdup.%#<V_sz_elem> %q0, %1" | |
646 | [(set_attr "type" "mve_move") | |
647 | ]) | |
648 | ||
649 | ;; | |
650 | ;; [vclzq_u, vclzq_s]) | |
651 | ;; | |
652 | (define_insn "mve_vclzq_<supf><mode>" | |
653 | [ | |
654 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
655 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
656 | VCLZQ)) | |
657 | ] | |
658 | "TARGET_HAVE_MVE" | |
659 | "vclz.i%#<V_sz_elem> %q0, %q1" | |
660 | [(set_attr "type" "mve_move") | |
661 | ]) | |
662 | ||
663 | ;; | |
664 | ;; [vclsq_s]) | |
665 | ;; | |
666 | (define_insn "mve_vclsq_s<mode>" | |
667 | [ | |
668 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
669 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
670 | VCLSQ_S)) | |
671 | ] | |
672 | "TARGET_HAVE_MVE" | |
673 | "vcls.s%#<V_sz_elem> %q0, %q1" | |
674 | [(set_attr "type" "mve_move") | |
675 | ]) | |
676 | ||
677 | ;; | |
678 | ;; [vaddvq_s, vaddvq_u]) | |
679 | ;; | |
680 | (define_insn "mve_vaddvq_<supf><mode>" | |
681 | [ | |
682 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
683 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
684 | VADDVQ)) | |
685 | ] | |
686 | "TARGET_HAVE_MVE" | |
687 | "vaddv.<supf>%#<V_sz_elem>\t%0, %q1" | |
688 | [(set_attr "type" "mve_move") | |
689 | ]) | |
690 | ||
691 | ;; | |
692 | ;; [vabsq_s]) | |
693 | ;; | |
694 | (define_insn "mve_vabsq_s<mode>" | |
695 | [ | |
696 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
697 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] | |
698 | VABSQ_S)) | |
699 | ] | |
700 | "TARGET_HAVE_MVE" | |
701 | "vabs.s%#<V_sz_elem>\t%q0, %q1" | |
702 | [(set_attr "type" "mve_move") | |
703 | ]) | |
704 | ||
705 | ;; | |
706 | ;; [vrev32q_u, vrev32q_s]) | |
707 | ;; | |
708 | (define_insn "mve_vrev32q_<supf><mode>" | |
709 | [ | |
710 | (set (match_operand:MVE_3 0 "s_register_operand" "=w") | |
711 | (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
712 | VREV32Q)) | |
713 | ] | |
714 | "TARGET_HAVE_MVE" | |
715 | "vrev32.%#<V_sz_elem>\t%q0, %q1" | |
716 | [(set_attr "type" "mve_move") | |
717 | ]) | |
718 | ||
719 | ;; | |
720 | ;; [vmovltq_u, vmovltq_s]) | |
721 | ;; | |
722 | (define_insn "mve_vmovltq_<supf><mode>" | |
723 | [ | |
724 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
725 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
726 | VMOVLTQ)) | |
727 | ] | |
728 | "TARGET_HAVE_MVE" | |
729 | "vmovlt.<supf>%#<V_sz_elem> %q0, %q1" | |
730 | [(set_attr "type" "mve_move") | |
731 | ]) | |
732 | ||
733 | ;; | |
734 | ;; [vmovlbq_s, vmovlbq_u]) | |
735 | ;; | |
736 | (define_insn "mve_vmovlbq_<supf><mode>" | |
737 | [ | |
738 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
739 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] | |
740 | VMOVLBQ)) | |
741 | ] | |
742 | "TARGET_HAVE_MVE" | |
743 | "vmovlb.<supf>%#<V_sz_elem> %q0, %q1" | |
744 | [(set_attr "type" "mve_move") | |
745 | ]) | |
746 | ||
747 | ;; | |
748 | ;; [vcvtpq_s, vcvtpq_u]) | |
749 | ;; | |
750 | (define_insn "mve_vcvtpq_<supf><mode>" | |
751 | [ | |
752 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
753 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
754 | VCVTPQ)) | |
755 | ] | |
756 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
757 | "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
758 | [(set_attr "type" "mve_move") | |
759 | ]) | |
760 | ||
761 | ;; | |
762 | ;; [vcvtnq_s, vcvtnq_u]) | |
763 | ;; | |
764 | (define_insn "mve_vcvtnq_<supf><mode>" | |
765 | [ | |
766 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
767 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
768 | VCVTNQ)) | |
769 | ] | |
770 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
771 | "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
772 | [(set_attr "type" "mve_move") | |
773 | ]) | |
774 | ||
775 | ;; | |
776 | ;; [vcvtmq_s, vcvtmq_u]) | |
777 | ;; | |
778 | (define_insn "mve_vcvtmq_<supf><mode>" | |
779 | [ | |
780 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
781 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
782 | VCVTMQ)) | |
783 | ] | |
784 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
785 | "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
786 | [(set_attr "type" "mve_move") | |
787 | ]) | |
788 | ||
789 | ;; | |
790 | ;; [vcvtaq_u, vcvtaq_s]) | |
791 | ;; | |
792 | (define_insn "mve_vcvtaq_<supf><mode>" | |
793 | [ | |
794 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
795 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] | |
796 | VCVTAQ)) | |
797 | ] | |
798 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
799 | "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1" | |
800 | [(set_attr "type" "mve_move") | |
801 | ]) | |
802 | ||
803 | ;; | |
804 | ;; [vmvnq_n_u, vmvnq_n_s]) | |
805 | ;; | |
806 | (define_insn "mve_vmvnq_n_<supf><mode>" | |
807 | [ | |
808 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
809 | (unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")] | |
810 | VMVNQ_N)) | |
811 | ] | |
812 | "TARGET_HAVE_MVE" | |
813 | "vmvn.i%#<V_sz_elem> %q0, %1" | |
814 | [(set_attr "type" "mve_move") | |
815 | ]) | |
816 | ||
817 | ;; | |
818 | ;; [vrev16q_u, vrev16q_s]) | |
819 | ;; | |
820 | (define_insn "mve_vrev16q_<supf>v16qi" | |
821 | [ | |
822 | (set (match_operand:V16QI 0 "s_register_operand" "=w") | |
823 | (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] | |
824 | VREV16Q)) | |
825 | ] | |
826 | "TARGET_HAVE_MVE" | |
827 | "vrev16.8 %q0, %q1" | |
828 | [(set_attr "type" "mve_move") | |
829 | ]) | |
830 | ||
831 | ;; | |
832 | ;; [vaddlvq_s vaddlvq_u]) | |
833 | ;; | |
834 | (define_insn "mve_vaddlvq_<supf>v4si" | |
835 | [ | |
836 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
837 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] | |
838 | VADDLVQ)) | |
839 | ] | |
840 | "TARGET_HAVE_MVE" | |
841 | "vaddlv.<supf>32 %Q0, %R0, %q1" | |
842 | [(set_attr "type" "mve_move") | |
843 | ]) | |
844 | ||
845 | ;; | |
846 | ;; [vctp8q vctp16q vctp32q vctp64q]) | |
847 | ;; | |
848 | (define_insn "mve_vctp<mode1>qhi" | |
849 | [ | |
850 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
851 | (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")] | |
852 | VCTPQ)) | |
853 | ] | |
854 | "TARGET_HAVE_MVE" | |
855 | "vctp.<mode1> %1" | |
856 | [(set_attr "type" "mve_move") | |
857 | ]) | |
858 | ||
859 | ;; | |
860 | ;; [vpnot]) | |
861 | ;; | |
862 | (define_insn "mve_vpnothi" | |
863 | [ | |
864 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
865 | (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")] | |
866 | VPNOT)) | |
867 | ] | |
868 | "TARGET_HAVE_MVE" | |
869 | "vpnot" | |
870 | [(set_attr "type" "mve_move") | |
871 | ]) | |
872 | ||
873 | ;; | |
874 | ;; [vsubq_n_f]) | |
875 | ;; | |
876 | (define_insn "mve_vsubq_n_f<mode>" | |
877 | [ | |
878 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
879 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
880 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
881 | VSUBQ_N_F)) | |
882 | ] | |
883 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
884 | "vsub.f<V_sz_elem> %q0, %q1, %2" | |
885 | [(set_attr "type" "mve_move") | |
886 | ]) | |
887 | ||
888 | ;; | |
889 | ;; [vbrsrq_n_f]) | |
890 | ;; | |
891 | (define_insn "mve_vbrsrq_n_f<mode>" | |
892 | [ | |
893 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
894 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
895 | (match_operand:SI 2 "s_register_operand" "r")] | |
896 | VBRSRQ_N_F)) | |
897 | ] | |
898 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
899 | "vbrsr.<V_sz_elem> %q0, %q1, %2" | |
900 | [(set_attr "type" "mve_move") | |
901 | ]) | |
902 | ||
903 | ;; | |
904 | ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) | |
905 | ;; | |
906 | (define_insn "mve_vcvtq_n_to_f_<supf><mode>" | |
907 | [ | |
908 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
909 | (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
910 | (match_operand:SI 2 "mve_imm_16" "Rd")] | |
911 | VCVTQ_N_TO_F)) | |
912 | ] | |
913 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
914 | "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2" | |
915 | [(set_attr "type" "mve_move") | |
916 | ]) | |
917 | ||
918 | ;; [vcreateq_f]) | |
919 | ;; | |
920 | (define_insn "mve_vcreateq_f<mode>" | |
921 | [ | |
922 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
923 | (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") | |
924 | (match_operand:DI 2 "s_register_operand" "r")] | |
925 | VCREATEQ_F)) | |
926 | ] | |
927 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
928 | "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" | |
929 | [(set_attr "type" "mve_move") | |
930 | (set_attr "length""8")]) | |
931 | ||
932 | ;; | |
933 | ;; [vcreateq_u, vcreateq_s]) | |
934 | ;; | |
935 | (define_insn "mve_vcreateq_<supf><mode>" | |
936 | [ | |
937 | (set (match_operand:MVE_1 0 "s_register_operand" "=w") | |
938 | (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") | |
939 | (match_operand:DI 2 "s_register_operand" "r")] | |
940 | VCREATEQ)) | |
941 | ] | |
942 | "TARGET_HAVE_MVE" | |
943 | "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" | |
944 | [(set_attr "type" "mve_move") | |
945 | (set_attr "length""8")]) | |
946 | ||
947 | ;; | |
948 | ;; [vshrq_n_s, vshrq_n_u]) | |
949 | ;; | |
950 | (define_insn "mve_vshrq_n_<supf><mode>" | |
951 | [ | |
952 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
953 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
954 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] | |
955 | VSHRQ_N)) | |
956 | ] | |
957 | "TARGET_HAVE_MVE" | |
958 | "vshr.<supf><V_sz_elem>\t%q0, %q1, %2" | |
959 | [(set_attr "type" "mve_move") | |
960 | ]) | |
961 | ||
962 | ;; | |
963 | ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) | |
964 | ;; | |
965 | (define_insn "mve_vcvtq_n_from_f_<supf><mode>" | |
966 | [ | |
967 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
968 | (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") | |
969 | (match_operand:SI 2 "mve_imm_16" "Rd")] | |
970 | VCVTQ_N_FROM_F)) | |
971 | ] | |
972 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
973 | "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2" | |
974 | [(set_attr "type" "mve_move") | |
975 | ]) | |
976 | ||
977 | ;; | |
978 | ;; [vaddlvq_p_s]) | |
979 | ;; | |
980 | (define_insn "mve_vaddlvq_p_<supf>v4si" | |
981 | [ | |
982 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
983 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
984 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
985 | VADDLVQ_P)) | |
986 | ] | |
987 | "TARGET_HAVE_MVE" | |
988 | "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1" | |
989 | [(set_attr "type" "mve_move") | |
990 | (set_attr "length""8")]) | |
991 | ||
992 | ;; | |
993 | ;; [vcmpneq_u, vcmpneq_s]) | |
994 | ;; | |
995 | (define_insn "mve_vcmpneq_<supf><mode>" | |
996 | [ | |
997 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
998 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
999 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1000 | VCMPNEQ)) | |
1001 | ] | |
1002 | "TARGET_HAVE_MVE" | |
1003 | "vcmp.i%#<V_sz_elem> ne, %q1, %q2" | |
1004 | [(set_attr "type" "mve_move") | |
1005 | ]) | |
1006 | ||
1007 | ;; | |
1008 | ;; [vshlq_s, vshlq_u]) | |
1009 | ;; | |
1010 | (define_insn "mve_vshlq_<supf><mode>" | |
1011 | [ | |
1012 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1013 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1014 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1015 | VSHLQ)) | |
1016 | ] | |
1017 | "TARGET_HAVE_MVE" | |
1018 | "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1019 | [(set_attr "type" "mve_move") | |
1020 | ]) | |
1021 | ||
1022 | ;; | |
1023 | ;; [vabdq_s, vabdq_u]) | |
1024 | ;; | |
1025 | (define_insn "mve_vabdq_<supf><mode>" | |
1026 | [ | |
1027 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1028 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1029 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1030 | VABDQ)) | |
1031 | ] | |
1032 | "TARGET_HAVE_MVE" | |
1033 | "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2" | |
1034 | [(set_attr "type" "mve_move") | |
1035 | ]) | |
1036 | ||
1037 | ;; | |
1038 | ;; [vaddq_n_s, vaddq_n_u]) | |
1039 | ;; | |
1040 | (define_insn "mve_vaddq_n_<supf><mode>" | |
1041 | [ | |
1042 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1043 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1044 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1045 | VADDQ_N)) | |
1046 | ] | |
1047 | "TARGET_HAVE_MVE" | |
1048 | "vadd.i%#<V_sz_elem> %q0, %q1, %2" | |
1049 | [(set_attr "type" "mve_move") | |
1050 | ]) | |
1051 | ||
1052 | ;; | |
1053 | ;; [vaddvaq_s, vaddvaq_u]) | |
1054 | ;; | |
1055 | (define_insn "mve_vaddvaq_<supf><mode>" | |
1056 | [ | |
1057 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1058 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
1059 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1060 | VADDVAQ)) | |
1061 | ] | |
1062 | "TARGET_HAVE_MVE" | |
1063 | "vaddva.<supf>%#<V_sz_elem> %0, %q2" | |
1064 | [(set_attr "type" "mve_move") | |
1065 | ]) | |
1066 | ||
1067 | ;; | |
1068 | ;; [vaddvq_p_u, vaddvq_p_s]) | |
1069 | ;; | |
1070 | (define_insn "mve_vaddvq_p_<supf><mode>" | |
1071 | [ | |
1072 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1073 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1074 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
1075 | VADDVQ_P)) | |
1076 | ] | |
1077 | "TARGET_HAVE_MVE" | |
1078 | "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1" | |
1079 | [(set_attr "type" "mve_move") | |
1080 | (set_attr "length""8")]) | |
1081 | ||
1082 | ;; | |
1083 | ;; [vandq_u, vandq_s]) | |
1084 | ;; | |
1085 | (define_insn "mve_vandq_<supf><mode>" | |
1086 | [ | |
1087 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1088 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1089 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1090 | VANDQ)) | |
1091 | ] | |
1092 | "TARGET_HAVE_MVE" | |
1093 | "vand %q0, %q1, %q2" | |
1094 | [(set_attr "type" "mve_move") | |
1095 | ]) | |
1096 | ||
1097 | ;; | |
1098 | ;; [vbicq_s, vbicq_u]) | |
1099 | ;; | |
1100 | (define_insn "mve_vbicq_<supf><mode>" | |
1101 | [ | |
1102 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1103 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1104 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1105 | VBICQ)) | |
1106 | ] | |
1107 | "TARGET_HAVE_MVE" | |
1108 | "vbic %q0, %q1, %q2" | |
1109 | [(set_attr "type" "mve_move") | |
1110 | ]) | |
1111 | ||
1112 | ;; | |
1113 | ;; [vbrsrq_n_u, vbrsrq_n_s]) | |
1114 | ;; | |
1115 | (define_insn "mve_vbrsrq_n_<supf><mode>" | |
1116 | [ | |
1117 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1118 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1119 | (match_operand:SI 2 "s_register_operand" "r")] | |
1120 | VBRSRQ_N)) | |
1121 | ] | |
1122 | "TARGET_HAVE_MVE" | |
1123 | "vbrsr.%#<V_sz_elem> %q0, %q1, %2" | |
1124 | [(set_attr "type" "mve_move") | |
1125 | ]) | |
1126 | ||
1127 | ;; | |
1128 | ;; [vcaddq_rot270_s, vcaddq_rot270_u]) | |
1129 | ;; | |
1130 | (define_insn "mve_vcaddq_rot270_<supf><mode>" | |
1131 | [ | |
1132 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1133 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1134 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1135 | VCADDQ_ROT270)) | |
1136 | ] | |
1137 | "TARGET_HAVE_MVE" | |
1138 | "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270" | |
1139 | [(set_attr "type" "mve_move") | |
1140 | ]) | |
1141 | ||
1142 | ;; | |
1143 | ;; [vcaddq_rot90_u, vcaddq_rot90_s]) | |
1144 | ;; | |
1145 | (define_insn "mve_vcaddq_rot90_<supf><mode>" | |
1146 | [ | |
1147 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1148 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1149 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1150 | VCADDQ_ROT90)) | |
1151 | ] | |
1152 | "TARGET_HAVE_MVE" | |
1153 | "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90" | |
1154 | [(set_attr "type" "mve_move") | |
1155 | ]) | |
1156 | ||
1157 | ;; | |
1158 | ;; [vcmpcsq_n_u]) | |
1159 | ;; | |
1160 | (define_insn "mve_vcmpcsq_n_u<mode>" | |
1161 | [ | |
1162 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1163 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1164 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1165 | VCMPCSQ_N_U)) | |
1166 | ] | |
1167 | "TARGET_HAVE_MVE" | |
1168 | "vcmp.u%#<V_sz_elem> cs, %q1, %2" | |
1169 | [(set_attr "type" "mve_move") | |
1170 | ]) | |
1171 | ||
1172 | ;; | |
1173 | ;; [vcmpcsq_u]) | |
1174 | ;; | |
1175 | (define_insn "mve_vcmpcsq_u<mode>" | |
1176 | [ | |
1177 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1178 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1179 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1180 | VCMPCSQ_U)) | |
1181 | ] | |
1182 | "TARGET_HAVE_MVE" | |
1183 | "vcmp.u%#<V_sz_elem> cs, %q1, %q2" | |
1184 | [(set_attr "type" "mve_move") | |
1185 | ]) | |
1186 | ||
1187 | ;; | |
1188 | ;; [vcmpeqq_n_s, vcmpeqq_n_u]) | |
1189 | ;; | |
1190 | (define_insn "mve_vcmpeqq_n_<supf><mode>" | |
1191 | [ | |
1192 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1193 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1194 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1195 | VCMPEQQ_N)) | |
1196 | ] | |
1197 | "TARGET_HAVE_MVE" | |
1198 | "vcmp.i%#<V_sz_elem> eq, %q1, %2" | |
1199 | [(set_attr "type" "mve_move") | |
1200 | ]) | |
1201 | ||
1202 | ;; | |
1203 | ;; [vcmpeqq_u, vcmpeqq_s]) | |
1204 | ;; | |
1205 | (define_insn "mve_vcmpeqq_<supf><mode>" | |
1206 | [ | |
1207 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1208 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1209 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1210 | VCMPEQQ)) | |
1211 | ] | |
1212 | "TARGET_HAVE_MVE" | |
1213 | "vcmp.i%#<V_sz_elem> eq, %q1, %q2" | |
1214 | [(set_attr "type" "mve_move") | |
1215 | ]) | |
1216 | ||
1217 | ;; | |
1218 | ;; [vcmpgeq_n_s]) | |
1219 | ;; | |
1220 | (define_insn "mve_vcmpgeq_n_s<mode>" | |
1221 | [ | |
1222 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1223 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1224 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1225 | VCMPGEQ_N_S)) | |
1226 | ] | |
1227 | "TARGET_HAVE_MVE" | |
1228 | "vcmp.s%#<V_sz_elem> ge, %q1, %2" | |
1229 | [(set_attr "type" "mve_move") | |
1230 | ]) | |
1231 | ||
1232 | ;; | |
1233 | ;; [vcmpgeq_s]) | |
1234 | ;; | |
1235 | (define_insn "mve_vcmpgeq_s<mode>" | |
1236 | [ | |
1237 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1238 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1239 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1240 | VCMPGEQ_S)) | |
1241 | ] | |
1242 | "TARGET_HAVE_MVE" | |
1243 | "vcmp.s%#<V_sz_elem> ge, %q1, %q2" | |
1244 | [(set_attr "type" "mve_move") | |
1245 | ]) | |
1246 | ||
1247 | ;; | |
1248 | ;; [vcmpgtq_n_s]) | |
1249 | ;; | |
1250 | (define_insn "mve_vcmpgtq_n_s<mode>" | |
1251 | [ | |
1252 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1253 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1254 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1255 | VCMPGTQ_N_S)) | |
1256 | ] | |
1257 | "TARGET_HAVE_MVE" | |
1258 | "vcmp.s%#<V_sz_elem> gt, %q1, %2" | |
1259 | [(set_attr "type" "mve_move") | |
1260 | ]) | |
1261 | ||
1262 | ;; | |
1263 | ;; [vcmpgtq_s]) | |
1264 | ;; | |
1265 | (define_insn "mve_vcmpgtq_s<mode>" | |
1266 | [ | |
1267 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1268 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1269 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1270 | VCMPGTQ_S)) | |
1271 | ] | |
1272 | "TARGET_HAVE_MVE" | |
1273 | "vcmp.s%#<V_sz_elem> gt, %q1, %q2" | |
1274 | [(set_attr "type" "mve_move") | |
1275 | ]) | |
1276 | ||
1277 | ;; | |
1278 | ;; [vcmphiq_n_u]) | |
1279 | ;; | |
1280 | (define_insn "mve_vcmphiq_n_u<mode>" | |
1281 | [ | |
1282 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1283 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1284 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1285 | VCMPHIQ_N_U)) | |
1286 | ] | |
1287 | "TARGET_HAVE_MVE" | |
1288 | "vcmp.u%#<V_sz_elem> hi, %q1, %2" | |
1289 | [(set_attr "type" "mve_move") | |
1290 | ]) | |
1291 | ||
1292 | ;; | |
1293 | ;; [vcmphiq_u]) | |
1294 | ;; | |
1295 | (define_insn "mve_vcmphiq_u<mode>" | |
1296 | [ | |
1297 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1298 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1299 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1300 | VCMPHIQ_U)) | |
1301 | ] | |
1302 | "TARGET_HAVE_MVE" | |
1303 | "vcmp.u%#<V_sz_elem> hi, %q1, %q2" | |
1304 | [(set_attr "type" "mve_move") | |
1305 | ]) | |
1306 | ||
1307 | ;; | |
1308 | ;; [vcmpleq_n_s]) | |
1309 | ;; | |
1310 | (define_insn "mve_vcmpleq_n_s<mode>" | |
1311 | [ | |
1312 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1313 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1314 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1315 | VCMPLEQ_N_S)) | |
1316 | ] | |
1317 | "TARGET_HAVE_MVE" | |
1318 | "vcmp.s%#<V_sz_elem> le, %q1, %2" | |
1319 | [(set_attr "type" "mve_move") | |
1320 | ]) | |
1321 | ||
1322 | ;; | |
1323 | ;; [vcmpleq_s]) | |
1324 | ;; | |
1325 | (define_insn "mve_vcmpleq_s<mode>" | |
1326 | [ | |
1327 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1328 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1329 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1330 | VCMPLEQ_S)) | |
1331 | ] | |
1332 | "TARGET_HAVE_MVE" | |
1333 | "vcmp.s%#<V_sz_elem> le, %q1, %q2" | |
1334 | [(set_attr "type" "mve_move") | |
1335 | ]) | |
1336 | ||
1337 | ;; | |
1338 | ;; [vcmpltq_n_s]) | |
1339 | ;; | |
1340 | (define_insn "mve_vcmpltq_n_s<mode>" | |
1341 | [ | |
1342 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1343 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1344 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1345 | VCMPLTQ_N_S)) | |
1346 | ] | |
1347 | "TARGET_HAVE_MVE" | |
1348 | "vcmp.s%#<V_sz_elem> lt, %q1, %2" | |
1349 | [(set_attr "type" "mve_move") | |
1350 | ]) | |
1351 | ||
1352 | ;; | |
1353 | ;; [vcmpltq_s]) | |
1354 | ;; | |
1355 | (define_insn "mve_vcmpltq_s<mode>" | |
1356 | [ | |
1357 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1358 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1359 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1360 | VCMPLTQ_S)) | |
1361 | ] | |
1362 | "TARGET_HAVE_MVE" | |
1363 | "vcmp.s%#<V_sz_elem> lt, %q1, %q2" | |
1364 | [(set_attr "type" "mve_move") | |
1365 | ]) | |
1366 | ||
1367 | ;; | |
1368 | ;; [vcmpneq_n_u, vcmpneq_n_s]) | |
1369 | ;; | |
1370 | (define_insn "mve_vcmpneq_n_<supf><mode>" | |
1371 | [ | |
1372 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
1373 | (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1374 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1375 | VCMPNEQ_N)) | |
1376 | ] | |
1377 | "TARGET_HAVE_MVE" | |
1378 | "vcmp.i%#<V_sz_elem> ne, %q1, %2" | |
1379 | [(set_attr "type" "mve_move") | |
1380 | ]) | |
1381 | ||
1382 | ;; | |
1383 | ;; [veorq_u, veorq_s]) | |
1384 | ;; | |
1385 | (define_insn "mve_veorq_<supf><mode>" | |
1386 | [ | |
1387 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1388 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1389 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1390 | VEORQ)) | |
1391 | ] | |
1392 | "TARGET_HAVE_MVE" | |
1393 | "veor %q0, %q1, %q2" | |
1394 | [(set_attr "type" "mve_move") | |
1395 | ]) | |
1396 | ||
1397 | ;; | |
1398 | ;; [vhaddq_n_u, vhaddq_n_s]) | |
1399 | ;; | |
1400 | (define_insn "mve_vhaddq_n_<supf><mode>" | |
1401 | [ | |
1402 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1403 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1404 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1405 | VHADDQ_N)) | |
1406 | ] | |
1407 | "TARGET_HAVE_MVE" | |
1408 | "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1409 | [(set_attr "type" "mve_move") | |
1410 | ]) | |
1411 | ||
1412 | ;; | |
1413 | ;; [vhaddq_s, vhaddq_u]) | |
1414 | ;; | |
1415 | (define_insn "mve_vhaddq_<supf><mode>" | |
1416 | [ | |
1417 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1418 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1419 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1420 | VHADDQ)) | |
1421 | ] | |
1422 | "TARGET_HAVE_MVE" | |
1423 | "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1424 | [(set_attr "type" "mve_move") | |
1425 | ]) | |
1426 | ||
1427 | ;; | |
1428 | ;; [vhcaddq_rot270_s]) | |
1429 | ;; | |
1430 | (define_insn "mve_vhcaddq_rot270_s<mode>" | |
1431 | [ | |
1432 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1433 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1434 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1435 | VHCADDQ_ROT270_S)) | |
1436 | ] | |
1437 | "TARGET_HAVE_MVE" | |
1438 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270" | |
1439 | [(set_attr "type" "mve_move") | |
1440 | ]) | |
1441 | ||
1442 | ;; | |
1443 | ;; [vhcaddq_rot90_s]) | |
1444 | ;; | |
1445 | (define_insn "mve_vhcaddq_rot90_s<mode>" | |
1446 | [ | |
1447 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1448 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1449 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1450 | VHCADDQ_ROT90_S)) | |
1451 | ] | |
1452 | "TARGET_HAVE_MVE" | |
1453 | "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90" | |
1454 | [(set_attr "type" "mve_move") | |
1455 | ]) | |
1456 | ||
1457 | ;; | |
1458 | ;; [vhsubq_n_u, vhsubq_n_s]) | |
1459 | ;; | |
1460 | (define_insn "mve_vhsubq_n_<supf><mode>" | |
1461 | [ | |
1462 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1463 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1464 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1465 | VHSUBQ_N)) | |
1466 | ] | |
1467 | "TARGET_HAVE_MVE" | |
1468 | "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1469 | [(set_attr "type" "mve_move") | |
1470 | ]) | |
1471 | ||
1472 | ;; | |
1473 | ;; [vhsubq_s, vhsubq_u]) | |
1474 | ;; | |
1475 | (define_insn "mve_vhsubq_<supf><mode>" | |
1476 | [ | |
1477 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1478 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1479 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1480 | VHSUBQ)) | |
1481 | ] | |
1482 | "TARGET_HAVE_MVE" | |
1483 | "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1484 | [(set_attr "type" "mve_move") | |
1485 | ]) | |
1486 | ||
1487 | ;; | |
1488 | ;; [vmaxaq_s]) | |
1489 | ;; | |
1490 | (define_insn "mve_vmaxaq_s<mode>" | |
1491 | [ | |
1492 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1493 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1494 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1495 | VMAXAQ_S)) | |
1496 | ] | |
1497 | "TARGET_HAVE_MVE" | |
1498 | "vmaxa.s%#<V_sz_elem> %q0, %q2" | |
1499 | [(set_attr "type" "mve_move") | |
1500 | ]) | |
1501 | ||
1502 | ;; | |
1503 | ;; [vmaxavq_s]) | |
1504 | ;; | |
1505 | (define_insn "mve_vmaxavq_s<mode>" | |
1506 | [ | |
1507 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1508 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1509 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1510 | VMAXAVQ_S)) | |
1511 | ] | |
1512 | "TARGET_HAVE_MVE" | |
1513 | "vmaxav.s%#<V_sz_elem>\t%0, %q2" | |
1514 | [(set_attr "type" "mve_move") | |
1515 | ]) | |
1516 | ||
1517 | ;; | |
1518 | ;; [vmaxq_u, vmaxq_s]) | |
1519 | ;; | |
1520 | (define_insn "mve_vmaxq_<supf><mode>" | |
1521 | [ | |
1522 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1523 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1524 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1525 | VMAXQ)) | |
1526 | ] | |
1527 | "TARGET_HAVE_MVE" | |
1528 | "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1529 | [(set_attr "type" "mve_move") | |
1530 | ]) | |
1531 | ||
1532 | ;; | |
1533 | ;; [vmaxvq_u, vmaxvq_s]) | |
1534 | ;; | |
1535 | (define_insn "mve_vmaxvq_<supf><mode>" | |
1536 | [ | |
1537 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1538 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1539 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1540 | VMAXVQ)) | |
1541 | ] | |
1542 | "TARGET_HAVE_MVE" | |
1543 | "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2" | |
1544 | [(set_attr "type" "mve_move") | |
1545 | ]) | |
1546 | ||
1547 | ;; | |
1548 | ;; [vminaq_s]) | |
1549 | ;; | |
1550 | (define_insn "mve_vminaq_s<mode>" | |
1551 | [ | |
1552 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1553 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1554 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1555 | VMINAQ_S)) | |
1556 | ] | |
1557 | "TARGET_HAVE_MVE" | |
1558 | "vmina.s%#<V_sz_elem>\t%q0, %q2" | |
1559 | [(set_attr "type" "mve_move") | |
1560 | ]) | |
1561 | ||
1562 | ;; | |
1563 | ;; [vminavq_s]) | |
1564 | ;; | |
1565 | (define_insn "mve_vminavq_s<mode>" | |
1566 | [ | |
1567 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1568 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1569 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1570 | VMINAVQ_S)) | |
1571 | ] | |
1572 | "TARGET_HAVE_MVE" | |
1573 | "vminav.s%#<V_sz_elem>\t%0, %q2" | |
1574 | [(set_attr "type" "mve_move") | |
1575 | ]) | |
1576 | ||
1577 | ;; | |
1578 | ;; [vminq_s, vminq_u]) | |
1579 | ;; | |
1580 | (define_insn "mve_vminq_<supf><mode>" | |
1581 | [ | |
1582 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1583 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1584 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1585 | VMINQ)) | |
1586 | ] | |
1587 | "TARGET_HAVE_MVE" | |
1588 | "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1589 | [(set_attr "type" "mve_move") | |
1590 | ]) | |
1591 | ||
1592 | ;; | |
1593 | ;; [vminvq_u, vminvq_s]) | |
1594 | ;; | |
1595 | (define_insn "mve_vminvq_<supf><mode>" | |
1596 | [ | |
1597 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
1598 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
1599 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1600 | VMINVQ)) | |
1601 | ] | |
1602 | "TARGET_HAVE_MVE" | |
1603 | "vminv.<supf>%#<V_sz_elem>\t%0, %q2" | |
1604 | [(set_attr "type" "mve_move") | |
1605 | ]) | |
1606 | ||
1607 | ;; | |
1608 | ;; [vmladavq_u, vmladavq_s]) | |
1609 | ;; | |
1610 | (define_insn "mve_vmladavq_<supf><mode>" | |
1611 | [ | |
1612 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1613 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1614 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1615 | VMLADAVQ)) | |
1616 | ] | |
1617 | "TARGET_HAVE_MVE" | |
1618 | "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2" | |
1619 | [(set_attr "type" "mve_move") | |
1620 | ]) | |
1621 | ||
1622 | ;; | |
1623 | ;; [vmladavxq_s]) | |
1624 | ;; | |
1625 | (define_insn "mve_vmladavxq_s<mode>" | |
1626 | [ | |
1627 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1628 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1629 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1630 | VMLADAVXQ_S)) | |
1631 | ] | |
1632 | "TARGET_HAVE_MVE" | |
1633 | "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1634 | [(set_attr "type" "mve_move") | |
1635 | ]) | |
1636 | ||
1637 | ;; | |
1638 | ;; [vmlsdavq_s]) | |
1639 | ;; | |
1640 | (define_insn "mve_vmlsdavq_s<mode>" | |
1641 | [ | |
1642 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1643 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1644 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1645 | VMLSDAVQ_S)) | |
1646 | ] | |
1647 | "TARGET_HAVE_MVE" | |
1648 | "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1649 | [(set_attr "type" "mve_move") | |
1650 | ]) | |
1651 | ||
1652 | ;; | |
1653 | ;; [vmlsdavxq_s]) | |
1654 | ;; | |
1655 | (define_insn "mve_vmlsdavxq_s<mode>" | |
1656 | [ | |
1657 | (set (match_operand:SI 0 "s_register_operand" "=e") | |
1658 | (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1659 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1660 | VMLSDAVXQ_S)) | |
1661 | ] | |
1662 | "TARGET_HAVE_MVE" | |
1663 | "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2" | |
1664 | [(set_attr "type" "mve_move") | |
1665 | ]) | |
1666 | ||
1667 | ;; | |
1668 | ;; [vmulhq_s, vmulhq_u]) | |
1669 | ;; | |
1670 | (define_insn "mve_vmulhq_<supf><mode>" | |
1671 | [ | |
1672 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1673 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1674 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1675 | VMULHQ)) | |
1676 | ] | |
1677 | "TARGET_HAVE_MVE" | |
1678 | "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1679 | [(set_attr "type" "mve_move") | |
1680 | ]) | |
1681 | ||
1682 | ;; | |
1683 | ;; [vmullbq_int_u, vmullbq_int_s]) | |
1684 | ;; | |
1685 | (define_insn "mve_vmullbq_int_<supf><mode>" | |
1686 | [ | |
1687 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
1688 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1689 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1690 | VMULLBQ_INT)) | |
1691 | ] | |
1692 | "TARGET_HAVE_MVE" | |
1693 | "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1694 | [(set_attr "type" "mve_move") | |
1695 | ]) | |
1696 | ||
1697 | ;; | |
1698 | ;; [vmulltq_int_u, vmulltq_int_s]) | |
1699 | ;; | |
1700 | (define_insn "mve_vmulltq_int_<supf><mode>" | |
1701 | [ | |
1702 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
1703 | (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1704 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1705 | VMULLTQ_INT)) | |
1706 | ] | |
1707 | "TARGET_HAVE_MVE" | |
1708 | "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1709 | [(set_attr "type" "mve_move") | |
1710 | ]) | |
1711 | ||
1712 | ;; | |
1713 | ;; [vmulq_n_u, vmulq_n_s]) | |
1714 | ;; | |
1715 | (define_insn "mve_vmulq_n_<supf><mode>" | |
1716 | [ | |
1717 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1718 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1719 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1720 | VMULQ_N)) | |
1721 | ] | |
1722 | "TARGET_HAVE_MVE" | |
1723 | "vmul.i%#<V_sz_elem>\t%q0, %q1, %2" | |
1724 | [(set_attr "type" "mve_move") | |
1725 | ]) | |
1726 | ||
1727 | ;; | |
1728 | ;; [vmulq_u, vmulq_s]) | |
1729 | ;; | |
1730 | (define_insn "mve_vmulq_<supf><mode>" | |
1731 | [ | |
1732 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1733 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1734 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1735 | VMULQ)) | |
1736 | ] | |
1737 | "TARGET_HAVE_MVE" | |
1738 | "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2" | |
1739 | [(set_attr "type" "mve_move") | |
1740 | ]) | |
1741 | ||
1742 | ;; | |
1743 | ;; [vornq_u, vornq_s]) | |
1744 | ;; | |
1745 | (define_insn "mve_vornq_<supf><mode>" | |
1746 | [ | |
1747 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1748 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1749 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1750 | VORNQ)) | |
1751 | ] | |
1752 | "TARGET_HAVE_MVE" | |
1753 | "vorn %q0, %q1, %q2" | |
1754 | [(set_attr "type" "mve_move") | |
1755 | ]) | |
1756 | ||
1757 | ;; | |
1758 | ;; [vorrq_s, vorrq_u]) | |
1759 | ;; | |
1760 | (define_insn "mve_vorrq_<supf><mode>" | |
1761 | [ | |
1762 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1763 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1764 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1765 | VORRQ)) | |
1766 | ] | |
1767 | "TARGET_HAVE_MVE" | |
1768 | "vorr %q0, %q1, %q2" | |
1769 | [(set_attr "type" "mve_move") | |
1770 | ]) | |
1771 | ||
1772 | ;; | |
1773 | ;; [vqaddq_n_s, vqaddq_n_u]) | |
1774 | ;; | |
1775 | (define_insn "mve_vqaddq_n_<supf><mode>" | |
1776 | [ | |
1777 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1778 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1779 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1780 | VQADDQ_N)) | |
1781 | ] | |
1782 | "TARGET_HAVE_MVE" | |
1783 | "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1784 | [(set_attr "type" "mve_move") | |
1785 | ]) | |
1786 | ||
1787 | ;; | |
1788 | ;; [vqaddq_u, vqaddq_s]) | |
1789 | ;; | |
1790 | (define_insn "mve_vqaddq_<supf><mode>" | |
1791 | [ | |
1792 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1793 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1794 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1795 | VQADDQ)) | |
1796 | ] | |
1797 | "TARGET_HAVE_MVE" | |
1798 | "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1799 | [(set_attr "type" "mve_move") | |
1800 | ]) | |
1801 | ||
1802 | ;; | |
1803 | ;; [vqdmulhq_n_s]) | |
1804 | ;; | |
1805 | (define_insn "mve_vqdmulhq_n_s<mode>" | |
1806 | [ | |
1807 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1808 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1809 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1810 | VQDMULHQ_N_S)) | |
1811 | ] | |
1812 | "TARGET_HAVE_MVE" | |
1813 | "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1814 | [(set_attr "type" "mve_move") | |
1815 | ]) | |
1816 | ||
1817 | ;; | |
1818 | ;; [vqdmulhq_s]) | |
1819 | ;; | |
1820 | (define_insn "mve_vqdmulhq_s<mode>" | |
1821 | [ | |
1822 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1823 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1824 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1825 | VQDMULHQ_S)) | |
1826 | ] | |
1827 | "TARGET_HAVE_MVE" | |
1828 | "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" | |
1829 | [(set_attr "type" "mve_move") | |
1830 | ]) | |
1831 | ||
1832 | ;; | |
1833 | ;; [vqrdmulhq_n_s]) | |
1834 | ;; | |
1835 | (define_insn "mve_vqrdmulhq_n_s<mode>" | |
1836 | [ | |
1837 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1838 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1839 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1840 | VQRDMULHQ_N_S)) | |
1841 | ] | |
1842 | "TARGET_HAVE_MVE" | |
1843 | "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1844 | [(set_attr "type" "mve_move") | |
1845 | ]) | |
1846 | ||
1847 | ;; | |
1848 | ;; [vqrdmulhq_s]) | |
1849 | ;; | |
1850 | (define_insn "mve_vqrdmulhq_s<mode>" | |
1851 | [ | |
1852 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1853 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1854 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1855 | VQRDMULHQ_S)) | |
1856 | ] | |
1857 | "TARGET_HAVE_MVE" | |
1858 | "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" | |
1859 | [(set_attr "type" "mve_move") | |
1860 | ]) | |
1861 | ||
1862 | ;; | |
1863 | ;; [vqrshlq_n_s, vqrshlq_n_u]) | |
1864 | ;; | |
1865 | (define_insn "mve_vqrshlq_n_<supf><mode>" | |
1866 | [ | |
1867 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1868 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1869 | (match_operand:SI 2 "s_register_operand" "r")] | |
1870 | VQRSHLQ_N)) | |
1871 | ] | |
1872 | "TARGET_HAVE_MVE" | |
1873 | "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1874 | [(set_attr "type" "mve_move") | |
1875 | ]) | |
1876 | ||
1877 | ;; | |
1878 | ;; [vqrshlq_s, vqrshlq_u]) | |
1879 | ;; | |
1880 | (define_insn "mve_vqrshlq_<supf><mode>" | |
1881 | [ | |
1882 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1883 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1884 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1885 | VQRSHLQ)) | |
1886 | ] | |
1887 | "TARGET_HAVE_MVE" | |
1888 | "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1889 | [(set_attr "type" "mve_move") | |
1890 | ]) | |
1891 | ||
1892 | ;; | |
1893 | ;; [vqshlq_n_s, vqshlq_n_u]) | |
1894 | ;; | |
1895 | (define_insn "mve_vqshlq_n_<supf><mode>" | |
1896 | [ | |
1897 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1898 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1899 | (match_operand:SI 2 "immediate_operand" "i")] | |
1900 | VQSHLQ_N)) | |
1901 | ] | |
1902 | "TARGET_HAVE_MVE" | |
1903 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1904 | [(set_attr "type" "mve_move") | |
1905 | ]) | |
1906 | ||
1907 | ;; | |
1908 | ;; [vqshlq_r_u, vqshlq_r_s]) | |
1909 | ;; | |
1910 | (define_insn "mve_vqshlq_r_<supf><mode>" | |
1911 | [ | |
1912 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1913 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
1914 | (match_operand:SI 2 "s_register_operand" "r")] | |
1915 | VQSHLQ_R)) | |
1916 | ] | |
1917 | "TARGET_HAVE_MVE" | |
1918 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
1919 | [(set_attr "type" "mve_move") | |
1920 | ]) | |
1921 | ||
1922 | ;; | |
1923 | ;; [vqshlq_s, vqshlq_u]) | |
1924 | ;; | |
1925 | (define_insn "mve_vqshlq_<supf><mode>" | |
1926 | [ | |
1927 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1928 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1929 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1930 | VQSHLQ)) | |
1931 | ] | |
1932 | "TARGET_HAVE_MVE" | |
1933 | "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1934 | [(set_attr "type" "mve_move") | |
1935 | ]) | |
1936 | ||
1937 | ;; | |
1938 | ;; [vqshluq_n_s]) | |
1939 | ;; | |
1940 | (define_insn "mve_vqshluq_n_s<mode>" | |
1941 | [ | |
1942 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1943 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1944 | (match_operand:SI 2 "mve_imm_7" "Ra")] | |
1945 | VQSHLUQ_N_S)) | |
1946 | ] | |
1947 | "TARGET_HAVE_MVE" | |
1948 | "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2" | |
1949 | [(set_attr "type" "mve_move") | |
1950 | ]) | |
1951 | ||
1952 | ;; | |
1953 | ;; [vqsubq_n_s, vqsubq_n_u]) | |
1954 | ;; | |
1955 | (define_insn "mve_vqsubq_n_<supf><mode>" | |
1956 | [ | |
1957 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1958 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1959 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
1960 | VQSUBQ_N)) | |
1961 | ] | |
1962 | "TARGET_HAVE_MVE" | |
1963 | "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
1964 | [(set_attr "type" "mve_move") | |
1965 | ]) | |
1966 | ||
1967 | ;; | |
1968 | ;; [vqsubq_u, vqsubq_s]) | |
1969 | ;; | |
1970 | (define_insn "mve_vqsubq_<supf><mode>" | |
1971 | [ | |
1972 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1973 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1974 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1975 | VQSUBQ)) | |
1976 | ] | |
1977 | "TARGET_HAVE_MVE" | |
1978 | "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1979 | [(set_attr "type" "mve_move") | |
1980 | ]) | |
1981 | ||
1982 | ;; | |
1983 | ;; [vrhaddq_s, vrhaddq_u]) | |
1984 | ;; | |
1985 | (define_insn "mve_vrhaddq_<supf><mode>" | |
1986 | [ | |
1987 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
1988 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
1989 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
1990 | VRHADDQ)) | |
1991 | ] | |
1992 | "TARGET_HAVE_MVE" | |
1993 | "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
1994 | [(set_attr "type" "mve_move") | |
1995 | ]) | |
1996 | ||
1997 | ;; | |
1998 | ;; [vrmulhq_s, vrmulhq_u]) | |
1999 | ;; | |
2000 | (define_insn "mve_vrmulhq_<supf><mode>" | |
2001 | [ | |
2002 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2003 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2004 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
2005 | VRMULHQ)) | |
2006 | ] | |
2007 | "TARGET_HAVE_MVE" | |
2008 | "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
2009 | [(set_attr "type" "mve_move") | |
2010 | ]) | |
2011 | ||
2012 | ;; | |
2013 | ;; [vrshlq_n_u, vrshlq_n_s]) | |
2014 | ;; | |
2015 | (define_insn "mve_vrshlq_n_<supf><mode>" | |
2016 | [ | |
2017 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2018 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2019 | (match_operand:SI 2 "s_register_operand" "r")] | |
2020 | VRSHLQ_N)) | |
2021 | ] | |
2022 | "TARGET_HAVE_MVE" | |
2023 | "vrshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
2024 | [(set_attr "type" "mve_move") | |
2025 | ]) | |
2026 | ||
2027 | ;; | |
2028 | ;; [vrshlq_s, vrshlq_u]) | |
2029 | ;; | |
2030 | (define_insn "mve_vrshlq_<supf><mode>" | |
2031 | [ | |
2032 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2033 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2034 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
2035 | VRSHLQ)) | |
2036 | ] | |
2037 | "TARGET_HAVE_MVE" | |
2038 | "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" | |
2039 | [(set_attr "type" "mve_move") | |
2040 | ]) | |
2041 | ||
2042 | ;; | |
2043 | ;; [vrshrq_n_s, vrshrq_n_u]) | |
2044 | ;; | |
2045 | (define_insn "mve_vrshrq_n_<supf><mode>" | |
2046 | [ | |
2047 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2048 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2049 | (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] | |
2050 | VRSHRQ_N)) | |
2051 | ] | |
2052 | "TARGET_HAVE_MVE" | |
2053 | "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
2054 | [(set_attr "type" "mve_move") | |
2055 | ]) | |
2056 | ||
2057 | ;; | |
2058 | ;; [vshlq_n_u, vshlq_n_s]) | |
2059 | ;; | |
2060 | (define_insn "mve_vshlq_n_<supf><mode>" | |
2061 | [ | |
2062 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2063 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2064 | (match_operand:SI 2 "immediate_operand" "i")] | |
2065 | VSHLQ_N)) | |
2066 | ] | |
2067 | "TARGET_HAVE_MVE" | |
2068 | "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
2069 | [(set_attr "type" "mve_move") | |
2070 | ]) | |
2071 | ||
2072 | ;; | |
2073 | ;; [vshlq_r_s, vshlq_r_u]) | |
2074 | ;; | |
2075 | (define_insn "mve_vshlq_r_<supf><mode>" | |
2076 | [ | |
2077 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2078 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") | |
2079 | (match_operand:SI 2 "s_register_operand" "r")] | |
2080 | VSHLQ_R)) | |
2081 | ] | |
2082 | "TARGET_HAVE_MVE" | |
2083 | "vshl.<supf>%#<V_sz_elem>\t%q0, %2" | |
2084 | [(set_attr "type" "mve_move") | |
2085 | ]) | |
2086 | ||
2087 | ;; | |
2088 | ;; [vsubq_n_s, vsubq_n_u]) | |
2089 | ;; | |
2090 | (define_insn "mve_vsubq_n_<supf><mode>" | |
2091 | [ | |
2092 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2093 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2094 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2095 | VSUBQ_N)) | |
2096 | ] | |
2097 | "TARGET_HAVE_MVE" | |
2098 | "vsub.i%#<V_sz_elem>\t%q0, %q1, %2" | |
2099 | [(set_attr "type" "mve_move") | |
2100 | ]) | |
2101 | ||
2102 | ;; | |
2103 | ;; [vsubq_s, vsubq_u]) | |
2104 | ;; | |
2105 | (define_insn "mve_vsubq_<supf><mode>" | |
2106 | [ | |
2107 | (set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
2108 | (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") | |
2109 | (match_operand:MVE_2 2 "s_register_operand" "w")] | |
2110 | VSUBQ)) | |
2111 | ] | |
2112 | "TARGET_HAVE_MVE" | |
2113 | "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2" | |
2114 | [(set_attr "type" "mve_move") | |
2115 | ]) | |
2116 | ||
2117 | ;; | |
2118 | ;; [vabdq_f]) | |
2119 | ;; | |
2120 | (define_insn "mve_vabdq_f<mode>" | |
2121 | [ | |
2122 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2123 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2124 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2125 | VABDQ_F)) | |
2126 | ] | |
2127 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2128 | "vabd.f%#<V_sz_elem> %q0, %q1, %q2" | |
2129 | [(set_attr "type" "mve_move") | |
2130 | ]) | |
2131 | ||
2132 | ;; | |
2133 | ;; [vaddlvaq_s vaddlvaq_u]) | |
2134 | ;; | |
2135 | (define_insn "mve_vaddlvaq_<supf>v4si" | |
2136 | [ | |
2137 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2138 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
2139 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2140 | VADDLVAQ)) | |
2141 | ] | |
2142 | "TARGET_HAVE_MVE" | |
2143 | "vaddlva.<supf>32 %Q0, %R0, %q2" | |
2144 | [(set_attr "type" "mve_move") | |
2145 | ]) | |
2146 | ||
2147 | ;; | |
2148 | ;; [vaddq_n_f]) | |
2149 | ;; | |
2150 | (define_insn "mve_vaddq_n_f<mode>" | |
2151 | [ | |
2152 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2153 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2154 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2155 | VADDQ_N_F)) | |
2156 | ] | |
2157 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2158 | "vadd.f%#<V_sz_elem> %q0, %q1, %2" | |
2159 | [(set_attr "type" "mve_move") | |
2160 | ]) | |
2161 | ||
2162 | ;; | |
2163 | ;; [vandq_f]) | |
2164 | ;; | |
2165 | (define_insn "mve_vandq_f<mode>" | |
2166 | [ | |
2167 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2168 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2169 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2170 | VANDQ_F)) | |
2171 | ] | |
2172 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2173 | "vand %q0, %q1, %q2" | |
2174 | [(set_attr "type" "mve_move") | |
2175 | ]) | |
2176 | ||
2177 | ;; | |
2178 | ;; [vbicq_f]) | |
2179 | ;; | |
2180 | (define_insn "mve_vbicq_f<mode>" | |
2181 | [ | |
2182 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2183 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2184 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2185 | VBICQ_F)) | |
2186 | ] | |
2187 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2188 | "vbic %q0, %q1, %q2" | |
2189 | [(set_attr "type" "mve_move") | |
2190 | ]) | |
2191 | ||
2192 | ;; | |
2193 | ;; [vbicq_n_s, vbicq_n_u]) | |
2194 | ;; | |
2195 | (define_insn "mve_vbicq_n_<supf><mode>" | |
2196 | [ | |
2197 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2198 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2199 | (match_operand:SI 2 "immediate_operand" "i")] | |
2200 | VBICQ_N)) | |
2201 | ] | |
2202 | "TARGET_HAVE_MVE" | |
2203 | "vbic.i%#<V_sz_elem> %q0, %2" | |
2204 | [(set_attr "type" "mve_move") | |
2205 | ]) | |
2206 | ||
2207 | ;; | |
2208 | ;; [vcaddq_rot270_f]) | |
2209 | ;; | |
2210 | (define_insn "mve_vcaddq_rot270_f<mode>" | |
2211 | [ | |
2212 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2213 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2214 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2215 | VCADDQ_ROT270_F)) | |
2216 | ] | |
2217 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2218 | "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270" | |
2219 | [(set_attr "type" "mve_move") | |
2220 | ]) | |
2221 | ||
2222 | ;; | |
2223 | ;; [vcaddq_rot90_f]) | |
2224 | ;; | |
2225 | (define_insn "mve_vcaddq_rot90_f<mode>" | |
2226 | [ | |
2227 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2228 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2229 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2230 | VCADDQ_ROT90_F)) | |
2231 | ] | |
2232 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2233 | "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90" | |
2234 | [(set_attr "type" "mve_move") | |
2235 | ]) | |
2236 | ||
2237 | ;; | |
2238 | ;; [vcmpeqq_f]) | |
2239 | ;; | |
2240 | (define_insn "mve_vcmpeqq_f<mode>" | |
2241 | [ | |
2242 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2243 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2244 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2245 | VCMPEQQ_F)) | |
2246 | ] | |
2247 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2248 | "vcmp.f%#<V_sz_elem> eq, %q1, %q2" | |
2249 | [(set_attr "type" "mve_move") | |
2250 | ]) | |
2251 | ||
2252 | ;; | |
2253 | ;; [vcmpeqq_n_f]) | |
2254 | ;; | |
2255 | (define_insn "mve_vcmpeqq_n_f<mode>" | |
2256 | [ | |
2257 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2258 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2259 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2260 | VCMPEQQ_N_F)) | |
2261 | ] | |
2262 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2263 | "vcmp.f%#<V_sz_elem> eq, %q1, %2" | |
2264 | [(set_attr "type" "mve_move") | |
2265 | ]) | |
2266 | ||
2267 | ;; | |
2268 | ;; [vcmpgeq_f]) | |
2269 | ;; | |
2270 | (define_insn "mve_vcmpgeq_f<mode>" | |
2271 | [ | |
2272 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2273 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2274 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2275 | VCMPGEQ_F)) | |
2276 | ] | |
2277 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2278 | "vcmp.f%#<V_sz_elem> ge, %q1, %q2" | |
2279 | [(set_attr "type" "mve_move") | |
2280 | ]) | |
2281 | ||
2282 | ;; | |
2283 | ;; [vcmpgeq_n_f]) | |
2284 | ;; | |
2285 | (define_insn "mve_vcmpgeq_n_f<mode>" | |
2286 | [ | |
2287 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2288 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2289 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2290 | VCMPGEQ_N_F)) | |
2291 | ] | |
2292 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2293 | "vcmp.f%#<V_sz_elem> ge, %q1, %2" | |
2294 | [(set_attr "type" "mve_move") | |
2295 | ]) | |
2296 | ||
2297 | ;; | |
2298 | ;; [vcmpgtq_f]) | |
2299 | ;; | |
2300 | (define_insn "mve_vcmpgtq_f<mode>" | |
2301 | [ | |
2302 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2303 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2304 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2305 | VCMPGTQ_F)) | |
2306 | ] | |
2307 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2308 | "vcmp.f%#<V_sz_elem> gt, %q1, %q2" | |
2309 | [(set_attr "type" "mve_move") | |
2310 | ]) | |
2311 | ||
2312 | ;; | |
2313 | ;; [vcmpgtq_n_f]) | |
2314 | ;; | |
2315 | (define_insn "mve_vcmpgtq_n_f<mode>" | |
2316 | [ | |
2317 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2318 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2319 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2320 | VCMPGTQ_N_F)) | |
2321 | ] | |
2322 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2323 | "vcmp.f%#<V_sz_elem> gt, %q1, %2" | |
2324 | [(set_attr "type" "mve_move") | |
2325 | ]) | |
2326 | ||
2327 | ;; | |
2328 | ;; [vcmpleq_f]) | |
2329 | ;; | |
2330 | (define_insn "mve_vcmpleq_f<mode>" | |
2331 | [ | |
2332 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2333 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2334 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2335 | VCMPLEQ_F)) | |
2336 | ] | |
2337 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2338 | "vcmp.f%#<V_sz_elem> le, %q1, %q2" | |
2339 | [(set_attr "type" "mve_move") | |
2340 | ]) | |
2341 | ||
2342 | ;; | |
2343 | ;; [vcmpleq_n_f]) | |
2344 | ;; | |
2345 | (define_insn "mve_vcmpleq_n_f<mode>" | |
2346 | [ | |
2347 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2348 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2349 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2350 | VCMPLEQ_N_F)) | |
2351 | ] | |
2352 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2353 | "vcmp.f%#<V_sz_elem> le, %q1, %2" | |
2354 | [(set_attr "type" "mve_move") | |
2355 | ]) | |
2356 | ||
2357 | ;; | |
2358 | ;; [vcmpltq_f]) | |
2359 | ;; | |
2360 | (define_insn "mve_vcmpltq_f<mode>" | |
2361 | [ | |
2362 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2363 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2364 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2365 | VCMPLTQ_F)) | |
2366 | ] | |
2367 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2368 | "vcmp.f%#<V_sz_elem> lt, %q1, %q2" | |
2369 | [(set_attr "type" "mve_move") | |
2370 | ]) | |
2371 | ||
2372 | ;; | |
2373 | ;; [vcmpltq_n_f]) | |
2374 | ;; | |
2375 | (define_insn "mve_vcmpltq_n_f<mode>" | |
2376 | [ | |
2377 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2378 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2379 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2380 | VCMPLTQ_N_F)) | |
2381 | ] | |
2382 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2383 | "vcmp.f%#<V_sz_elem> lt, %q1, %2" | |
2384 | [(set_attr "type" "mve_move") | |
2385 | ]) | |
2386 | ||
2387 | ;; | |
2388 | ;; [vcmpneq_f]) | |
2389 | ;; | |
2390 | (define_insn "mve_vcmpneq_f<mode>" | |
2391 | [ | |
2392 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2393 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2394 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2395 | VCMPNEQ_F)) | |
2396 | ] | |
2397 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2398 | "vcmp.f%#<V_sz_elem> ne, %q1, %q2" | |
2399 | [(set_attr "type" "mve_move") | |
2400 | ]) | |
2401 | ||
2402 | ;; | |
2403 | ;; [vcmpneq_n_f]) | |
2404 | ;; | |
2405 | (define_insn "mve_vcmpneq_n_f<mode>" | |
2406 | [ | |
2407 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2408 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2409 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2410 | VCMPNEQ_N_F)) | |
2411 | ] | |
2412 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2413 | "vcmp.f%#<V_sz_elem> ne, %q1, %2" | |
2414 | [(set_attr "type" "mve_move") | |
2415 | ]) | |
2416 | ||
2417 | ;; | |
2418 | ;; [vcmulq_f]) | |
2419 | ;; | |
2420 | (define_insn "mve_vcmulq_f<mode>" | |
2421 | [ | |
2422 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2423 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2424 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2425 | VCMULQ_F)) | |
2426 | ] | |
2427 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2428 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0" | |
2429 | [(set_attr "type" "mve_move") | |
2430 | ]) | |
2431 | ||
2432 | ;; | |
2433 | ;; [vcmulq_rot180_f]) | |
2434 | ;; | |
2435 | (define_insn "mve_vcmulq_rot180_f<mode>" | |
2436 | [ | |
2437 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2438 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2439 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2440 | VCMULQ_ROT180_F)) | |
2441 | ] | |
2442 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2443 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180" | |
2444 | [(set_attr "type" "mve_move") | |
2445 | ]) | |
2446 | ||
2447 | ;; | |
2448 | ;; [vcmulq_rot270_f]) | |
2449 | ;; | |
2450 | (define_insn "mve_vcmulq_rot270_f<mode>" | |
2451 | [ | |
2452 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2453 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2454 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2455 | VCMULQ_ROT270_F)) | |
2456 | ] | |
2457 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2458 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270" | |
2459 | [(set_attr "type" "mve_move") | |
2460 | ]) | |
2461 | ||
2462 | ;; | |
2463 | ;; [vcmulq_rot90_f]) | |
2464 | ;; | |
2465 | (define_insn "mve_vcmulq_rot90_f<mode>" | |
2466 | [ | |
2467 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2468 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2469 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2470 | VCMULQ_ROT90_F)) | |
2471 | ] | |
2472 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2473 | "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90" | |
2474 | [(set_attr "type" "mve_move") | |
2475 | ]) | |
2476 | ||
2477 | ;; | |
2478 | ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) | |
2479 | ;; | |
2480 | (define_insn "mve_vctp<mode1>q_mhi" | |
2481 | [ | |
2482 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
2483 | (unspec:HI [(match_operand:SI 1 "s_register_operand" "r") | |
2484 | (match_operand:HI 2 "vpr_register_operand" "Up")] | |
2485 | VCTPQ_M)) | |
2486 | ] | |
2487 | "TARGET_HAVE_MVE" | |
2488 | "vpst\;vctpt.<mode1> %1" | |
2489 | [(set_attr "type" "mve_move") | |
2490 | (set_attr "length""8")]) | |
2491 | ||
2492 | ;; | |
2493 | ;; [vcvtbq_f16_f32]) | |
2494 | ;; | |
2495 | (define_insn "mve_vcvtbq_f16_f32v8hf" | |
2496 | [ | |
2497 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2498 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2499 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
2500 | VCVTBQ_F16_F32)) | |
2501 | ] | |
2502 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2503 | "vcvtb.f16.f32 %q0, %q2" | |
2504 | [(set_attr "type" "mve_move") | |
2505 | ]) | |
2506 | ||
2507 | ;; | |
2508 | ;; [vcvttq_f16_f32]) | |
2509 | ;; | |
2510 | (define_insn "mve_vcvttq_f16_f32v8hf" | |
2511 | [ | |
2512 | (set (match_operand:V8HF 0 "s_register_operand" "=w") | |
2513 | (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") | |
2514 | (match_operand:V4SF 2 "s_register_operand" "w")] | |
2515 | VCVTTQ_F16_F32)) | |
2516 | ] | |
2517 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2518 | "vcvtt.f16.f32 %q0, %q2" | |
2519 | [(set_attr "type" "mve_move") | |
2520 | ]) | |
2521 | ||
2522 | ;; | |
2523 | ;; [veorq_f]) | |
2524 | ;; | |
2525 | (define_insn "mve_veorq_f<mode>" | |
2526 | [ | |
2527 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2528 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2529 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2530 | VEORQ_F)) | |
2531 | ] | |
2532 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2533 | "veor %q0, %q1, %q2" | |
2534 | [(set_attr "type" "mve_move") | |
2535 | ]) | |
2536 | ||
2537 | ;; | |
2538 | ;; [vmaxnmaq_f]) | |
2539 | ;; | |
2540 | (define_insn "mve_vmaxnmaq_f<mode>" | |
2541 | [ | |
2542 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2543 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2544 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2545 | VMAXNMAQ_F)) | |
2546 | ] | |
2547 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2548 | "vmaxnma.f%#<V_sz_elem> %q0, %q2" | |
2549 | [(set_attr "type" "mve_move") | |
2550 | ]) | |
2551 | ||
2552 | ;; | |
2553 | ;; [vmaxnmavq_f]) | |
2554 | ;; | |
2555 | (define_insn "mve_vmaxnmavq_f<mode>" | |
2556 | [ | |
2557 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2558 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2559 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2560 | VMAXNMAVQ_F)) | |
2561 | ] | |
2562 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2563 | "vmaxnmav.f%#<V_sz_elem> %0, %q2" | |
2564 | [(set_attr "type" "mve_move") | |
2565 | ]) | |
2566 | ||
2567 | ;; | |
2568 | ;; [vmaxnmq_f]) | |
2569 | ;; | |
2570 | (define_insn "mve_vmaxnmq_f<mode>" | |
2571 | [ | |
2572 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2573 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2574 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2575 | VMAXNMQ_F)) | |
2576 | ] | |
2577 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2578 | "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2" | |
2579 | [(set_attr "type" "mve_move") | |
2580 | ]) | |
2581 | ||
2582 | ;; | |
2583 | ;; [vmaxnmvq_f]) | |
2584 | ;; | |
2585 | (define_insn "mve_vmaxnmvq_f<mode>" | |
2586 | [ | |
2587 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2588 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2589 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2590 | VMAXNMVQ_F)) | |
2591 | ] | |
2592 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2593 | "vmaxnmv.f%#<V_sz_elem> %0, %q2" | |
2594 | [(set_attr "type" "mve_move") | |
2595 | ]) | |
2596 | ||
2597 | ;; | |
2598 | ;; [vminnmaq_f]) | |
2599 | ;; | |
2600 | (define_insn "mve_vminnmaq_f<mode>" | |
2601 | [ | |
2602 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2603 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
2604 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2605 | VMINNMAQ_F)) | |
2606 | ] | |
2607 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2608 | "vminnma.f%#<V_sz_elem> %q0, %q2" | |
2609 | [(set_attr "type" "mve_move") | |
2610 | ]) | |
2611 | ||
2612 | ;; | |
2613 | ;; [vminnmavq_f]) | |
2614 | ;; | |
2615 | (define_insn "mve_vminnmavq_f<mode>" | |
2616 | [ | |
2617 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2618 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2619 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2620 | VMINNMAVQ_F)) | |
2621 | ] | |
2622 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2623 | "vminnmav.f%#<V_sz_elem> %0, %q2" | |
2624 | [(set_attr "type" "mve_move") | |
2625 | ]) | |
2626 | ||
2627 | ;; | |
2628 | ;; [vminnmq_f]) | |
2629 | ;; | |
2630 | (define_insn "mve_vminnmq_f<mode>" | |
2631 | [ | |
2632 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2633 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2634 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2635 | VMINNMQ_F)) | |
2636 | ] | |
2637 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2638 | "vminnm.f%#<V_sz_elem> %q0, %q1, %q2" | |
2639 | [(set_attr "type" "mve_move") | |
2640 | ]) | |
2641 | ||
2642 | ;; | |
2643 | ;; [vminnmvq_f]) | |
2644 | ;; | |
2645 | (define_insn "mve_vminnmvq_f<mode>" | |
2646 | [ | |
2647 | (set (match_operand:<V_elem> 0 "s_register_operand" "=r") | |
2648 | (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") | |
2649 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2650 | VMINNMVQ_F)) | |
2651 | ] | |
2652 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2653 | "vminnmv.f%#<V_sz_elem> %0, %q2" | |
2654 | [(set_attr "type" "mve_move") | |
2655 | ]) | |
2656 | ||
2657 | ;; | |
2658 | ;; [vmlaldavq_u, vmlaldavq_s]) | |
2659 | ;; | |
2660 | (define_insn "mve_vmlaldavq_<supf><mode>" | |
2661 | [ | |
2662 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2663 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2664 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2665 | VMLALDAVQ)) | |
2666 | ] | |
2667 | "TARGET_HAVE_MVE" | |
2668 | "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2669 | [(set_attr "type" "mve_move") | |
2670 | ]) | |
2671 | ||
2672 | ;; | |
2673 | ;; [vmlaldavxq_s]) | |
2674 | ;; | |
2675 | (define_insn "mve_vmlaldavxq_s<mode>" | |
2676 | [ | |
2677 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2678 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2679 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2680 | VMLALDAVXQ_S)) | |
2681 | ] | |
2682 | "TARGET_HAVE_MVE" | |
2683 | "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2684 | [(set_attr "type" "mve_move") | |
2685 | ]) | |
2686 | ||
2687 | ;; | |
2688 | ;; [vmlsldavq_s]) | |
2689 | ;; | |
2690 | (define_insn "mve_vmlsldavq_s<mode>" | |
2691 | [ | |
2692 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2693 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2694 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2695 | VMLSLDAVQ_S)) | |
2696 | ] | |
2697 | "TARGET_HAVE_MVE" | |
2698 | "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2699 | [(set_attr "type" "mve_move") | |
2700 | ]) | |
2701 | ||
2702 | ;; | |
2703 | ;; [vmlsldavxq_s]) | |
2704 | ;; | |
2705 | (define_insn "mve_vmlsldavxq_s<mode>" | |
2706 | [ | |
2707 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2708 | (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2709 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2710 | VMLSLDAVXQ_S)) | |
2711 | ] | |
2712 | "TARGET_HAVE_MVE" | |
2713 | "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2" | |
2714 | [(set_attr "type" "mve_move") | |
2715 | ]) | |
2716 | ||
2717 | ;; | |
2718 | ;; [vmovnbq_u, vmovnbq_s]) | |
2719 | ;; | |
2720 | (define_insn "mve_vmovnbq_<supf><mode>" | |
2721 | [ | |
2722 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2723 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2724 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2725 | VMOVNBQ)) | |
2726 | ] | |
2727 | "TARGET_HAVE_MVE" | |
2728 | "vmovnb.i%#<V_sz_elem> %q0, %q2" | |
2729 | [(set_attr "type" "mve_move") | |
2730 | ]) | |
2731 | ||
2732 | ;; | |
2733 | ;; [vmovntq_s, vmovntq_u]) | |
2734 | ;; | |
2735 | (define_insn "mve_vmovntq_<supf><mode>" | |
2736 | [ | |
2737 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2738 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2739 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2740 | VMOVNTQ)) | |
2741 | ] | |
2742 | "TARGET_HAVE_MVE" | |
2743 | "vmovnt.i%#<V_sz_elem> %q0, %q2" | |
2744 | [(set_attr "type" "mve_move") | |
2745 | ]) | |
2746 | ||
2747 | ;; | |
2748 | ;; [vmulq_f]) | |
2749 | ;; | |
2750 | (define_insn "mve_vmulq_f<mode>" | |
2751 | [ | |
2752 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2753 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2754 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2755 | VMULQ_F)) | |
2756 | ] | |
2757 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2758 | "vmul.f%#<V_sz_elem> %q0, %q1, %q2" | |
2759 | [(set_attr "type" "mve_move") | |
2760 | ]) | |
2761 | ||
2762 | ;; | |
2763 | ;; [vmulq_n_f]) | |
2764 | ;; | |
2765 | (define_insn "mve_vmulq_n_f<mode>" | |
2766 | [ | |
2767 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2768 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2769 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2770 | VMULQ_N_F)) | |
2771 | ] | |
2772 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2773 | "vmul.f%#<V_sz_elem> %q0, %q1, %2" | |
2774 | [(set_attr "type" "mve_move") | |
2775 | ]) | |
2776 | ||
2777 | ;; | |
2778 | ;; [vornq_f]) | |
2779 | ;; | |
2780 | (define_insn "mve_vornq_f<mode>" | |
2781 | [ | |
2782 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2783 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2784 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2785 | VORNQ_F)) | |
2786 | ] | |
2787 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2788 | "vorn %q0, %q1, %q2" | |
2789 | [(set_attr "type" "mve_move") | |
2790 | ]) | |
2791 | ||
2792 | ;; | |
2793 | ;; [vorrq_f]) | |
2794 | ;; | |
2795 | (define_insn "mve_vorrq_f<mode>" | |
2796 | [ | |
2797 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
2798 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
2799 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
2800 | VORRQ_F)) | |
2801 | ] | |
2802 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
2803 | "vorr %q0, %q1, %q2" | |
2804 | [(set_attr "type" "mve_move") | |
2805 | ]) | |
2806 | ||
2807 | ;; | |
2808 | ;; [vorrq_n_u, vorrq_n_s]) | |
2809 | ;; | |
2810 | (define_insn "mve_vorrq_n_<supf><mode>" | |
2811 | [ | |
2812 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
2813 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
2814 | (match_operand:SI 2 "immediate_operand" "i")] | |
2815 | VORRQ_N)) | |
2816 | ] | |
2817 | "TARGET_HAVE_MVE" | |
2818 | "vorr.i%#<V_sz_elem> %q0, %2" | |
2819 | [(set_attr "type" "mve_move") | |
2820 | ]) | |
2821 | ||
2822 | ;; | |
2823 | ;; [vqdmullbq_n_s]) | |
2824 | ;; | |
2825 | (define_insn "mve_vqdmullbq_n_s<mode>" | |
2826 | [ | |
2827 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2828 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2829 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2830 | VQDMULLBQ_N_S)) | |
2831 | ] | |
2832 | "TARGET_HAVE_MVE" | |
2833 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2" | |
2834 | [(set_attr "type" "mve_move") | |
2835 | ]) | |
2836 | ||
2837 | ;; | |
2838 | ;; [vqdmullbq_s]) | |
2839 | ;; | |
2840 | (define_insn "mve_vqdmullbq_s<mode>" | |
2841 | [ | |
2842 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2843 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2844 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2845 | VQDMULLBQ_S)) | |
2846 | ] | |
2847 | "TARGET_HAVE_MVE" | |
2848 | "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2" | |
2849 | [(set_attr "type" "mve_move") | |
2850 | ]) | |
2851 | ||
2852 | ;; | |
2853 | ;; [vqdmulltq_n_s]) | |
2854 | ;; | |
2855 | (define_insn "mve_vqdmulltq_n_s<mode>" | |
2856 | [ | |
2857 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2858 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2859 | (match_operand:<V_elem> 2 "s_register_operand" "r")] | |
2860 | VQDMULLTQ_N_S)) | |
2861 | ] | |
2862 | "TARGET_HAVE_MVE" | |
2863 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2" | |
2864 | [(set_attr "type" "mve_move") | |
2865 | ]) | |
2866 | ||
2867 | ;; | |
2868 | ;; [vqdmulltq_s]) | |
2869 | ;; | |
2870 | (define_insn "mve_vqdmulltq_s<mode>" | |
2871 | [ | |
2872 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2873 | (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") | |
2874 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2875 | VQDMULLTQ_S)) | |
2876 | ] | |
2877 | "TARGET_HAVE_MVE" | |
2878 | "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2" | |
2879 | [(set_attr "type" "mve_move") | |
2880 | ]) | |
2881 | ||
2882 | ;; | |
2883 | ;; [vqmovnbq_u, vqmovnbq_s]) | |
2884 | ;; | |
2885 | (define_insn "mve_vqmovnbq_<supf><mode>" | |
2886 | [ | |
2887 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2888 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2889 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2890 | VQMOVNBQ)) | |
2891 | ] | |
2892 | "TARGET_HAVE_MVE" | |
2893 | "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2" | |
2894 | [(set_attr "type" "mve_move") | |
2895 | ]) | |
2896 | ||
2897 | ;; | |
2898 | ;; [vqmovntq_u, vqmovntq_s]) | |
2899 | ;; | |
2900 | (define_insn "mve_vqmovntq_<supf><mode>" | |
2901 | [ | |
2902 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2903 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2904 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2905 | VQMOVNTQ)) | |
2906 | ] | |
2907 | "TARGET_HAVE_MVE" | |
2908 | "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2" | |
2909 | [(set_attr "type" "mve_move") | |
2910 | ]) | |
2911 | ||
2912 | ;; | |
2913 | ;; [vqmovunbq_s]) | |
2914 | ;; | |
2915 | (define_insn "mve_vqmovunbq_s<mode>" | |
2916 | [ | |
2917 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2918 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2919 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2920 | VQMOVUNBQ_S)) | |
2921 | ] | |
2922 | "TARGET_HAVE_MVE" | |
2923 | "vqmovunb.s%#<V_sz_elem> %q0, %q2" | |
2924 | [(set_attr "type" "mve_move") | |
2925 | ]) | |
2926 | ||
2927 | ;; | |
2928 | ;; [vqmovuntq_s]) | |
2929 | ;; | |
2930 | (define_insn "mve_vqmovuntq_s<mode>" | |
2931 | [ | |
2932 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
2933 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
2934 | (match_operand:MVE_5 2 "s_register_operand" "w")] | |
2935 | VQMOVUNTQ_S)) | |
2936 | ] | |
2937 | "TARGET_HAVE_MVE" | |
2938 | "vqmovunt.s%#<V_sz_elem> %q0, %q2" | |
2939 | [(set_attr "type" "mve_move") | |
2940 | ]) | |
2941 | ||
2942 | ;; | |
2943 | ;; [vrmlaldavhxq_s]) | |
2944 | ;; | |
2945 | (define_insn "mve_vrmlaldavhxq_sv4si" | |
2946 | [ | |
2947 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2948 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2949 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2950 | VRMLALDAVHXQ_S)) | |
2951 | ] | |
2952 | "TARGET_HAVE_MVE" | |
2953 | "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2" | |
2954 | [(set_attr "type" "mve_move") | |
2955 | ]) | |
2956 | ||
2957 | ;; | |
2958 | ;; [vrmlsldavhq_s]) | |
2959 | ;; | |
2960 | (define_insn "mve_vrmlsldavhq_sv4si" | |
2961 | [ | |
2962 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2963 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2964 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2965 | VRMLSLDAVHQ_S)) | |
2966 | ] | |
2967 | "TARGET_HAVE_MVE" | |
2968 | "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2" | |
2969 | [(set_attr "type" "mve_move") | |
2970 | ]) | |
2971 | ||
2972 | ;; | |
2973 | ;; [vrmlsldavhxq_s]) | |
2974 | ;; | |
2975 | (define_insn "mve_vrmlsldavhxq_sv4si" | |
2976 | [ | |
2977 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
2978 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
2979 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
2980 | VRMLSLDAVHXQ_S)) | |
2981 | ] | |
2982 | "TARGET_HAVE_MVE" | |
2983 | "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2" | |
2984 | [(set_attr "type" "mve_move") | |
2985 | ]) | |
2986 | ||
2987 | ;; | |
2988 | ;; [vshllbq_n_s, vshllbq_n_u]) | |
2989 | ;; | |
2990 | (define_insn "mve_vshllbq_n_<supf><mode>" | |
2991 | [ | |
2992 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
2993 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
2994 | (match_operand:SI 2 "immediate_operand" "i")] | |
2995 | VSHLLBQ_N)) | |
2996 | ] | |
2997 | "TARGET_HAVE_MVE" | |
2998 | "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
2999 | [(set_attr "type" "mve_move") | |
3000 | ]) | |
3001 | ||
3002 | ;; | |
3003 | ;; [vshlltq_n_u, vshlltq_n_s]) | |
3004 | ;; | |
3005 | (define_insn "mve_vshlltq_n_<supf><mode>" | |
3006 | [ | |
3007 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3008 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
3009 | (match_operand:SI 2 "immediate_operand" "i")] | |
3010 | VSHLLTQ_N)) | |
3011 | ] | |
3012 | "TARGET_HAVE_MVE" | |
3013 | "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2" | |
3014 | [(set_attr "type" "mve_move") | |
3015 | ]) | |
3016 | ||
3017 | ;; | |
3018 | ;; [vsubq_f]) | |
3019 | ;; | |
3020 | (define_insn "mve_vsubq_f<mode>" | |
3021 | [ | |
3022 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3023 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") | |
3024 | (match_operand:MVE_0 2 "s_register_operand" "w")] | |
3025 | VSUBQ_F)) | |
3026 | ] | |
3027 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3028 | "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2" | |
3029 | [(set_attr "type" "mve_move") | |
3030 | ]) | |
3031 | ||
3032 | ;; | |
3033 | ;; [vmulltq_poly_p]) | |
3034 | ;; | |
3035 | (define_insn "mve_vmulltq_poly_p<mode>" | |
3036 | [ | |
3037 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3038 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
3039 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
3040 | VMULLTQ_POLY_P)) | |
3041 | ] | |
3042 | "TARGET_HAVE_MVE" | |
3043 | "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
3044 | [(set_attr "type" "mve_move") | |
3045 | ]) | |
3046 | ||
3047 | ;; | |
3048 | ;; [vmullbq_poly_p]) | |
3049 | ;; | |
3050 | (define_insn "mve_vmullbq_poly_p<mode>" | |
3051 | [ | |
3052 | (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") | |
3053 | (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") | |
3054 | (match_operand:MVE_3 2 "s_register_operand" "w")] | |
3055 | VMULLBQ_POLY_P)) | |
3056 | ] | |
3057 | "TARGET_HAVE_MVE" | |
3058 | "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2" | |
3059 | [(set_attr "type" "mve_move") | |
3060 | ]) | |
3061 | ||
3062 | ;; | |
3063 | ;; [vrmlaldavhq_u vrmlaldavhq_s]) | |
3064 | ;; | |
3065 | (define_insn "mve_vrmlaldavhq_<supf>v4si" | |
3066 | [ | |
3067 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3068 | (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") | |
3069 | (match_operand:V4SI 2 "s_register_operand" "w")] | |
3070 | VRMLALDAVHQ)) | |
3071 | ] | |
3072 | "TARGET_HAVE_MVE" | |
3073 | "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2" | |
3074 | [(set_attr "type" "mve_move") | |
3075 | ]) | |
3076 | ||
3077 | ;; | |
3078 | ;; [vbicq_m_n_s, vbicq_m_n_u]) | |
3079 | ;; | |
3080 | (define_insn "mve_vbicq_m_n_<supf><mode>" | |
3081 | [ | |
3082 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
3083 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
3084 | (match_operand:SI 2 "immediate_operand" "i") | |
3085 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3086 | VBICQ_M_N)) | |
3087 | ] | |
3088 | "TARGET_HAVE_MVE" | |
3089 | "vpst\;vbict.i%#<V_sz_elem> %q0, %2" | |
3090 | [(set_attr "type" "mve_move") | |
3091 | (set_attr "length""8")]) | |
3092 | ;; | |
3093 | ;; [vcmpeqq_m_f]) | |
3094 | ;; | |
3095 | (define_insn "mve_vcmpeqq_m_f<mode>" | |
3096 | [ | |
3097 | (set (match_operand:HI 0 "vpr_register_operand" "=Up") | |
3098 | (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") | |
3099 | (match_operand:MVE_0 2 "s_register_operand" "w") | |
3100 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3101 | VCMPEQQ_M_F)) | |
3102 | ] | |
3103 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3104 | "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2" | |
3105 | [(set_attr "type" "mve_move") | |
3106 | (set_attr "length""8")]) | |
3107 | ;; | |
3108 | ;; [vcvtaq_m_u, vcvtaq_m_s]) | |
3109 | ;; | |
3110 | (define_insn "mve_vcvtaq_m_<supf><mode>" | |
3111 | [ | |
3112 | (set (match_operand:MVE_5 0 "s_register_operand" "=w") | |
3113 | (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") | |
3114 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
3115 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3116 | VCVTAQ_M)) | |
3117 | ] | |
3118 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3119 | "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" | |
3120 | [(set_attr "type" "mve_move") | |
3121 | (set_attr "length""8")]) | |
3122 | ;; | |
3123 | ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) | |
3124 | ;; | |
3125 | (define_insn "mve_vcvtq_m_to_f_<supf><mode>" | |
3126 | [ | |
3127 | (set (match_operand:MVE_0 0 "s_register_operand" "=w") | |
3128 | (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") | |
3129 | (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") | |
3130 | (match_operand:HI 3 "vpr_register_operand" "Up")] | |
3131 | VCVTQ_M_TO_F)) | |
3132 | ] | |
3133 | "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" | |
3134 | "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2" | |
3135 | [(set_attr "type" "mve_move") | |
3136 | (set_attr "length""8")]) | |
3137 | ;; | |
3138 | ;; [vqrshrnbq_n_u, vqrshrnbq_n_s]) | |
3139 | ;; | |
3140 | (define_insn "mve_vqrshrnbq_n_<supf><mode>" | |
3141 | [ | |
3142 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
3143 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
3144 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3145 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
3146 | VQRSHRNBQ_N)) | |
3147 | ] | |
3148 | "TARGET_HAVE_MVE" | |
3149 | "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3" | |
3150 | [(set_attr "type" "mve_move") | |
3151 | ]) | |
3152 | ;; | |
3153 | ;; [vqrshrunbq_n_s]) | |
3154 | ;; | |
3155 | (define_insn "mve_vqrshrunbq_n_s<mode>" | |
3156 | [ | |
3157 | (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") | |
3158 | (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") | |
3159 | (match_operand:MVE_5 2 "s_register_operand" "w") | |
3160 | (match_operand:SI 3 "mve_imm_8" "Rb")] | |
3161 | VQRSHRUNBQ_N_S)) | |
3162 | ] | |
3163 | "TARGET_HAVE_MVE" | |
3164 | "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3" | |
3165 | [(set_attr "type" "mve_move") | |
3166 | ]) | |
3167 | ;; | |
3168 | ;; [vrmlaldavhaq_s vrmlaldavhaq_u]) | |
3169 | ;; | |
3170 | (define_insn "mve_vrmlaldavhaq_<supf>v4si" | |
3171 | [ | |
3172 | (set (match_operand:DI 0 "s_register_operand" "=r") | |
3173 | (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") | |
3174 | (match_operand:V4SI 2 "s_register_operand" "w") | |
3175 | (match_operand:V4SI 3 "s_register_operand" "w")] | |
3176 | VRMLALDAVHAQ)) | |
3177 | ] | |
3178 | "TARGET_HAVE_MVE" | |
3179 | "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3" | |
3180 | [(set_attr "type" "mve_move") | |
3181 | ]) | |
3182 | ||
3183 | ;; | |
3184 | ;; [vabavq_s, vabavq_u]) | |
3185 | ;; | |
3186 | (define_insn "mve_vabavq_<supf><mode>" | |
3187 | [ | |
3188 | (set (match_operand:SI 0 "s_register_operand" "=r") | |
3189 | (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") | |
3190 | (match_operand:MVE_2 2 "s_register_operand" "w") | |
3191 | (match_operand:MVE_2 3 "s_register_operand" "w")] | |
3192 | VABAVQ)) | |
3193 | ] | |
3194 | "TARGET_HAVE_MVE" | |
3195 | "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3" | |
3196 | [(set_attr "type" "mve_move") | |
3197 | ]) | |
3198 | ||
3199 | ;; | |
3200 | ;; [vshlcq_u vshlcq_s] | |
3201 | ;; | |
3202 | (define_expand "mve_vshlcq_vec_<supf><mode>" | |
3203 | [(match_operand:MVE_2 0 "s_register_operand") | |
3204 | (match_operand:MVE_2 1 "s_register_operand") | |
3205 | (match_operand:SI 2 "s_register_operand") | |
3206 | (match_operand:SI 3 "mve_imm_32") | |
3207 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
3208 | "TARGET_HAVE_MVE" | |
3209 | { | |
3210 | rtx ignore_wb = gen_reg_rtx (SImode); | |
3211 | emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], | |
3212 | operands[2], operands[3])); | |
3213 | DONE; | |
3214 | }) | |
3215 | ||
3216 | (define_expand "mve_vshlcq_carry_<supf><mode>" | |
3217 | [(match_operand:SI 0 "s_register_operand") | |
3218 | (match_operand:MVE_2 1 "s_register_operand") | |
3219 | (match_operand:SI 2 "s_register_operand") | |
3220 | (match_operand:SI 3 "mve_imm_32") | |
3221 | (unspec:MVE_2 [(const_int 0)] VSHLCQ)] | |
3222 | "TARGET_HAVE_MVE" | |
3223 | { | |
3224 | rtx ignore_vec = gen_reg_rtx (<MODE>mode); | |
3225 | emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], | |
3226 | operands[2], operands[3])); | |
3227 | DONE; | |
3228 | }) | |
3229 | ||
3230 | (define_insn "mve_vshlcq_<supf><mode>" | |
3231 | [(set (match_operand:MVE_2 0 "s_register_operand" "=w") | |
3232 | (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") | |
3233 | (match_operand:SI 3 "s_register_operand" "1") | |
3234 | (match_operand:SI 4 "mve_imm_32" "Rf")] | |
3235 | VSHLCQ)) | |
3236 | (set (match_operand:SI 1 "s_register_operand" "=r") | |
3237 | (unspec:SI [(match_dup 2) | |
3238 | (match_dup 3) | |
3239 | (match_dup 4)] | |
3240 | VSHLCQ))] | |
3241 | "TARGET_HAVE_MVE" | |
3242 | "vshlc %q0, %1, %4") |