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[NDS32] Remove unused insn type: call.
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1/* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21/* ------------------------------------------------------------------------ */
22
23#define IN_TARGET_CODE 1
24
25#include "config.h"
26#include "system.h"
27#include "coretypes.h"
28#include "backend.h"
29#include "target.h"
30#include "rtl.h"
31#include "tree.h"
32#include "tree-pass.h"
33#include "stringpool.h"
34#include "attribs.h"
35#include "df.h"
36#include "memmodel.h"
37#include "tm_p.h"
38#include "optabs.h" /* For GEN_FCN. */
39#include "regs.h"
40#include "emit-rtl.h"
41#include "recog.h"
42#include "diagnostic-core.h"
43#include "stor-layout.h"
44#include "varasm.h"
45#include "calls.h"
46#include "output.h"
47#include "explow.h"
48#include "expr.h"
49#include "tm-constrs.h"
50#include "builtins.h"
51#include "cpplib.h"
52#include "context.h"
53
54/* This file should be included last. */
55#include "target-def.h"
56
57/* ------------------------------------------------------------------------ */
58
59/* This file is divided into five parts:
60
61 PART 1: Auxiliary static variable definitions and
62 target hook static variable definitions.
63
64 PART 2: Auxiliary static function definitions.
65
66 PART 3: Implement target hook stuff definitions.
67
68 PART 4: Implemet extern function definitions,
69 the prototype is in nds32-protos.h.
70
71 PART 5: Initialize target hook structure and definitions. */
72
73/* ------------------------------------------------------------------------ */
74
75/* PART 1: Auxiliary static variable definitions and
76 target hook static variable definitions. */
77
78/* Define intrinsic register names.
79 Please refer to nds32_intrinsic.h file, the index is corresponding to
80 'enum nds32_intrinsic_registers' data type values.
81 NOTE that the base value starting from 1024. */
82static const char * const nds32_intrinsic_register_names[] =
83{
84 "$CPU_VER",
85 "$ICM_CFG",
86 "$DCM_CFG",
87 "$MMU_CFG",
88 "$MSC_CFG",
89 "$MSC_CFG2",
90 "$CORE_ID",
91 "$FUCOP_EXIST",
92
93 "$PSW",
94 "$IPSW",
95 "$P_IPSW",
96 "$IVB",
97 "$EVA",
98 "$P_EVA",
99 "$ITYPE",
100 "$P_ITYPE",
101
102 "$MERR",
103 "$IPC",
104 "$P_IPC",
105 "$OIPC",
106 "$P_P0",
107 "$P_P1",
108
109 "$INT_MASK",
110 "$INT_MASK2",
111 "$INT_MASK3",
112 "$INT_PEND",
113 "$INT_PEND2",
114 "$INT_PEND3",
115 "$SP_USR",
116 "$SP_PRIV",
117 "$INT_PRI",
118 "$INT_PRI2",
119 "$INT_PRI3",
120 "$INT_PRI4",
121 "$INT_CTRL",
122 "$INT_TRIGGER",
123 "$INT_TRIGGER2",
124 "$INT_GPR_PUSH_DIS",
125
126 "$MMU_CTL",
127 "$L1_PPTB",
128 "$TLB_VPN",
129 "$TLB_DATA",
130 "$TLB_MISC",
131 "$VLPT_IDX",
132 "$ILMB",
133 "$DLMB",
134
135 "$CACHE_CTL",
136 "$HSMP_SADDR",
137 "$HSMP_EADDR",
138 "$SDZ_CTL",
139 "$N12MISC_CTL",
140 "$MISC_CTL",
141 "$ECC_MISC",
142
143 "$BPC0",
144 "$BPC1",
145 "$BPC2",
146 "$BPC3",
147 "$BPC4",
148 "$BPC5",
149 "$BPC6",
150 "$BPC7",
151
152 "$BPA0",
153 "$BPA1",
154 "$BPA2",
155 "$BPA3",
156 "$BPA4",
157 "$BPA5",
158 "$BPA6",
159 "$BPA7",
160
161 "$BPAM0",
162 "$BPAM1",
163 "$BPAM2",
164 "$BPAM3",
165 "$BPAM4",
166 "$BPAM5",
167 "$BPAM6",
168 "$BPAM7",
169
170 "$BPV0",
171 "$BPV1",
172 "$BPV2",
173 "$BPV3",
174 "$BPV4",
175 "$BPV5",
176 "$BPV6",
177 "$BPV7",
178
179 "$BPCID0",
180 "$BPCID1",
181 "$BPCID2",
182 "$BPCID3",
183 "$BPCID4",
184 "$BPCID5",
185 "$BPCID6",
186 "$BPCID7",
187
188 "$EDM_CFG",
189 "$EDMSW",
190 "$EDM_CTL",
191 "$EDM_DTR",
192 "$BPMTC",
193 "$DIMBR",
194
195 "$TECR0",
196 "$TECR1",
197 "$PFMC0",
198 "$PFMC1",
199 "$PFMC2",
200 "$PFM_CTL",
201 "$PFT_CTL",
202 "$HSP_CTL",
203 "$SP_BOUND",
204 "$SP_BOUND_PRIV",
205 "$SP_BASE",
206 "$SP_BASE_PRIV",
207 "$FUCOP_CTL",
208 "$PRUSR_ACC_CTL",
209
210 "$DMA_CFG",
211 "$DMA_GCSW",
212 "$DMA_CHNSEL",
213 "$DMA_ACT",
214 "$DMA_SETUP",
215 "$DMA_ISADDR",
216 "$DMA_ESADDR",
217 "$DMA_TCNT",
218 "$DMA_STATUS",
219 "$DMA_2DSET",
220 "$DMA_2DSCTL",
221 "$DMA_RCNT",
222 "$DMA_HSTATUS",
223
224 "$PC",
225 "$SP_USR1",
226 "$SP_USR2",
227 "$SP_USR3",
228 "$SP_PRIV1",
229 "$SP_PRIV2",
230 "$SP_PRIV3",
231 "$BG_REGION",
232 "$SFCR",
233 "$SIGN",
234 "$ISIGN",
235 "$P_ISIGN",
236 "$IFC_LP",
237 "$ITB"
238};
239
240
241/* Defining register allocation order for performance.
242 We want to allocate callee-saved registers after others.
243 It may be used by nds32_adjust_reg_alloc_order(). */
244static const int nds32_reg_alloc_order_for_speed[] =
245{
246 0, 1, 2, 3, 4, 5, 16, 17,
247 18, 19, 20, 21, 22, 23, 24, 25,
248 26, 27, 6, 7, 8, 9, 10, 11,
249 12, 13, 14, 15
250};
251
252/* Defining target-specific uses of __attribute__. */
253static const struct attribute_spec nds32_attribute_table[] =
254{
255 /* Syntax: { name, min_len, max_len, decl_required, type_required,
256 function_type_required, affects_type_identity, handler,
257 exclude } */
258
259 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
260 { "interrupt", 1, 64, false, false, false, false, NULL, NULL },
261 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */
262 { "exception", 1, 8, false, false, false, false, NULL, NULL },
263 /* Argument is user's interrupt numbers. The vector number is always 0. */
264 { "reset", 1, 1, false, false, false, false, NULL, NULL },
265
266 /* The attributes describing isr nested type. */
267 { "nested", 0, 0, false, false, false, false, NULL, NULL },
268 { "not_nested", 0, 0, false, false, false, false, NULL, NULL },
269 { "nested_ready", 0, 0, false, false, false, false, NULL, NULL },
270
271 /* The attributes describing isr register save scheme. */
272 { "save_all", 0, 0, false, false, false, false, NULL, NULL },
273 { "partial_save", 0, 0, false, false, false, false, NULL, NULL },
274
275 /* The attributes used by reset attribute. */
276 { "nmi", 1, 1, false, false, false, false, NULL, NULL },
277 { "warm", 1, 1, false, false, false, false, NULL, NULL },
278
279 /* The attribute telling no prologue/epilogue. */
280 { "naked", 0, 0, false, false, false, false, NULL, NULL },
281
282 /* The last attribute spec is set to be NULL. */
283 { NULL, 0, 0, false, false, false, false, NULL, NULL }
284};
285
286
287/* ------------------------------------------------------------------------ */
288
289/* PART 2: Auxiliary static function definitions. */
290
291/* Function to save and restore machine-specific function data. */
292static struct machine_function *
293nds32_init_machine_status (void)
294{
295 struct machine_function *machine;
296 machine = ggc_cleared_alloc<machine_function> ();
297
298 /* Initially assume this function needs prologue/epilogue. */
299 machine->naked_p = 0;
300
301 /* Initially assume this function does NOT use fp_as_gp optimization. */
302 machine->fp_as_gp_p = 0;
303
304 return machine;
305}
306
307/* Function to compute stack frame size and
308 store into cfun->machine structure. */
309static void
310nds32_compute_stack_frame (void)
311{
312 int r;
313 int block_size;
314 bool v3pushpop_p;
315
316 /* Because nds32_compute_stack_frame() will be called from different place,
317 everytime we enter this function, we have to assume this function
318 needs prologue/epilogue. */
319 cfun->machine->naked_p = 0;
320
321 /* Get variadic arguments size to prepare pretend arguments and
322 we will push them into stack at prologue by ourself. */
323 cfun->machine->va_args_size = crtl->args.pretend_args_size;
324 if (cfun->machine->va_args_size != 0)
325 {
326 cfun->machine->va_args_first_regno
327 = NDS32_GPR_ARG_FIRST_REGNUM
328 + NDS32_MAX_GPR_REGS_FOR_ARGS
329 - (crtl->args.pretend_args_size / UNITS_PER_WORD);
330 cfun->machine->va_args_last_regno
331 = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1;
332 }
333 else
334 {
335 cfun->machine->va_args_first_regno = SP_REGNUM;
336 cfun->machine->va_args_last_regno = SP_REGNUM;
337 }
338
339 /* Important: We need to make sure that varargs area is 8-byte alignment. */
340 block_size = cfun->machine->va_args_size;
341 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
342 {
343 cfun->machine->va_args_area_padding_bytes
344 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size;
345 }
346
347 /* Get local variables, incoming variables, and temporary variables size.
348 Note that we need to make sure it is 8-byte alignment because
349 there may be no padding bytes if we are using LRA. */
350 cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ());
351
352 /* Get outgoing arguments size. */
353 cfun->machine->out_args_size = crtl->outgoing_args_size;
354
355 /* If $fp value is required to be saved on stack, it needs 4 bytes space.
356 Check whether $fp is ever live. */
357 cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0;
358
359 /* If $gp value is required to be saved on stack, it needs 4 bytes space.
360 Check whether we are using PIC code genration. */
361 cfun->machine->gp_size = (flag_pic) ? 4 : 0;
362
363 /* If $lp value is required to be saved on stack, it needs 4 bytes space.
364 Check whether $lp is ever live. */
365 cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0;
366
367 /* Initially there is no padding bytes. */
368 cfun->machine->callee_saved_area_gpr_padding_bytes = 0;
369
370 /* Calculate the bytes of saving callee-saved registers on stack. */
371 cfun->machine->callee_saved_gpr_regs_size = 0;
372 cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM;
373 cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM;
374 cfun->machine->callee_saved_fpr_regs_size = 0;
375 cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM;
376 cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM;
377
378 /* Currently, there is no need to check $r28~$r31
379 because we will save them in another way. */
380 for (r = 0; r < 28; r++)
381 {
382 if (NDS32_REQUIRED_CALLEE_SAVED_P (r))
383 {
384 /* Mark the first required callee-saved register
385 (only need to set it once).
386 If first regno == SP_REGNUM, we can tell that
387 it is the first time to be here. */
388 if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM)
389 cfun->machine->callee_saved_first_gpr_regno = r;
390 /* Mark the last required callee-saved register. */
391 cfun->machine->callee_saved_last_gpr_regno = r;
392 }
393 }
394
395 /* Recording fpu callee-saved register. */
396 if (TARGET_HARD_FLOAT)
397 {
398 for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++)
399 {
400 if (NDS32_REQUIRED_CALLEE_SAVED_P (r))
401 {
402 /* Mark the first required callee-saved register. */
403 if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM)
404 {
405 /* Make first callee-saved number is even,
406 bacause we use doubleword access, and this way
407 promise 8-byte alignemt. */
408 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r))
409 cfun->machine->callee_saved_first_fpr_regno = r - 1;
410 else
411 cfun->machine->callee_saved_first_fpr_regno = r;
412 }
413 cfun->machine->callee_saved_last_fpr_regno = r;
414 }
415 }
416
417 /* Make last callee-saved register number is odd,
418 we hope callee-saved register is even. */
419 int last_fpr = cfun->machine->callee_saved_last_fpr_regno;
420 if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr))
421 cfun->machine->callee_saved_last_fpr_regno++;
422 }
423
424 /* Check if this function can omit prologue/epilogue code fragment.
425 If there is 'naked' attribute in this function,
426 we can set 'naked_p' flag to indicate that
427 we do not have to generate prologue/epilogue.
428 Or, if all the following conditions succeed,
429 we can set this function 'naked_p' as well:
430 condition 1: first_regno == last_regno == SP_REGNUM,
431 which means we do not have to save
432 any callee-saved registers.
433 condition 2: Both $lp and $fp are NOT live in this function,
434 which means we do not need to save them and there
435 is no outgoing size.
436 condition 3: There is no local_size, which means
437 we do not need to adjust $sp. */
438 if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
439 || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM
440 && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM
441 && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM
442 && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM
443 && !df_regs_ever_live_p (FP_REGNUM)
444 && !df_regs_ever_live_p (LP_REGNUM)
445 && cfun->machine->local_size == 0))
446 {
447 /* Set this function 'naked_p' and other functions can check this flag.
448 Note that in nds32 port, the 'naked_p = 1' JUST means there is no
449 callee-saved, local size, and outgoing size.
450 The varargs space and ret instruction may still present in
451 the prologue/epilogue expanding. */
452 cfun->machine->naked_p = 1;
453
454 /* No need to save $fp, $gp, and $lp.
455 We should set these value to be zero
456 so that nds32_initial_elimination_offset() can work properly. */
457 cfun->machine->fp_size = 0;
458 cfun->machine->gp_size = 0;
459 cfun->machine->lp_size = 0;
460
461 /* If stack usage computation is required,
462 we need to provide the static stack size. */
463 if (flag_stack_usage_info)
464 current_function_static_stack_size = 0;
465
466 /* No need to do following adjustment, return immediately. */
467 return;
468 }
469
470 v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P;
471
472 /* Adjustment for v3push instructions:
473 If we are using v3push (push25/pop25) instructions,
474 we need to make sure Rb is $r6 and Re is
475 located on $r6, $r8, $r10, or $r14.
476 Some results above will be discarded and recomputed.
477 Note that it is only available under V3/V3M ISA and we
478 DO NOT setup following stuff for isr or variadic function. */
479 if (v3pushpop_p)
480 {
481 /* Recompute:
482 cfun->machine->fp_size
483 cfun->machine->gp_size
484 cfun->machine->lp_size
485 cfun->machine->callee_saved_first_gpr_regno
486 cfun->machine->callee_saved_last_gpr_regno */
487
488 /* For v3push instructions, $fp, $gp, and $lp are always saved. */
489 cfun->machine->fp_size = 4;
490 cfun->machine->gp_size = 4;
491 cfun->machine->lp_size = 4;
492
493 /* Remember to set Rb = $r6. */
494 cfun->machine->callee_saved_first_gpr_regno = 6;
495
496 if (cfun->machine->callee_saved_last_gpr_regno <= 6)
497 {
498 /* Re = $r6 */
499 cfun->machine->callee_saved_last_gpr_regno = 6;
500 }
501 else if (cfun->machine->callee_saved_last_gpr_regno <= 8)
502 {
503 /* Re = $r8 */
504 cfun->machine->callee_saved_last_gpr_regno = 8;
505 }
506 else if (cfun->machine->callee_saved_last_gpr_regno <= 10)
507 {
508 /* Re = $r10 */
509 cfun->machine->callee_saved_last_gpr_regno = 10;
510 }
511 else if (cfun->machine->callee_saved_last_gpr_regno <= 14)
512 {
513 /* Re = $r14 */
514 cfun->machine->callee_saved_last_gpr_regno = 14;
515 }
516 else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM)
517 {
518 /* If last_regno is SP_REGNUM, which means
519 it is never changed, so set it to Re = $r6. */
520 cfun->machine->callee_saved_last_gpr_regno = 6;
521 }
522 else
523 {
524 /* The program flow should not go here. */
525 gcc_unreachable ();
526 }
527 }
528
529 int sp_adjust = cfun->machine->local_size
530 + cfun->machine->out_args_size
531 + cfun->machine->callee_saved_area_gpr_padding_bytes
532 + cfun->machine->callee_saved_fpr_regs_size;
533
534 if (!v3pushpop_p
535 && sp_adjust == 0
536 && !frame_pointer_needed)
537 {
538 block_size = cfun->machine->fp_size
539 + cfun->machine->gp_size
540 + cfun->machine->lp_size
541 + (4 * (cfun->machine->callee_saved_last_gpr_regno
542 - cfun->machine->callee_saved_first_gpr_regno
543 + 1));
544
545 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
546 {
547 /* $r14 is last callee save register. */
548 if (cfun->machine->callee_saved_last_gpr_regno
549 < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM)
550 {
551 cfun->machine->callee_saved_last_gpr_regno++;
552 }
553 else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM)
554 {
555 cfun->machine->callee_saved_first_gpr_regno
556 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM;
557 cfun->machine->callee_saved_last_gpr_regno
558 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM;
559 }
560 }
561 }
562
563 /* We have correctly set callee_saved_first_gpr_regno
564 and callee_saved_last_gpr_regno.
565 Initially, the callee_saved_gpr_regs_size is supposed to be 0.
566 As long as callee_saved_last_gpr_regno is not SP_REGNUM,
567 we can update callee_saved_gpr_regs_size with new size. */
568 if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM)
569 {
570 /* Compute pushed size of callee-saved registers. */
571 cfun->machine->callee_saved_gpr_regs_size
572 = 4 * (cfun->machine->callee_saved_last_gpr_regno
573 - cfun->machine->callee_saved_first_gpr_regno
574 + 1);
575 }
576
577 if (TARGET_HARD_FLOAT)
578 {
579 /* Compute size of callee svaed floating-point registers. */
580 if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM)
581 {
582 cfun->machine->callee_saved_fpr_regs_size
583 = 4 * (cfun->machine->callee_saved_last_fpr_regno
584 - cfun->machine->callee_saved_first_fpr_regno
585 + 1);
586 }
587 }
588
589 /* Important: We need to make sure that
590 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size)
591 is 8-byte alignment.
592 If it is not, calculate the padding bytes. */
593 block_size = cfun->machine->fp_size
594 + cfun->machine->gp_size
595 + cfun->machine->lp_size
596 + cfun->machine->callee_saved_gpr_regs_size;
597 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
598 {
599 cfun->machine->callee_saved_area_gpr_padding_bytes
600 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size;
601 }
602
603 /* If stack usage computation is required,
604 we need to provide the static stack size. */
605 if (flag_stack_usage_info)
606 {
607 current_function_static_stack_size
608 = NDS32_ROUND_UP_DOUBLE_WORD (block_size)
609 + cfun->machine->local_size
610 + cfun->machine->out_args_size;
611 }
612}
613
614/* Function to create a parallel rtx pattern
615 which presents stack push multiple behavior.
616 The overall concept are:
617 "push registers to memory",
618 "adjust stack pointer". */
619static void
620nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re,
621 bool save_fp_p, bool save_gp_p, bool save_lp_p,
622 bool vaarg_p)
623{
624 unsigned regno;
625 int extra_count;
626 int num_use_regs;
627 int par_index;
628 int offset;
629
630 rtx reg;
631 rtx mem;
632 rtx push_rtx;
633 rtx adjust_sp_rtx;
634 rtx parallel_insn;
635 rtx dwarf;
636
637 /* We need to provide a customized rtx which contains
638 necessary information for data analysis,
639 so we create a parallel rtx like this:
640 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
641 (reg:SI Rb))
642 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
643 (reg:SI Rb+1))
644 ...
645 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
646 (reg:SI Re))
647 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
648 (reg:SI FP_REGNUM))
649 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
650 (reg:SI GP_REGNUM))
651 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
652 (reg:SI LP_REGNUM))
653 (set (reg:SI SP_REGNUM)
654 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
655
656 /* Calculate the number of registers that will be pushed. */
657 extra_count = 0;
658 if (save_fp_p)
659 extra_count++;
660 if (save_gp_p)
661 extra_count++;
662 if (save_lp_p)
663 extra_count++;
664 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
665 if (Rb == SP_REGNUM && Re == SP_REGNUM)
666 num_use_regs = extra_count;
667 else
668 num_use_regs = Re - Rb + 1 + extra_count;
669
670 /* In addition to used registers,
671 we need one more space for (set sp sp-x) rtx. */
672 parallel_insn = gen_rtx_PARALLEL (VOIDmode,
673 rtvec_alloc (num_use_regs + 1));
674 par_index = 0;
675
676 /* Initialize offset and start to create push behavior. */
677 offset = -(num_use_regs * 4);
678
679 /* Create (set mem regX) from Rb, Rb+1 up to Re. */
680 for (regno = Rb; regno <= Re; regno++)
681 {
682 /* Rb and Re may be SP_REGNUM.
683 We need to break this loop immediately. */
684 if (regno == SP_REGNUM)
685 break;
686
687 reg = gen_rtx_REG (SImode, regno);
688 mem = gen_frame_mem (SImode, plus_constant (Pmode,
689 stack_pointer_rtx,
690 offset));
691 push_rtx = gen_rtx_SET (mem, reg);
692 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
693 RTX_FRAME_RELATED_P (push_rtx) = 1;
694 offset = offset + 4;
695 par_index++;
696 }
697
698 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
699 if (save_fp_p)
700 {
701 reg = gen_rtx_REG (SImode, FP_REGNUM);
702 mem = gen_frame_mem (SImode, plus_constant (Pmode,
703 stack_pointer_rtx,
704 offset));
705 push_rtx = gen_rtx_SET (mem, reg);
706 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
707 RTX_FRAME_RELATED_P (push_rtx) = 1;
708 offset = offset + 4;
709 par_index++;
710 }
711 if (save_gp_p)
712 {
713 reg = gen_rtx_REG (SImode, GP_REGNUM);
714 mem = gen_frame_mem (SImode, plus_constant (Pmode,
715 stack_pointer_rtx,
716 offset));
717 push_rtx = gen_rtx_SET (mem, reg);
718 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
719 RTX_FRAME_RELATED_P (push_rtx) = 1;
720 offset = offset + 4;
721 par_index++;
722 }
723 if (save_lp_p)
724 {
725 reg = gen_rtx_REG (SImode, LP_REGNUM);
726 mem = gen_frame_mem (SImode, plus_constant (Pmode,
727 stack_pointer_rtx,
728 offset));
729 push_rtx = gen_rtx_SET (mem, reg);
730 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
731 RTX_FRAME_RELATED_P (push_rtx) = 1;
732 offset = offset + 4;
733 par_index++;
734 }
735
736 /* Create (set sp sp-x). */
737
738 /* We need to re-calculate the offset value again for adjustment. */
739 offset = -(num_use_regs * 4);
740 adjust_sp_rtx
741 = gen_rtx_SET (stack_pointer_rtx,
742 plus_constant (Pmode, stack_pointer_rtx, offset));
743 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
744 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
745
746 parallel_insn = emit_insn (parallel_insn);
747
748 /* The insn rtx 'parallel_insn' will change frame layout.
749 We need to use RTX_FRAME_RELATED_P so that GCC is able to
750 generate CFI (Call Frame Information) stuff. */
751 RTX_FRAME_RELATED_P (parallel_insn) = 1;
752
753 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG
754 since we will not restore those register at epilogue. */
755 if (vaarg_p)
756 {
757 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA,
758 copy_rtx (adjust_sp_rtx), NULL_RTX);
759 REG_NOTES (parallel_insn) = dwarf;
760 }
761}
762
763/* Function to create a parallel rtx pattern
764 which presents stack pop multiple behavior.
765 The overall concept are:
766 "pop registers from memory",
767 "adjust stack pointer". */
768static void
769nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re,
770 bool save_fp_p, bool save_gp_p, bool save_lp_p)
771{
772 unsigned regno;
773 int extra_count;
774 int num_use_regs;
775 int par_index;
776 int offset;
777
778 rtx reg;
779 rtx mem;
780 rtx pop_rtx;
781 rtx adjust_sp_rtx;
782 rtx parallel_insn;
783 rtx dwarf = NULL_RTX;
784
785 /* We need to provide a customized rtx which contains
786 necessary information for data analysis,
787 so we create a parallel rtx like this:
788 (parallel [(set (reg:SI Rb)
789 (mem (reg:SI SP_REGNUM)))
790 (set (reg:SI Rb+1)
791 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
792 ...
793 (set (reg:SI Re)
794 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
795 (set (reg:SI FP_REGNUM)
796 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
797 (set (reg:SI GP_REGNUM)
798 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
799 (set (reg:SI LP_REGNUM)
800 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
801 (set (reg:SI SP_REGNUM)
802 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
803
804 /* Calculate the number of registers that will be poped. */
805 extra_count = 0;
806 if (save_fp_p)
807 extra_count++;
808 if (save_gp_p)
809 extra_count++;
810 if (save_lp_p)
811 extra_count++;
812 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
813 if (Rb == SP_REGNUM && Re == SP_REGNUM)
814 num_use_regs = extra_count;
815 else
816 num_use_regs = Re - Rb + 1 + extra_count;
817
818 /* In addition to used registers,
819 we need one more space for (set sp sp+x) rtx. */
820 parallel_insn = gen_rtx_PARALLEL (VOIDmode,
821 rtvec_alloc (num_use_regs + 1));
822 par_index = 0;
823
824 /* Initialize offset and start to create pop behavior. */
825 offset = 0;
826
827 /* Create (set regX mem) from Rb, Rb+1 up to Re. */
828 for (regno = Rb; regno <= Re; regno++)
829 {
830 /* Rb and Re may be SP_REGNUM.
831 We need to break this loop immediately. */
832 if (regno == SP_REGNUM)
833 break;
834
835 reg = gen_rtx_REG (SImode, regno);
836 mem = gen_frame_mem (SImode, plus_constant (Pmode,
837 stack_pointer_rtx,
838 offset));
839 pop_rtx = gen_rtx_SET (reg, mem);
840 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
841 RTX_FRAME_RELATED_P (pop_rtx) = 1;
842 offset = offset + 4;
843 par_index++;
844
845 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
846 }
847
848 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
849 if (save_fp_p)
850 {
851 reg = gen_rtx_REG (SImode, FP_REGNUM);
852 mem = gen_frame_mem (SImode, plus_constant (Pmode,
853 stack_pointer_rtx,
854 offset));
855 pop_rtx = gen_rtx_SET (reg, mem);
856 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
857 RTX_FRAME_RELATED_P (pop_rtx) = 1;
858 offset = offset + 4;
859 par_index++;
860
861 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
862 }
863 if (save_gp_p)
864 {
865 reg = gen_rtx_REG (SImode, GP_REGNUM);
866 mem = gen_frame_mem (SImode, plus_constant (Pmode,
867 stack_pointer_rtx,
868 offset));
869 pop_rtx = gen_rtx_SET (reg, mem);
870 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
871 RTX_FRAME_RELATED_P (pop_rtx) = 1;
872 offset = offset + 4;
873 par_index++;
874
875 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
876 }
877 if (save_lp_p)
878 {
879 reg = gen_rtx_REG (SImode, LP_REGNUM);
880 mem = gen_frame_mem (SImode, plus_constant (Pmode,
881 stack_pointer_rtx,
882 offset));
883 pop_rtx = gen_rtx_SET (reg, mem);
884 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
885 RTX_FRAME_RELATED_P (pop_rtx) = 1;
886 offset = offset + 4;
887 par_index++;
888
889 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
890 }
891
892 /* Create (set sp sp+x). */
893
894 /* The offset value is already in place. No need to re-calculate it. */
895 adjust_sp_rtx
896 = gen_rtx_SET (stack_pointer_rtx,
897 plus_constant (Pmode, stack_pointer_rtx, offset));
898 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
899
900 /* Tell gcc we adjust SP in this insn. */
901 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf);
902
903 parallel_insn = emit_insn (parallel_insn);
904
905 /* The insn rtx 'parallel_insn' will change frame layout.
906 We need to use RTX_FRAME_RELATED_P so that GCC is able to
907 generate CFI (Call Frame Information) stuff. */
908 RTX_FRAME_RELATED_P (parallel_insn) = 1;
909
910 /* Add CFI info by manual. */
911 REG_NOTES (parallel_insn) = dwarf;
912}
913
914/* Function to create a parallel rtx pattern
915 which presents stack v3push behavior.
916 The overall concept are:
917 "push registers to memory",
918 "adjust stack pointer". */
919static void
920nds32_emit_stack_v3push (unsigned Rb,
921 unsigned Re,
922 unsigned imm8u)
923{
924 unsigned regno;
925 int num_use_regs;
926 int par_index;
927 int offset;
928
929 rtx reg;
930 rtx mem;
931 rtx push_rtx;
932 rtx adjust_sp_rtx;
933 rtx parallel_insn;
934
935 /* We need to provide a customized rtx which contains
936 necessary information for data analysis,
937 so we create a parallel rtx like this:
938 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
939 (reg:SI Rb))
940 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
941 (reg:SI Rb+1))
942 ...
943 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
944 (reg:SI Re))
945 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
946 (reg:SI FP_REGNUM))
947 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
948 (reg:SI GP_REGNUM))
949 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
950 (reg:SI LP_REGNUM))
951 (set (reg:SI SP_REGNUM)
952 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
953
954 /* Calculate the number of registers that will be pushed.
955 Since $fp, $gp, and $lp is always pushed with v3push instruction,
956 we need to count these three registers.
957 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
958 So there is no need to worry about Rb=Re=SP_REGNUM case. */
959 num_use_regs = Re - Rb + 1 + 3;
960
961 /* In addition to used registers,
962 we need one more space for (set sp sp-x-imm8u) rtx. */
963 parallel_insn = gen_rtx_PARALLEL (VOIDmode,
964 rtvec_alloc (num_use_regs + 1));
965 par_index = 0;
966
967 /* Initialize offset and start to create push behavior. */
968 offset = -(num_use_regs * 4);
969
970 /* Create (set mem regX) from Rb, Rb+1 up to Re.
971 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
972 So there is no need to worry about Rb=Re=SP_REGNUM case. */
973 for (regno = Rb; regno <= Re; regno++)
974 {
975 reg = gen_rtx_REG (SImode, regno);
976 mem = gen_frame_mem (SImode, plus_constant (Pmode,
977 stack_pointer_rtx,
978 offset));
979 push_rtx = gen_rtx_SET (mem, reg);
980 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
981 RTX_FRAME_RELATED_P (push_rtx) = 1;
982 offset = offset + 4;
983 par_index++;
984 }
985
986 /* Create (set mem fp). */
987 reg = gen_rtx_REG (SImode, FP_REGNUM);
988 mem = gen_frame_mem (SImode, plus_constant (Pmode,
989 stack_pointer_rtx,
990 offset));
991 push_rtx = gen_rtx_SET (mem, reg);
992 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
993 RTX_FRAME_RELATED_P (push_rtx) = 1;
994 offset = offset + 4;
995 par_index++;
996 /* Create (set mem gp). */
997 reg = gen_rtx_REG (SImode, GP_REGNUM);
998 mem = gen_frame_mem (SImode, plus_constant (Pmode,
999 stack_pointer_rtx,
1000 offset));
1001 push_rtx = gen_rtx_SET (mem, reg);
1002 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
1003 RTX_FRAME_RELATED_P (push_rtx) = 1;
1004 offset = offset + 4;
1005 par_index++;
1006 /* Create (set mem lp). */
1007 reg = gen_rtx_REG (SImode, LP_REGNUM);
1008 mem = gen_frame_mem (SImode, plus_constant (Pmode,
1009 stack_pointer_rtx,
1010 offset));
1011 push_rtx = gen_rtx_SET (mem, reg);
1012 XVECEXP (parallel_insn, 0, par_index) = push_rtx;
1013 RTX_FRAME_RELATED_P (push_rtx) = 1;
1014 offset = offset + 4;
1015 par_index++;
1016
1017 /* Create (set sp sp-x-imm8u). */
1018
1019 /* We need to re-calculate the offset value again for adjustment. */
1020 offset = -(num_use_regs * 4);
1021 adjust_sp_rtx
1022 = gen_rtx_SET (stack_pointer_rtx,
1023 plus_constant (Pmode,
1024 stack_pointer_rtx,
1025 offset - imm8u));
1026 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
1027 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
1028
1029 parallel_insn = emit_insn (parallel_insn);
1030
1031 /* The insn rtx 'parallel_insn' will change frame layout.
1032 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1033 generate CFI (Call Frame Information) stuff. */
1034 RTX_FRAME_RELATED_P (parallel_insn) = 1;
1035}
1036
1037/* Function to create a parallel rtx pattern
1038 which presents stack v3pop behavior.
1039 The overall concept are:
1040 "pop registers from memory",
1041 "adjust stack pointer". */
1042static void
1043nds32_emit_stack_v3pop (unsigned Rb,
1044 unsigned Re,
1045 unsigned imm8u)
1046{
1047 unsigned regno;
1048 int num_use_regs;
1049 int par_index;
1050 int offset;
1051
1052 rtx reg;
1053 rtx mem;
1054 rtx pop_rtx;
1055 rtx adjust_sp_rtx;
1056 rtx parallel_insn;
1057 rtx dwarf = NULL_RTX;
1058
1059 /* We need to provide a customized rtx which contains
1060 necessary information for data analysis,
1061 so we create a parallel rtx like this:
1062 (parallel [(set (reg:SI Rb)
1063 (mem (reg:SI SP_REGNUM)))
1064 (set (reg:SI Rb+1)
1065 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
1066 ...
1067 (set (reg:SI Re)
1068 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
1069 (set (reg:SI FP_REGNUM)
1070 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
1071 (set (reg:SI GP_REGNUM)
1072 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
1073 (set (reg:SI LP_REGNUM)
1074 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
1075 (set (reg:SI SP_REGNUM)
1076 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
1077
1078 /* Calculate the number of registers that will be poped.
1079 Since $fp, $gp, and $lp is always poped with v3pop instruction,
1080 we need to count these three registers.
1081 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1082 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1083 num_use_regs = Re - Rb + 1 + 3;
1084
1085 /* In addition to used registers,
1086 we need one more space for (set sp sp+x+imm8u) rtx. */
1087 parallel_insn = gen_rtx_PARALLEL (VOIDmode,
1088 rtvec_alloc (num_use_regs + 1));
1089 par_index = 0;
1090
1091 /* Initialize offset and start to create pop behavior. */
1092 offset = 0;
1093
1094 /* Create (set regX mem) from Rb, Rb+1 up to Re.
1095 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1096 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1097 for (regno = Rb; regno <= Re; regno++)
1098 {
1099 reg = gen_rtx_REG (SImode, regno);
1100 mem = gen_frame_mem (SImode, plus_constant (Pmode,
1101 stack_pointer_rtx,
1102 offset));
1103 pop_rtx = gen_rtx_SET (reg, mem);
1104 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
1105 RTX_FRAME_RELATED_P (pop_rtx) = 1;
1106 offset = offset + 4;
1107 par_index++;
1108
1109 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
1110 }
1111
1112 /* Create (set fp mem). */
1113 reg = gen_rtx_REG (SImode, FP_REGNUM);
1114 mem = gen_frame_mem (SImode, plus_constant (Pmode,
1115 stack_pointer_rtx,
1116 offset));
1117 pop_rtx = gen_rtx_SET (reg, mem);
1118 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
1119 RTX_FRAME_RELATED_P (pop_rtx) = 1;
1120 offset = offset + 4;
1121 par_index++;
1122 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
1123
1124 /* Create (set gp mem). */
1125 reg = gen_rtx_REG (SImode, GP_REGNUM);
1126 mem = gen_frame_mem (SImode, plus_constant (Pmode,
1127 stack_pointer_rtx,
1128 offset));
1129 pop_rtx = gen_rtx_SET (reg, mem);
1130 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
1131 RTX_FRAME_RELATED_P (pop_rtx) = 1;
1132 offset = offset + 4;
1133 par_index++;
1134 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
1135
1136 /* Create (set lp mem ). */
1137 reg = gen_rtx_REG (SImode, LP_REGNUM);
1138 mem = gen_frame_mem (SImode, plus_constant (Pmode,
1139 stack_pointer_rtx,
1140 offset));
1141 pop_rtx = gen_rtx_SET (reg, mem);
1142 XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
1143 RTX_FRAME_RELATED_P (pop_rtx) = 1;
1144 offset = offset + 4;
1145 par_index++;
1146 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
1147
1148 /* Create (set sp sp+x+imm8u). */
1149
1150 /* The offset value is already in place. No need to re-calculate it. */
1151 adjust_sp_rtx
1152 = gen_rtx_SET (stack_pointer_rtx,
1153 plus_constant (Pmode,
1154 stack_pointer_rtx,
1155 offset + imm8u));
1156 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
1157
1158 if (frame_pointer_needed)
1159 {
1160 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp)
1161 (const_int 0))
1162 mean reset frame pointer to $sp and reset to offset 0. */
1163 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
1164 const0_rtx);
1165 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
1166 }
1167 else
1168 {
1169 /* Tell gcc we adjust SP in this insn. */
1170 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA,
1171 copy_rtx (adjust_sp_rtx), dwarf);
1172 }
1173
1174 parallel_insn = emit_insn (parallel_insn);
1175
1176 /* The insn rtx 'parallel_insn' will change frame layout.
1177 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1178 generate CFI (Call Frame Information) stuff. */
1179 RTX_FRAME_RELATED_P (parallel_insn) = 1;
1180
1181 /* Add CFI info by manual. */
1182 REG_NOTES (parallel_insn) = dwarf;
1183}
1184
1185/* Function that may creates more instructions
1186 for large value on adjusting stack pointer.
1187
1188 In nds32 target, 'addi' can be used for stack pointer
1189 adjustment in prologue/epilogue stage.
1190 However, sometimes there are too many local variables so that
1191 the adjustment value is not able to be fit in the 'addi' instruction.
1192 One solution is to move value into a register
1193 and then use 'add' instruction.
1194 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */
1195static void
1196nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value)
1197{
1198 rtx tmp_reg;
1199 rtx frame_adjust_insn;
1200 rtx adjust_value_rtx = GEN_INT (adjust_value);
1201
1202 if (adjust_value == 0)
1203 return;
1204
1205 if (!satisfies_constraint_Is15 (adjust_value_rtx))
1206 {
1207 /* The value is not able to fit in single addi instruction.
1208 Create more instructions of moving value into a register
1209 and then add stack pointer with it. */
1210
1211 /* $r15 is going to be temporary register to hold the value. */
1212 tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
1213
1214 /* Create one more instruction to move value
1215 into the temporary register. */
1216 emit_move_insn (tmp_reg, adjust_value_rtx);
1217
1218 /* Create new 'add' rtx. */
1219 frame_adjust_insn = gen_addsi3 (to_reg,
1220 from_reg,
1221 tmp_reg);
1222 /* Emit rtx into insn list and receive its transformed insn rtx. */
1223 frame_adjust_insn = emit_insn (frame_adjust_insn);
1224
1225 /* Because (tmp_reg <- full_value) may be split into two
1226 rtl patterns, we can not set its RTX_FRAME_RELATED_P.
1227 We need to construct another (sp <- sp + full_value)
1228 and then insert it into sp_adjust_insn's reg note to
1229 represent a frame related expression.
1230 GCC knows how to refer it and output debug information. */
1231
1232 rtx plus_rtx;
1233 rtx set_rtx;
1234
1235 plus_rtx = plus_constant (Pmode, from_reg, adjust_value);
1236 set_rtx = gen_rtx_SET (to_reg, plus_rtx);
1237 add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx);
1238 }
1239 else
1240 {
1241 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
1242 frame_adjust_insn = gen_addsi3 (to_reg,
1243 from_reg,
1244 adjust_value_rtx);
1245 /* Emit rtx into instructions list and receive INSN rtx form. */
1246 frame_adjust_insn = emit_insn (frame_adjust_insn);
1247 }
1248
1249 /* The insn rtx 'sp_adjust_insn' will change frame layout.
1250 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1251 generate CFI (Call Frame Information) stuff. */
1252 RTX_FRAME_RELATED_P (frame_adjust_insn) = 1;
1253}
1254
1255/* Return true if MODE/TYPE need double word alignment. */
1256static bool
1257nds32_needs_double_word_align (machine_mode mode, const_tree type)
1258{
1259 unsigned int align;
1260
1261 /* Pick up the alignment according to the mode or type. */
1262 align = NDS32_MODE_TYPE_ALIGN (mode, type);
1263
1264 return (align > PARM_BOUNDARY);
1265}
1266
1267/* Return true if FUNC is a naked function. */
1268static bool
1269nds32_naked_function_p (tree func)
1270{
1271 tree t;
1272
1273 if (TREE_CODE (func) != FUNCTION_DECL)
1274 abort ();
1275
1276 t = lookup_attribute ("naked", DECL_ATTRIBUTES (func));
1277
1278 return (t != NULL_TREE);
1279}
1280
1281/* Function that check if 'X' is a valid address register.
1282 The variable 'STRICT' is very important to
1283 make decision for register number.
1284
1285 STRICT : true
1286 => We are in reload pass or after reload pass.
1287 The register number should be strictly limited in general registers.
1288
1289 STRICT : false
1290 => Before reload pass, we are free to use any register number. */
1291static bool
1292nds32_address_register_rtx_p (rtx x, bool strict)
1293{
1294 int regno;
1295
1296 if (GET_CODE (x) != REG)
1297 return false;
1298
1299 regno = REGNO (x);
1300
1301 if (strict)
1302 return REGNO_OK_FOR_BASE_P (regno);
1303 else
1304 return true;
1305}
1306
1307/* Function that check if 'INDEX' is valid to be a index rtx for address.
1308
1309 OUTER_MODE : Machine mode of outer address rtx.
1310 INDEX : Check if this rtx is valid to be a index for address.
1311 STRICT : If it is true, we are in reload pass or after reload pass. */
1312static bool
1313nds32_legitimate_index_p (machine_mode outer_mode,
1314 rtx index,
1315 bool strict)
1316{
1317 int regno;
1318 rtx op0;
1319 rtx op1;
1320
1321 switch (GET_CODE (index))
1322 {
1323 case REG:
1324 regno = REGNO (index);
1325 /* If we are in reload pass or after reload pass,
1326 we need to limit it to general register. */
1327 if (strict)
1328 return REGNO_OK_FOR_INDEX_P (regno);
1329 else
1330 return true;
1331
1332 case CONST_INT:
1333 /* The alignment of the integer value is determined by 'outer_mode'. */
1334 switch (GET_MODE_SIZE (outer_mode))
1335 {
1336 case 1:
1337 /* Further check if the value is legal for the 'outer_mode'. */
1338 if (satisfies_constraint_Is15 (index))
1339 return true;
1340 break;
1341
1342 case 2:
1343 /* Further check if the value is legal for the 'outer_mode'. */
1344 if (satisfies_constraint_Is16 (index))
1345 {
1346 /* Make sure address is half word alignment. */
1347 if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index)))
1348 return true;
1349 }
1350 break;
1351
1352 case 4:
1353 /* Further check if the value is legal for the 'outer_mode'. */
1354 if (satisfies_constraint_Is17 (index))
1355 {
1356 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
1357 {
1358 if (!satisfies_constraint_Is14 (index))
1359 return false;
1360 }
1361
1362 /* Make sure address is word alignment. */
1363 if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
1364 return true;
1365 }
1366 break;
1367
1368 case 8:
1369 if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4,
1370 SImode)))
1371 {
1372 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
1373 {
1374 if (!satisfies_constraint_Is14 (index))
1375 return false;
1376 }
1377
1378 /* Make sure address is word alignment.
1379 Currently we do not have 64-bit load/store yet,
1380 so we will use two 32-bit load/store instructions to do
1381 memory access and they are single word alignment. */
1382 if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
1383 return true;
1384 }
1385 break;
1386
1387 default:
1388 return false;
1389 }
1390
1391 return false;
1392
1393 case MULT:
1394 op0 = XEXP (index, 0);
1395 op1 = XEXP (index, 1);
1396
1397 if (REG_P (op0) && CONST_INT_P (op1))
1398 {
1399 int multiplier;
1400 multiplier = INTVAL (op1);
1401
1402 /* We only allow (mult reg const_int_1), (mult reg const_int_2),
1403 (mult reg const_int_4) or (mult reg const_int_8). */
1404 if (multiplier != 1 && multiplier != 2
1405 && multiplier != 4 && multiplier != 8)
1406 return false;
1407
1408 regno = REGNO (op0);
1409 /* Limit it in general registers if we are
1410 in reload pass or after reload pass. */
1411 if(strict)
1412 return REGNO_OK_FOR_INDEX_P (regno);
1413 else
1414 return true;
1415 }
1416
1417 return false;
1418
1419 case ASHIFT:
1420 op0 = XEXP (index, 0);
1421 op1 = XEXP (index, 1);
1422
1423 if (REG_P (op0) && CONST_INT_P (op1))
1424 {
1425 int sv;
1426 /* op1 is already the sv value for use to do left shift. */
1427 sv = INTVAL (op1);
1428
1429 /* We only allow (ashift reg const_int_0)
1430 or (ashift reg const_int_1) or (ashift reg const_int_2) or
1431 (ashift reg const_int_3). */
1432 if (sv != 0 && sv != 1 && sv !=2 && sv != 3)
1433 return false;
1434
1435 regno = REGNO (op0);
1436 /* Limit it in general registers if we are
1437 in reload pass or after reload pass. */
1438 if(strict)
1439 return REGNO_OK_FOR_INDEX_P (regno);
1440 else
1441 return true;
1442 }
1443
1444 return false;
1445
1446 default:
1447 return false;
1448 }
1449}
1450
1451static void
1452nds32_register_pass (
1453 rtl_opt_pass *(*make_pass_func) (gcc::context *),
1454 enum pass_positioning_ops pass_pos,
1455 const char *ref_pass_name)
1456{
1457 opt_pass *new_opt_pass = make_pass_func (g);
1458
1459 struct register_pass_info insert_pass =
1460 {
1461 new_opt_pass, /* pass */
1462 ref_pass_name, /* reference_pass_name */
1463 1, /* ref_pass_instance_number */
1464 pass_pos /* po_op */
1465 };
1466
1467 register_pass (&insert_pass);
1468}
1469
1470/* This function is called from nds32_option_override ().
1471 All new passes should be registered here. */
1472static void
1473nds32_register_passes (void)
1474{
1475 nds32_register_pass (
1476 make_pass_nds32_relax_opt,
1477 PASS_POS_INSERT_AFTER,
1478 "mach");
1479}
1480
1481/* ------------------------------------------------------------------------ */
1482
1483/* PART 3: Implement target hook stuff definitions. */
1484\f
1485
1486/* Computing the Length of an Insn.
1487 Modifies the length assigned to instruction INSN.
1488 LEN is the initially computed length of the insn. */
1489int
1490nds32_adjust_insn_length (rtx_insn *insn, int length)
1491{
1492 int adjust_value = 0;
1493 switch (recog_memoized (insn))
1494 {
1495 case CODE_FOR_call_internal:
1496 case CODE_FOR_call_value_internal:
1497 {
1498 /* We need insert a nop after a noretun function call
1499 to prevent software breakpoint corrupt the next function. */
1500 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
1501 {
1502 if (TARGET_16_BIT)
1503 adjust_value += 2;
1504 else
1505 adjust_value += 4;
1506 }
1507 }
1508 return length + adjust_value;
1509
1510 default:
1511 return length;
1512 }
1513}
1514
1515/* Register Usage. */
1516
1517static void
1518nds32_conditional_register_usage (void)
1519{
1520 int regno;
1521
1522 if (TARGET_HARD_FLOAT)
1523 {
1524 for (regno = NDS32_FIRST_FPR_REGNUM;
1525 regno <= NDS32_LAST_FPR_REGNUM; regno++)
1526 {
1527 fixed_regs[regno] = 0;
1528 if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
1529 call_used_regs[regno] = 1;
1530 else if (regno >= NDS32_FIRST_FPR_REGNUM + 22
1531 && regno < NDS32_FIRST_FPR_REGNUM + 48)
1532 call_used_regs[regno] = 1;
1533 else
1534 call_used_regs[regno] = 0;
1535 }
1536 }
1537 else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
1538 {
1539 for (regno = NDS32_FIRST_FPR_REGNUM;
1540 regno <= NDS32_LAST_FPR_REGNUM;
1541 regno++)
1542 fixed_regs[regno] = 0;
1543 }
1544}
1545
1546\f
1547/* Register Classes. */
1548
1549static unsigned char
1550nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED,
1551 machine_mode mode)
1552{
1553 /* Return the maximum number of consecutive registers
1554 needed to represent "mode" in a register of "rclass". */
1555 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1556}
1557
1558static int
1559nds32_register_priority (int hard_regno)
1560{
1561 /* Encourage to use r0-r7 for LRA when optimize for size. */
1562 if (optimize_size)
1563 {
1564 if (hard_regno < 8)
1565 return 4;
1566 else if (hard_regno < 16)
1567 return 3;
1568 else if (hard_regno < 28)
1569 return 2;
1570 else
1571 return 1;
1572 }
1573 else
1574 {
1575 if (hard_regno > 27)
1576 return 1;
1577 else
1578 return 4;
1579 }
1580}
1581
1582static bool
1583nds32_can_change_mode_class (machine_mode from,
1584 machine_mode to,
1585 reg_class_t rclass)
1586{
1587 /* Don't spill double-precision register to two singal-precision
1588 registers */
1589 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
1590 && GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
1591 {
1592 return !reg_classes_intersect_p (rclass, FP_REGS);
1593 }
1594
1595 return true;
1596}
1597
1598\f
1599/* Stack Layout and Calling Conventions. */
1600
1601/* There are three kinds of pointer concepts using in GCC compiler:
1602
1603 frame pointer: A pointer to the first location of local variables.
1604 stack pointer: A pointer to the top of a stack frame.
1605 argument pointer: A pointer to the incoming arguments.
1606
1607 In nds32 target calling convention, we are using 8-byte alignment.
1608 Besides, we would like to have each stack frame of a function includes:
1609
1610 [Block A]
1611 1. previous hard frame pointer
1612 2. return address
1613 3. callee-saved registers
1614 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
1615 and save it at
1616 cfun->machine->callee_saved_area_padding_bytes)
1617
1618 [Block B]
1619 1. local variables
1620 2. spilling location
1621 3. <padding bytes> (it will be calculated by GCC itself)
1622 4. incoming arguments
1623 5. <padding bytes> (it will be calculated by GCC itself)
1624
1625 [Block C]
1626 1. <padding bytes> (it will be calculated by GCC itself)
1627 2. outgoing arguments
1628
1629 We 'wrap' these blocks together with
1630 hard frame pointer ($r28) and stack pointer ($r31).
1631 By applying the basic frame/stack/argument pointers concept,
1632 the layout of a stack frame shoule be like this:
1633
1634 | |
1635 old stack pointer -> ----
1636 | | \
1637 | | saved arguments for
1638 | | vararg functions
1639 | | /
1640 hard frame pointer -> --
1641 & argument pointer | | \
1642 | | previous hardware frame pointer
1643 | | return address
1644 | | callee-saved registers
1645 | | /
1646 frame pointer -> --
1647 | | \
1648 | | local variables
1649 | | and incoming arguments
1650 | | /
1651 --
1652 | | \
1653 | | outgoing
1654 | | arguments
1655 | | /
1656 stack pointer -> ----
1657
1658 $SFP and $AP are used to represent frame pointer and arguments pointer,
1659 which will be both eliminated as hard frame pointer. */
1660
1661/* -- Eliminating Frame Pointer and Arg Pointer. */
1662
1663static bool
1664nds32_can_eliminate (const int from_reg, const int to_reg)
1665{
1666 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
1667 return true;
1668
1669 if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM)
1670 return true;
1671
1672 if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
1673 return true;
1674
1675 if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM)
1676 return true;
1677
1678 return false;
1679}
1680
1681/* -- Passing Arguments in Registers. */
1682
1683static rtx
1684nds32_function_arg (cumulative_args_t ca, machine_mode mode,
1685 const_tree type, bool named)
1686{
1687 unsigned int regno;
1688 CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
1689
1690 /* The last time this hook is called,
1691 it is called with MODE == VOIDmode. */
1692 if (mode == VOIDmode)
1693 return NULL_RTX;
1694
1695 /* For nameless arguments, we need to take care it individually. */
1696 if (!named)
1697 {
1698 /* If we are under hard float abi, we have arguments passed on the
1699 stack and all situation can be handled by GCC itself. */
1700 if (TARGET_HARD_FLOAT)
1701 return NULL_RTX;
1702
1703 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type))
1704 {
1705 /* If we still have enough registers to pass argument, pick up
1706 next available register number. */
1707 regno
1708 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
1709 return gen_rtx_REG (mode, regno);
1710 }
1711
1712 /* No register available, return NULL_RTX.
1713 The compiler will use stack to pass argument instead. */
1714 return NULL_RTX;
1715 }
1716
1717 /* The following is to handle named argument.
1718 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT
1719 are different. */
1720 if (TARGET_HARD_FLOAT)
1721 {
1722 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR
1723 to pass argument. We have to further check TYPE and MODE so
1724 that we can determine which kind of register we shall use. */
1725
1726 /* Note that we need to pass argument entirely in registers under
1727 hard float abi. */
1728 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1729 && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type))
1730 {
1731 /* Pick up the next available FPR register number. */
1732 regno
1733 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type);
1734 return gen_rtx_REG (mode, regno);
1735 }
1736 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
1737 && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type))
1738 {
1739 /* Pick up the next available GPR register number. */
1740 regno
1741 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
1742 return gen_rtx_REG (mode, regno);
1743 }
1744 }
1745 else
1746 {
1747 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass
1748 argument. Since we allow to pass argument partially in registers,
1749 we can just return it if there are still registers available. */
1750 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type))
1751 {
1752 /* Pick up the next available register number. */
1753 regno
1754 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type);
1755 return gen_rtx_REG (mode, regno);
1756 }
1757
1758 }
1759
1760 /* No register available, return NULL_RTX.
1761 The compiler will use stack to pass argument instead. */
1762 return NULL_RTX;
1763}
1764
1765static bool
1766nds32_must_pass_in_stack (machine_mode mode, const_tree type)
1767{
1768 /* Return true if a type must be passed in memory.
1769 If it is NOT using hard float abi, small aggregates can be
1770 passed in a register even we are calling a variadic function.
1771 So there is no need to take padding into consideration. */
1772 if (TARGET_HARD_FLOAT)
1773 return must_pass_in_stack_var_size_or_pad (mode, type);
1774 else
1775 return must_pass_in_stack_var_size (mode, type);
1776}
1777
1778static int
1779nds32_arg_partial_bytes (cumulative_args_t ca, machine_mode mode,
1780 tree type, bool named ATTRIBUTE_UNUSED)
1781{
1782 /* Returns the number of bytes at the beginning of an argument that
1783 must be put in registers. The value must be zero for arguments that are
1784 passed entirely in registers or that are entirely pushed on the stack.
1785 Besides, TARGET_FUNCTION_ARG for these arguments should return the
1786 first register to be used by the caller for this argument. */
1787 unsigned int needed_reg_count;
1788 unsigned int remaining_reg_count;
1789 CUMULATIVE_ARGS *cum;
1790
1791 cum = get_cumulative_args (ca);
1792
1793 /* Under hard float abi, we better have argument entirely passed in
1794 registers or pushed on the stack so that we can reduce the complexity
1795 of dealing with cum->gpr_offset and cum->fpr_offset. */
1796 if (TARGET_HARD_FLOAT)
1797 return 0;
1798
1799 /* If we have already runned out of argument registers, return zero
1800 so that the argument will be entirely pushed on the stack. */
1801 if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
1802 >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
1803 return 0;
1804
1805 /* Calculate how many registers do we need for this argument. */
1806 needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type);
1807
1808 /* Calculate how many argument registers have left for passing argument.
1809 Note that we should count it from next available register number. */
1810 remaining_reg_count
1811 = NDS32_MAX_GPR_REGS_FOR_ARGS
1812 - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
1813 - NDS32_GPR_ARG_FIRST_REGNUM);
1814
1815 /* Note that we have to return the nubmer of bytes, not registers count. */
1816 if (needed_reg_count > remaining_reg_count)
1817 return remaining_reg_count * UNITS_PER_WORD;
1818
1819 return 0;
1820}
1821
1822static void
1823nds32_function_arg_advance (cumulative_args_t ca, machine_mode mode,
1824 const_tree type, bool named)
1825{
1826 CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
1827
1828 if (named)
1829 {
1830 /* We need to further check TYPE and MODE so that we can determine
1831 which kind of register we shall advance. */
1832
1833 /* Under hard float abi, we may advance FPR registers. */
1834 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
1835 {
1836 cum->fpr_offset
1837 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type)
1838 - NDS32_FPR_ARG_FIRST_REGNUM
1839 + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
1840 }
1841 else
1842 {
1843 cum->gpr_offset
1844 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
1845 - NDS32_GPR_ARG_FIRST_REGNUM
1846 + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
1847 }
1848 }
1849 else
1850 {
1851 /* If this nameless argument is NOT under TARGET_HARD_FLOAT,
1852 we can advance next register as well so that caller is
1853 able to pass arguments in registers and callee must be
1854 in charge of pushing all of them into stack. */
1855 if (!TARGET_HARD_FLOAT)
1856 {
1857 cum->gpr_offset
1858 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
1859 - NDS32_GPR_ARG_FIRST_REGNUM
1860 + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
1861 }
1862 }
1863}
1864
1865static unsigned int
1866nds32_function_arg_boundary (machine_mode mode, const_tree type)
1867{
1868 return (nds32_needs_double_word_align (mode, type)
1869 ? NDS32_DOUBLE_WORD_ALIGNMENT
1870 : PARM_BOUNDARY);
1871}
1872
1873/* -- How Scalar Function Values Are Returned. */
1874
1875static rtx
1876nds32_function_value (const_tree ret_type,
1877 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1878 bool outgoing ATTRIBUTE_UNUSED)
1879{
1880 machine_mode mode;
1881 int unsignedp;
1882
1883 mode = TYPE_MODE (ret_type);
1884 unsignedp = TYPE_UNSIGNED (ret_type);
1885
1886 if (INTEGRAL_TYPE_P (ret_type))
1887 mode = promote_mode (ret_type, mode, &unsignedp);
1888
1889 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
1890 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM);
1891 else
1892 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
1893}
1894
1895static rtx
1896nds32_libcall_value (machine_mode mode,
1897 const_rtx fun ATTRIBUTE_UNUSED)
1898{
1899 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
1900 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM);
1901
1902 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
1903}
1904
1905static bool
1906nds32_function_value_regno_p (const unsigned int regno)
1907{
1908 if (regno == NDS32_GPR_RET_FIRST_REGNUM
1909 || (TARGET_HARD_FLOAT
1910 && regno == NDS32_FPR_RET_FIRST_REGNUM))
1911 return true;
1912
1913 return false;
1914}
1915
1916/* -- How Large Values Are Returned. */
1917
1918static bool
1919nds32_return_in_memory (const_tree type,
1920 const_tree fntype ATTRIBUTE_UNUSED)
1921{
1922 /* Note that int_size_in_bytes can return -1 if the size can vary
1923 or is larger than an integer. */
1924 HOST_WIDE_INT size = int_size_in_bytes (type);
1925
1926 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers,
1927 the return value is supposed to be in memory. We need to be aware of
1928 that the size may be -1. */
1929 if (TREE_CODE (type) == COMPLEX_TYPE)
1930 if (size < 0 || size > 2 * UNITS_PER_WORD)
1931 return true;
1932
1933 /* If it is BLKmode and the total size cannot be hold within two registers,
1934 the return value is supposed to be in memory. We need to be aware of
1935 that the size may be -1. */
1936 if (TYPE_MODE (type) == BLKmode)
1937 if (size < 0 || size > 2 * UNITS_PER_WORD)
1938 return true;
1939
1940 /* For other cases, having result in memory is unnecessary. */
1941 return false;
1942}
1943
1944/* -- Function Entry and Exit. */
1945
1946/* The content produced from this function
1947 will be placed before prologue body. */
1948static void
1949nds32_asm_function_prologue (FILE *file)
1950{
1951 int r;
1952 const char *func_name;
1953 tree attrs;
1954 tree name;
1955
1956 /* All stack frame information is supposed to be
1957 already computed when expanding prologue.
1958 The result is in cfun->machine.
1959 DO NOT call nds32_compute_stack_frame() here
1960 because it may corrupt the essential information. */
1961
1962 fprintf (file, "\t! BEGIN PROLOGUE\n");
1963 fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed);
1964 fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size);
1965 fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size);
1966 fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size);
1967
1968 /* Use df_regs_ever_live_p() to detect if the register
1969 is ever used in the current function. */
1970 fprintf (file, "\t! registers ever_live: ");
1971 for (r = 0; r < 65; r++)
1972 {
1973 if (df_regs_ever_live_p (r))
1974 fprintf (file, "%s, ", reg_names[r]);
1975 }
1976 fputc ('\n', file);
1977
1978 /* Display the attributes of this function. */
1979 fprintf (file, "\t! function attributes: ");
1980 /* Get the attributes tree list.
1981 Note that GCC builds attributes list with reverse order. */
1982 attrs = DECL_ATTRIBUTES (current_function_decl);
1983
1984 /* If there is no any attribute, print out "None". */
1985 if (!attrs)
1986 fprintf (file, "None");
1987
1988 /* If there are some attributes, try if we need to
1989 construct isr vector information. */
1990 func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl));
1991 nds32_construct_isr_vectors_information (attrs, func_name);
1992
1993 /* Display all attributes of this function. */
1994 while (attrs)
1995 {
1996 name = TREE_PURPOSE (attrs);
1997 fprintf (file, "%s ", IDENTIFIER_POINTER (name));
1998
1999 /* Pick up the next attribute. */
2000 attrs = TREE_CHAIN (attrs);
2001 }
2002 fputc ('\n', file);
2003}
2004
2005/* After rtl prologue has been expanded, this function is used. */
2006static void
2007nds32_asm_function_end_prologue (FILE *file)
2008{
2009 fprintf (file, "\t! END PROLOGUE\n");
2010
2011 /* If frame pointer is NOT needed and -mfp-as-gp is issued,
2012 we can generate special directive: ".omit_fp_begin"
2013 to guide linker doing fp-as-gp optimization.
2014 However, for a naked function, which means
2015 it should not have prologue/epilogue,
2016 using fp-as-gp still requires saving $fp by push/pop behavior and
2017 there is no benefit to use fp-as-gp on such small function.
2018 So we need to make sure this function is NOT naked as well. */
2019 if (!frame_pointer_needed
2020 && !cfun->machine->naked_p
2021 && cfun->machine->fp_as_gp_p)
2022 {
2023 fprintf (file, "\t! ----------------------------------------\n");
2024 fprintf (file, "\t! Guide linker to do "
2025 "link time optimization: fp-as-gp\n");
2026 fprintf (file, "\t! We add one more instruction to "
2027 "initialize $fp near to $gp location.\n");
2028 fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n");
2029 fprintf (file, "\t! this extra instruction should be "
2030 "eliminated at link stage.\n");
2031 fprintf (file, "\t.omit_fp_begin\n");
2032 fprintf (file, "\tla\t$fp,_FP_BASE_\n");
2033 fprintf (file, "\t! ----------------------------------------\n");
2034 }
2035}
2036
2037/* Before rtl epilogue has been expanded, this function is used. */
2038static void
2039nds32_asm_function_begin_epilogue (FILE *file)
2040{
2041 /* If frame pointer is NOT needed and -mfp-as-gp is issued,
2042 we can generate special directive: ".omit_fp_end"
2043 to claim fp-as-gp optimization range.
2044 However, for a naked function,
2045 which means it should not have prologue/epilogue,
2046 using fp-as-gp still requires saving $fp by push/pop behavior and
2047 there is no benefit to use fp-as-gp on such small function.
2048 So we need to make sure this function is NOT naked as well. */
2049 if (!frame_pointer_needed
2050 && !cfun->machine->naked_p
2051 && cfun->machine->fp_as_gp_p)
2052 {
2053 fprintf (file, "\t! ----------------------------------------\n");
2054 fprintf (file, "\t! Claim the range of fp-as-gp "
2055 "link time optimization\n");
2056 fprintf (file, "\t.omit_fp_end\n");
2057 fprintf (file, "\t! ----------------------------------------\n");
2058 }
2059
2060 fprintf (file, "\t! BEGIN EPILOGUE\n");
2061}
2062
2063/* The content produced from this function
2064 will be placed after epilogue body. */
2065static void
2066nds32_asm_function_epilogue (FILE *file)
2067{
2068 fprintf (file, "\t! END EPILOGUE\n");
2069}
2070
2071static void
2072nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
2073 HOST_WIDE_INT delta,
2074 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2075 tree function)
2076{
2077 int this_regno;
2078
2079 /* Make sure unwind info is emitted for the thunk if needed. */
2080 final_start_function (emit_barrier (), file, 1);
2081
2082 this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
2083 ? 1
2084 : 0);
2085
2086 if (delta != 0)
2087 {
2088 if (satisfies_constraint_Is15 (GEN_INT (delta)))
2089 {
2090 fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n",
2091 this_regno, this_regno, delta);
2092 }
2093 else if (satisfies_constraint_Is20 (GEN_INT (delta)))
2094 {
2095 fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta);
2096 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
2097 }
2098 else
2099 {
2100 fprintf (file,
2101 "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n",
2102 delta);
2103 fprintf (file,
2104 "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n",
2105 delta);
2106 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
2107 }
2108 }
2109
2110 fprintf (file, "\tb\t");
2111 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2112 fprintf (file, "\n");
2113
2114 final_end_function ();
2115}
2116
2117/* -- Permitting tail calls. */
2118
2119/* Return true if it is ok to do sibling call optimization. */
2120static bool
2121nds32_function_ok_for_sibcall (tree decl,
2122 tree exp ATTRIBUTE_UNUSED)
2123{
2124 /* The DECL is NULL if it is an indirect call. */
2125
2126 /* 1. Do not apply sibling call if -mv3push is enabled,
2127 because pop25 instruction also represents return behavior.
2128 2. If this function is a variadic function, do not apply sibling call
2129 because the stack layout may be a mess.
2130 3. We don't want to apply sibling call optimization for indirect
2131 sibcall because the pop behavior in epilogue may pollute the
2132 content of caller-saved regsiter when the register is used for
2133 indirect sibcall. */
2134 return (!TARGET_V3PUSH
2135 && (cfun->machine->va_args_size == 0)
2136 && decl);
2137}
2138
2139/* Determine whether we need to enable warning for function return check. */
2140static bool
2141nds32_warn_func_return (tree decl)
2142{
2143 /* Naked functions are implemented entirely in assembly, including the
2144 return sequence, so suppress warnings about this. */
2145 return !nds32_naked_function_p (decl);
2146}
2147
2148\f
2149/* Implementing the Varargs Macros. */
2150
2151static void
2152nds32_setup_incoming_varargs (cumulative_args_t ca,
2153 machine_mode mode,
2154 tree type,
2155 int *pretend_args_size,
2156 int second_time ATTRIBUTE_UNUSED)
2157{
2158 unsigned int total_args_regs;
2159 unsigned int num_of_used_regs;
2160 unsigned int remaining_reg_count;
2161 CUMULATIVE_ARGS *cum;
2162
2163 /* If we are under hard float abi, we do not need to set *pretend_args_size.
2164 So that all nameless arguments are pushed by caller and all situation
2165 can be handled by GCC itself. */
2166 if (TARGET_HARD_FLOAT)
2167 return;
2168
2169 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
2170 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
2171 However, for nameless(anonymous) arguments, we should push them on the
2172 stack so that all the nameless arguments appear to have been passed
2173 consecutively in the memory for accessing. Hence, we need to check and
2174 exclude the registers that are used for named arguments. */
2175
2176 cum = get_cumulative_args (ca);
2177
2178 /* The MODE and TYPE describe the last argument.
2179 We need those information to determine the remaining registers
2180 for varargs. */
2181 total_args_regs
2182 = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM;
2183 num_of_used_regs
2184 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type)
2185 + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
2186
2187 remaining_reg_count = total_args_regs - num_of_used_regs;
2188 *pretend_args_size = remaining_reg_count * UNITS_PER_WORD;
2189
2190 return;
2191}
2192
2193static bool
2194nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
2195{
2196 /* If this hook returns true, the named argument of FUNCTION_ARG is always
2197 true for named arguments, and false for unnamed arguments. */
2198 return true;
2199}
2200
2201\f
2202/* Trampolines for Nested Functions. */
2203
2204static void
2205nds32_asm_trampoline_template (FILE *f)
2206{
2207 if (TARGET_REDUCED_REGS)
2208 {
2209 /* Trampoline is not supported on reduced-set registers yet. */
2210 sorry ("a nested function is not supported for reduced registers");
2211 }
2212 else
2213 {
2214 asm_fprintf (f, "\t! Trampoline code template\n");
2215 asm_fprintf (f, "\t! This code fragment will be copied "
2216 "into stack on demand\n");
2217
2218 asm_fprintf (f, "\tmfusr\t$r16,$pc\n");
2219 asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] "
2220 "! load nested function address\n");
2221 asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] "
2222 "! load chain_value\n");
2223 asm_fprintf (f, "\tjr\t$r15\n");
2224 }
2225
2226 /* Preserve space ($pc + 16) for saving chain_value,
2227 nds32_trampoline_init will fill the value in this slot. */
2228 asm_fprintf (f, "\t! space for saving chain_value\n");
2229 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2230
2231 /* Preserve space ($pc + 20) for saving nested function address,
2232 nds32_trampoline_init will fill the value in this slot. */
2233 asm_fprintf (f, "\t! space for saving nested function address\n");
2234 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2235}
2236
2237/* Emit RTL insns to initialize the variable parts of a trampoline. */
2238static void
2239nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2240{
2241 int i;
2242
2243 /* Nested function address. */
2244 rtx fnaddr;
2245 /* The memory rtx that is going to
2246 be filled with chain_value. */
2247 rtx chain_value_mem;
2248 /* The memory rtx that is going to
2249 be filled with nested function address. */
2250 rtx nested_func_mem;
2251
2252 /* Start address of trampoline code in stack, for doing cache sync. */
2253 rtx sync_cache_addr;
2254 /* Temporary register for sync instruction. */
2255 rtx tmp_reg;
2256 /* Instruction-cache sync instruction,
2257 requesting an argument as starting address. */
2258 rtx isync_insn;
2259 /* For convenience reason of doing comparison. */
2260 int tramp_align_in_bytes;
2261
2262 /* Trampoline is not supported on reduced-set registers yet. */
2263 if (TARGET_REDUCED_REGS)
2264 sorry ("a nested function is not supported for reduced registers");
2265
2266 /* STEP 1: Copy trampoline code template into stack,
2267 fill up essential data into stack. */
2268
2269 /* Extract nested function address rtx. */
2270 fnaddr = XEXP (DECL_RTL (fndecl), 0);
2271
2272 /* m_tramp is memory rtx that is going to be filled with trampoline code.
2273 We have nds32_asm_trampoline_template() to emit template pattern. */
2274 emit_block_move (m_tramp, assemble_trampoline_template (),
2275 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2276
2277 /* After copying trampoline code into stack,
2278 fill chain_value into stack. */
2279 chain_value_mem = adjust_address (m_tramp, SImode, 16);
2280 emit_move_insn (chain_value_mem, chain_value);
2281 /* After copying trampoline code int stack,
2282 fill nested function address into stack. */
2283 nested_func_mem = adjust_address (m_tramp, SImode, 20);
2284 emit_move_insn (nested_func_mem, fnaddr);
2285
2286 /* STEP 2: Sync instruction-cache. */
2287
2288 /* We have successfully filled trampoline code into stack.
2289 However, in order to execute code in stack correctly,
2290 we must sync instruction cache. */
2291 sync_cache_addr = XEXP (m_tramp, 0);
2292 tmp_reg = gen_reg_rtx (SImode);
2293 isync_insn = gen_unspec_volatile_isync (tmp_reg);
2294
2295 /* Because nds32_cache_block_size is in bytes,
2296 we get trampoline alignment in bytes for convenient comparison. */
2297 tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT;
2298
2299 if (tramp_align_in_bytes >= nds32_cache_block_size
2300 && (tramp_align_in_bytes % nds32_cache_block_size) == 0)
2301 {
2302 /* Under this condition, the starting address of trampoline
2303 must be aligned to the starting address of each cache block
2304 and we do not have to worry about cross-boundary issue. */
2305 for (i = 0;
2306 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
2307 / nds32_cache_block_size;
2308 i++)
2309 {
2310 emit_move_insn (tmp_reg,
2311 plus_constant (Pmode, sync_cache_addr,
2312 nds32_cache_block_size * i));
2313 emit_insn (isync_insn);
2314 }
2315 }
2316 else if (TRAMPOLINE_SIZE > nds32_cache_block_size)
2317 {
2318 /* The starting address of trampoline code
2319 may not be aligned to the cache block,
2320 so the trampoline code may be across two cache block.
2321 We need to sync the last element, which is 4-byte size,
2322 of trampoline template. */
2323 for (i = 0;
2324 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
2325 / nds32_cache_block_size;
2326 i++)
2327 {
2328 emit_move_insn (tmp_reg,
2329 plus_constant (Pmode, sync_cache_addr,
2330 nds32_cache_block_size * i));
2331 emit_insn (isync_insn);
2332 }
2333
2334 /* The last element of trampoline template is 4-byte size. */
2335 emit_move_insn (tmp_reg,
2336 plus_constant (Pmode, sync_cache_addr,
2337 TRAMPOLINE_SIZE - 4));
2338 emit_insn (isync_insn);
2339 }
2340 else
2341 {
2342 /* This is the simplest case.
2343 Because TRAMPOLINE_SIZE is less than or
2344 equal to nds32_cache_block_size,
2345 we can just sync start address and
2346 the last element of trampoline code. */
2347
2348 /* Sync starting address of tampoline code. */
2349 emit_move_insn (tmp_reg, sync_cache_addr);
2350 emit_insn (isync_insn);
2351 /* Sync the last element, which is 4-byte size,
2352 of trampoline template. */
2353 emit_move_insn (tmp_reg,
2354 plus_constant (Pmode, sync_cache_addr,
2355 TRAMPOLINE_SIZE - 4));
2356 emit_insn (isync_insn);
2357 }
2358
2359 /* Set instruction serialization barrier
2360 to guarantee the correct operations. */
2361 emit_insn (gen_unspec_volatile_isb ());
2362}
2363
2364\f
2365/* Addressing Modes. */
2366
2367static bool
2368nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
2369{
2370 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
2371 {
2372 /* When using floating-point instructions,
2373 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
2374 if ((mode == DFmode || mode == SFmode)
2375 && (GET_CODE (x) == SYMBOL_REF
2376 || GET_CODE(x) == CONST))
2377 return false;
2378
2379 /* Allow [post_modify] addressing mode, when using FPU instructions. */
2380 if (GET_CODE (x) == POST_MODIFY
2381 && mode == DFmode)
2382 {
2383 if (GET_CODE (XEXP (x, 0)) == REG
2384 && GET_CODE (XEXP (x, 1)) == PLUS)
2385 {
2386 rtx plus_op = XEXP (x, 1);
2387 rtx op0 = XEXP (plus_op, 0);
2388 rtx op1 = XEXP (plus_op, 1);
2389
2390 if (nds32_address_register_rtx_p (op0, strict)
2391 && CONST_INT_P (op1))
2392 {
2393 if (satisfies_constraint_Is14 (op1))
2394 {
2395 /* Make sure address is word alignment.
2396 Currently we do not have 64-bit load/store yet,
2397 so we will use two 32-bit load/store instructions to do
2398 memory access and they are single word alignment. */
2399 if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1)))
2400 return true;
2401 }
2402 }
2403 }
2404 }
2405 }
2406
2407 /* For (mem:DI addr) or (mem:DF addr) case,
2408 we only allow 'addr' to be [reg], [symbol_ref],
2409 [const], or [reg + const_int] pattern. */
2410 if (mode == DImode || mode == DFmode)
2411 {
2412 /* Allow [Reg + const_int] addressing mode. */
2413 if (GET_CODE (x) == PLUS)
2414 {
2415 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)
2416 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)
2417 && CONST_INT_P (XEXP (x, 1)))
2418 return true;
2419 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict)
2420 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)
2421 && CONST_INT_P (XEXP (x, 0)))
2422 return true;
2423 }
2424
2425 /* Allow [post_inc] and [post_dec] addressing mode. */
2426 if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC)
2427 {
2428 if (nds32_address_register_rtx_p (XEXP (x, 0), strict))
2429 return true;
2430 }
2431
2432 /* Now check [reg], [symbol_ref], and [const]. */
2433 if (GET_CODE (x) != REG
2434 && GET_CODE (x) != SYMBOL_REF
2435 && GET_CODE (x) != CONST)
2436 return false;
2437 }
2438
2439 /* Check if 'x' is a valid address. */
2440 switch (GET_CODE (x))
2441 {
2442 case REG:
2443 /* (mem (reg A)) => [Ra] */
2444 return nds32_address_register_rtx_p (x, strict);
2445
2446 case SYMBOL_REF:
2447 /* (mem (symbol_ref A)) => [symbol_ref] */
2448 /* If -mcmodel=large, the 'symbol_ref' is not a valid address
2449 during or after LRA/reload phase. */
2450 if (TARGET_CMODEL_LARGE
2451 && (reload_completed
2452 || reload_in_progress
2453 || lra_in_progress))
2454 return false;
2455 /* If -mcmodel=medium and the symbol references to rodata section,
2456 the 'symbol_ref' is not a valid address during or after
2457 LRA/reload phase. */
2458 if (TARGET_CMODEL_MEDIUM
2459 && NDS32_SYMBOL_REF_RODATA_P (x)
2460 && (reload_completed
2461 || reload_in_progress
2462 || lra_in_progress))
2463 return false;
2464
2465 return true;
2466
2467 case CONST:
2468 /* (mem (const (...)))
2469 => [ + const_addr ], where const_addr = symbol_ref + const_int */
2470 if (GET_CODE (XEXP (x, 0)) == PLUS)
2471 {
2472 rtx plus_op = XEXP (x, 0);
2473
2474 rtx op0 = XEXP (plus_op, 0);
2475 rtx op1 = XEXP (plus_op, 1);
2476
2477 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
2478 {
2479 /* Now we see the [ + const_addr ] pattern, but we need
2480 some further checking. */
2481 /* If -mcmodel=large, the 'const_addr' is not a valid address
2482 during or after LRA/reload phase. */
2483 if (TARGET_CMODEL_LARGE
2484 && (reload_completed
2485 || reload_in_progress
2486 || lra_in_progress))
2487 return false;
2488 /* If -mcmodel=medium and the symbol references to rodata section,
2489 the 'const_addr' is not a valid address during or after
2490 LRA/reload phase. */
2491 if (TARGET_CMODEL_MEDIUM
2492 && NDS32_SYMBOL_REF_RODATA_P (op0)
2493 && (reload_completed
2494 || reload_in_progress
2495 || lra_in_progress))
2496 return false;
2497
2498 /* At this point we can make sure 'const_addr' is a
2499 valid address. */
2500 return true;
2501 }
2502 }
2503
2504 return false;
2505
2506 case POST_MODIFY:
2507 /* (mem (post_modify (reg) (plus (reg) (reg))))
2508 => [Ra], Rb */
2509 /* (mem (post_modify (reg) (plus (reg) (const_int))))
2510 => [Ra], const_int */
2511 if (GET_CODE (XEXP (x, 0)) == REG
2512 && GET_CODE (XEXP (x, 1)) == PLUS)
2513 {
2514 rtx plus_op = XEXP (x, 1);
2515
2516 rtx op0 = XEXP (plus_op, 0);
2517 rtx op1 = XEXP (plus_op, 1);
2518
2519 if (nds32_address_register_rtx_p (op0, strict)
2520 && nds32_legitimate_index_p (mode, op1, strict))
2521 return true;
2522 else
2523 return false;
2524 }
2525
2526 return false;
2527
2528 case POST_INC:
2529 case POST_DEC:
2530 /* (mem (post_inc reg)) => [Ra], 1/2/4 */
2531 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
2532 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
2533 We only need to deal with register Ra. */
2534 if (nds32_address_register_rtx_p (XEXP (x, 0), strict))
2535 return true;
2536 else
2537 return false;
2538
2539 case PLUS:
2540 /* (mem (plus reg const_int))
2541 => [Ra + imm] */
2542 /* (mem (plus reg reg))
2543 => [Ra + Rb] */
2544 /* (mem (plus (mult reg const_int) reg))
2545 => [Ra + Rb << sv] */
2546 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)
2547 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict))
2548 return true;
2549 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict)
2550 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict))
2551 return true;
2552 else
2553 return false;
2554
2555 case LO_SUM:
2556 /* (mem (lo_sum (reg) (symbol_ref))) */
2557 /* (mem (lo_sum (reg) (const))) */
2558 gcc_assert (REG_P (XEXP (x, 0)));
2559 if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
2560 || GET_CODE (XEXP (x, 1)) == CONST)
2561 return nds32_legitimate_address_p (mode, XEXP (x, 1), strict);
2562 else
2563 return false;
2564
2565 default:
2566 return false;
2567 }
2568}
2569
2570\f
2571/* Condition Code Status. */
2572
2573/* -- Representation of condition codes using registers. */
2574
2575static void
2576nds32_canonicalize_comparison (int *code,
2577 rtx *op0 ATTRIBUTE_UNUSED,
2578 rtx *op1,
2579 bool op0_preserve_value ATTRIBUTE_UNUSED)
2580{
2581 /* When the instruction combination pass tries to combine a comparison insn
2582 with its previous insns, it also transforms the operator in order to
2583 minimize its constant field. For example, it tries to transform a
2584 comparison insn from
2585 (set (reg:SI 54)
2586 (ltu:SI (reg:SI 52)
2587 (const_int 10 [0xa])))
2588 to
2589 (set (reg:SI 54)
2590 (leu:SI (reg:SI 52)
2591 (const_int 9 [0x9])))
2592
2593 However, the nds32 target only provides instructions supporting the LTU
2594 operation directly, and the implementation of the pattern "cbranchsi4"
2595 only expands the LTU form. In order to handle the non-LTU operations
2596 generated from passes other than the RTL expansion pass, we have to
2597 implement this hook to revert those changes. Since we only expand the LTU
2598 operator in the RTL expansion pass, we might only need to handle the LEU
2599 case, unless we find other optimization passes perform more aggressive
2600 transformations. */
2601
2602 if (*code == LEU && CONST_INT_P (*op1))
2603 {
2604 *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode);
2605 *code = LTU;
2606 }
2607}
2608
2609\f
2610/* Describing Relative Costs of Operations. */
2611
2612static int
2613nds32_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2614 reg_class_t from,
2615 reg_class_t to)
2616{
2617 if ((from == FP_REGS && to != FP_REGS)
2618 || (from != FP_REGS && to == FP_REGS))
2619 return 9;
2620 else if (from == HIGH_REGS || to == HIGH_REGS)
2621 return optimize_size ? 6 : 2;
2622 else
2623 return 2;
2624}
2625
2626static int
2627nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2628 reg_class_t rclass ATTRIBUTE_UNUSED,
2629 bool in ATTRIBUTE_UNUSED)
2630{
2631 return 8;
2632}
2633
2634/* This target hook describes the relative costs of RTL expressions.
2635 Return 'true' when all subexpressions of x have been processed.
2636 Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
2637 Refer to gcc/rtlanal.c for more information. */
2638static bool
2639nds32_rtx_costs (rtx x,
2640 machine_mode mode,
2641 int outer_code,
2642 int opno,
2643 int *total,
2644 bool speed)
2645{
2646 return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed);
2647}
2648
2649static int
2650nds32_address_cost (rtx address,
2651 machine_mode mode,
2652 addr_space_t as,
2653 bool speed)
2654{
2655 return nds32_address_cost_impl (address, mode, as, speed);
2656}
2657
2658\f
2659/* Dividing the Output into Sections (Texts, Data, . . . ). */
2660
2661/* If references to a symbol or a constant must be treated differently
2662 depending on something about the variable or function named by the symbol
2663 (such as what section it is in), we use this hook to store flags
2664 in symbol_ref rtx. */
2665static void
2666nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p)
2667{
2668 default_encode_section_info (decl, rtl, new_decl_p);
2669
2670 /* For the memory rtx, if it references to rodata section, we can store
2671 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the
2672 nds32_legitimate_address_p() can determine how to treat such symbol_ref
2673 based on -mcmodel=X and this information. */
2674 if (MEM_P (rtl) && MEM_READONLY_P (rtl))
2675 {
2676 rtx addr = XEXP (rtl, 0);
2677
2678 if (GET_CODE (addr) == SYMBOL_REF)
2679 {
2680 /* For (mem (symbol_ref X)) case. */
2681 SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA;
2682 }
2683 else if (GET_CODE (addr) == CONST
2684 && GET_CODE (XEXP (addr, 0)) == PLUS)
2685 {
2686 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */
2687 rtx plus_op = XEXP (addr, 0);
2688 rtx op0 = XEXP (plus_op, 0);
2689 rtx op1 = XEXP (plus_op, 1);
2690
2691 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
2692 SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA;
2693 }
2694 }
2695}
2696
2697\f
2698/* Defining the Output Assembler Language. */
2699
2700/* -- The Overall Framework of an Assembler File. */
2701
2702static void
2703nds32_asm_file_start (void)
2704{
2705 default_file_start ();
2706
2707 /* Tell assembler which ABI we are using. */
2708 fprintf (asm_out_file, "\t! ABI version\n");
2709 if (TARGET_HARD_FLOAT)
2710 fprintf (asm_out_file, "\t.abi_2fp_plus\n");
2711 else
2712 fprintf (asm_out_file, "\t.abi_2\n");
2713
2714 /* Tell assembler that this asm code is generated by compiler. */
2715 fprintf (asm_out_file, "\t! This asm file is generated by compiler\n");
2716 fprintf (asm_out_file, "\t.flag\tverbatim\n");
2717 /* Give assembler the size of each vector for interrupt handler. */
2718 fprintf (asm_out_file, "\t! This vector size directive is required "
2719 "for checking inconsistency on interrupt handler\n");
2720 fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size);
2721
2722 fprintf (asm_out_file, "\t! ------------------------------------\n");
2723
2724 if (TARGET_ISA_V2)
2725 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2");
2726 if (TARGET_ISA_V3)
2727 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3");
2728 if (TARGET_ISA_V3M)
2729 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M");
2730
2731 if (TARGET_CMODEL_SMALL)
2732 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL");
2733 if (TARGET_CMODEL_MEDIUM)
2734 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM");
2735 if (TARGET_CMODEL_LARGE)
2736 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE");
2737
2738 fprintf (asm_out_file, "\t! Endian setting\t: %s\n",
2739 ((TARGET_BIG_ENDIAN) ? "big-endian"
2740 : "little-endian"));
2741 fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n",
2742 ((TARGET_FPU_SINGLE) ? "Yes"
2743 : "No"));
2744 fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n",
2745 ((TARGET_FPU_DOUBLE) ? "Yes"
2746 : "No"));
2747 fprintf (asm_out_file, "\t! ABI version\t\t: %s\n",
2748 ((TARGET_HARD_FLOAT) ? "ABI2FP+"
2749 : "ABI2"));
2750
2751 fprintf (asm_out_file, "\t! ------------------------------------\n");
2752
2753 fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n",
2754 ((TARGET_CMOV) ? "Yes"
2755 : "No"));
2756 fprintf (asm_out_file, "\t! Use performance extension\t: %s\n",
2757 ((TARGET_EXT_PERF) ? "Yes"
2758 : "No"));
2759 fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n",
2760 ((TARGET_EXT_PERF2) ? "Yes"
2761 : "No"));
2762 fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n",
2763 ((TARGET_EXT_STRING) ? "Yes"
2764 : "No"));
2765
2766 fprintf (asm_out_file, "\t! ------------------------------------\n");
2767
2768 fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n",
2769 ((TARGET_V3PUSH) ? "Yes"
2770 : "No"));
2771 fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n",
2772 ((TARGET_16_BIT) ? "Yes"
2773 : "No"));
2774 fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n",
2775 ((TARGET_REDUCED_REGS) ? "Yes"
2776 : "No"));
2777
2778 fprintf (asm_out_file, "\t! ------------------------------------\n");
2779
2780 if (optimize_size)
2781 fprintf (asm_out_file, "\t! Optimization level\t: -Os\n");
2782 else
2783 fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize);
2784
2785 fprintf (asm_out_file, "\t! ------------------------------------\n");
2786
2787 fprintf (asm_out_file, "\t! Cache block size\t: %d\n",
2788 nds32_cache_block_size);
2789
2790 fprintf (asm_out_file, "\t! ------------------------------------\n");
2791
2792 nds32_asm_file_start_for_isr ();
2793}
2794
2795static void
2796nds32_asm_file_end (void)
2797{
2798 nds32_asm_file_end_for_isr ();
2799
2800 fprintf (asm_out_file, "\t! ------------------------------------\n");
2801}
2802
2803/* -- Output and Generation of Labels. */
2804
2805static void
2806nds32_asm_globalize_label (FILE *stream, const char *name)
2807{
2808 fputs ("\t.global\t", stream);
2809 assemble_name (stream, name);
2810 fputs ("\n", stream);
2811}
2812
2813/* -- Output of Assembler Instructions. */
2814
2815static void
2816nds32_print_operand (FILE *stream, rtx x, int code)
2817{
2818 HOST_WIDE_INT one_position;
2819 HOST_WIDE_INT zero_position;
2820 bool pick_lsb_p = false;
2821 bool pick_msb_p = false;
2822 int regno;
2823
2824 int op_value;
2825
2826 switch (code)
2827 {
2828 case 0 :
2829 /* Do nothing special. */
2830 break;
2831
2832 case 'b':
2833 /* Use exact_log2() to search the 0-bit position. */
2834 gcc_assert (CONST_INT_P (x));
2835 zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode));
2836 gcc_assert (zero_position != -1);
2837 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position);
2838
2839 /* No need to handle following process, so return immediately. */
2840 return;
2841
2842 case 'e':
2843 gcc_assert (MEM_P (x)
2844 && GET_CODE (XEXP (x, 0)) == PLUS
2845 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
2846 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1)));
2847
2848 /* No need to handle following process, so return immediately. */
2849 return;
2850 case 'B':
2851 /* Use exact_log2() to search the 1-bit position. */
2852 gcc_assert (CONST_INT_P (x));
2853 one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode));
2854 gcc_assert (one_position != -1);
2855 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position);
2856
2857 /* No need to handle following process, so return immediately. */
2858 return;
2859
2860 case 'L':
2861 /* X is supposed to be REG rtx. */
2862 gcc_assert (REG_P (x));
2863 /* Claim that we are going to pick LSB part of X. */
2864 pick_lsb_p = true;
2865 break;
2866
2867 case 'H':
2868 /* X is supposed to be REG rtx. */
2869 gcc_assert (REG_P (x));
2870 /* Claim that we are going to pick MSB part of X. */
2871 pick_msb_p = true;
2872 break;
2873
2874 case 'V':
2875 /* 'x' is supposed to be CONST_INT, get the value. */
2876 gcc_assert (CONST_INT_P (x));
2877 op_value = INTVAL (x);
2878
2879 /* According to the Andes architecture,
2880 the system/user register index range is 0 ~ 1023.
2881 In order to avoid conflict between user-specified-integer value
2882 and enum-specified-register value,
2883 the 'enum nds32_intrinsic_registers' value
2884 in nds32_intrinsic.h starts from 1024. */
2885 if (op_value < 1024 && op_value >= 0)
2886 {
2887 /* If user gives integer value directly (0~1023),
2888 we just print out the value. */
2889 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value);
2890 }
2891 else if (op_value < 0
2892 || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names)
2893 + 1024))
2894 {
2895 /* The enum index value for array size is out of range. */
2896 error ("intrinsic register index is out of range");
2897 }
2898 else
2899 {
2900 /* If user applies normal way with __NDS32_REG_XXX__ enum data,
2901 we can print out register name. Remember to substract 1024. */
2902 fprintf (stream, "%s",
2903 nds32_intrinsic_register_names[op_value - 1024]);
2904 }
2905
2906 /* No need to handle following process, so return immediately. */
2907 return;
2908
2909 default :
2910 /* Unknown flag. */
2911 output_operand_lossage ("invalid operand output code");
2912 break;
2913 }
2914
2915 switch (GET_CODE (x))
2916 {
2917 case LABEL_REF:
2918 case SYMBOL_REF:
2919 output_addr_const (stream, x);
2920 break;
2921
2922 case REG:
2923 /* Print a Double-precision register name. */
2924 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
2925 && NDS32_IS_FPR_REGNUM (REGNO (x)))
2926 {
2927 regno = REGNO (x);
2928 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno))
2929 {
2930 output_operand_lossage ("invalid operand for code '%c'", code);
2931 break;
2932 }
2933 fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1);
2934 break;
2935 }
2936
2937 /* Print LSB or MSB part of register pair if the
2938 constraint modifier 'L' or 'H' is specified. */
2939 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
2940 && NDS32_IS_GPR_REGNUM (REGNO (x)))
2941 {
2942 if ((pick_lsb_p && WORDS_BIG_ENDIAN)
2943 || (pick_msb_p && !WORDS_BIG_ENDIAN))
2944 {
2945 /* If we would like to print out LSB register under big-endian,
2946 or print out MSB register under little-endian, we need to
2947 increase register number. */
2948 regno = REGNO (x);
2949 regno++;
2950 fputs (reg_names[regno], stream);
2951 break;
2952 }
2953 }
2954
2955 /* Forbid using static chain register ($r16)
2956 on reduced-set registers configuration. */
2957 if (TARGET_REDUCED_REGS
2958 && REGNO (x) == STATIC_CHAIN_REGNUM)
2959 sorry ("a nested function is not supported for reduced registers");
2960
2961 /* Normal cases, print out register name. */
2962 fputs (reg_names[REGNO (x)], stream);
2963 break;
2964
2965 case MEM:
2966 output_address (GET_MODE (x), XEXP (x, 0));
2967 break;
2968
2969 case HIGH:
2970 if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE)
2971 {
2972 const REAL_VALUE_TYPE *rv;
2973 long val;
2974 gcc_assert (GET_MODE (x) == SFmode);
2975
2976 rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0));
2977 REAL_VALUE_TO_TARGET_SINGLE (*rv, val);
2978
2979 fprintf (stream, "hi20(0x%lx)", val);
2980 }
2981 else
2982 gcc_unreachable ();
2983 break;
2984
2985 case CONST_DOUBLE:
2986 const REAL_VALUE_TYPE *rv;
2987 long val;
2988 gcc_assert (GET_MODE (x) == SFmode);
2989
2990 rv = CONST_DOUBLE_REAL_VALUE (x);
2991 REAL_VALUE_TO_TARGET_SINGLE (*rv, val);
2992
2993 fprintf (stream, "0x%lx", val);
2994 break;
2995
2996 case CODE_LABEL:
2997 case CONST_INT:
2998 case CONST:
2999 output_addr_const (stream, x);
3000 break;
3001
3002 default:
3003 /* Generally, output_addr_const () is able to handle most cases.
3004 We want to see what CODE could appear,
3005 so we use gcc_unreachable() to stop it. */
3006 debug_rtx (x);
3007 gcc_unreachable ();
3008 break;
3009 }
3010}
3011
3012static void
3013nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
3014{
3015 rtx op0, op1;
3016
3017 switch (GET_CODE (x))
3018 {
3019 case SYMBOL_REF:
3020 case CONST:
3021 /* [ + symbol_ref] */
3022 /* [ + const_addr], where const_addr = symbol_ref + const_int */
3023 fputs ("[ + ", stream);
3024 output_addr_const (stream, x);
3025 fputs ("]", stream);
3026 break;
3027
3028 case REG:
3029 /* Forbid using static chain register ($r16)
3030 on reduced-set registers configuration. */
3031 if (TARGET_REDUCED_REGS
3032 && REGNO (x) == STATIC_CHAIN_REGNUM)
3033 sorry ("a nested function is not supported for reduced registers");
3034
3035 /* [Ra] */
3036 fprintf (stream, "[%s]", reg_names[REGNO (x)]);
3037 break;
3038
3039 case PLUS:
3040 op0 = XEXP (x, 0);
3041 op1 = XEXP (x, 1);
3042
3043 /* Checking op0, forbid using static chain register ($r16)
3044 on reduced-set registers configuration. */
3045 if (TARGET_REDUCED_REGS
3046 && REG_P (op0)
3047 && REGNO (op0) == STATIC_CHAIN_REGNUM)
3048 sorry ("a nested function is not supported for reduced registers");
3049 /* Checking op1, forbid using static chain register ($r16)
3050 on reduced-set registers configuration. */
3051 if (TARGET_REDUCED_REGS
3052 && REG_P (op1)
3053 && REGNO (op1) == STATIC_CHAIN_REGNUM)
3054 sorry ("a nested function is not supported for reduced registers");
3055
3056 if (REG_P (op0) && CONST_INT_P (op1))
3057 {
3058 /* [Ra + imm] */
3059 fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]",
3060 reg_names[REGNO (op0)], INTVAL (op1));
3061 }
3062 else if (REG_P (op0) && REG_P (op1))
3063 {
3064 /* [Ra + Rb] */
3065 fprintf (stream, "[%s + %s]",
3066 reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
3067 }
3068 else if (GET_CODE (op0) == MULT && REG_P (op1))
3069 {
3070 /* [Ra + Rb << sv]
3071 From observation, the pattern looks like:
3072 (plus:SI (mult:SI (reg:SI 58)
3073 (const_int 4 [0x4]))
3074 (reg/f:SI 57)) */
3075 int sv;
3076
3077 /* We need to set sv to output shift value. */
3078 if (INTVAL (XEXP (op0, 1)) == 1)
3079 sv = 0;
3080 else if (INTVAL (XEXP (op0, 1)) == 2)
3081 sv = 1;
3082 else if (INTVAL (XEXP (op0, 1)) == 4)
3083 sv = 2;
3084 else if (INTVAL (XEXP (op0, 1)) == 8)
3085 sv = 3;
3086 else
3087 gcc_unreachable ();
3088
3089 fprintf (stream, "[%s + %s << %d]",
3090 reg_names[REGNO (op1)],
3091 reg_names[REGNO (XEXP (op0, 0))],
3092 sv);
3093 }
3094 else
3095 {
3096 /* The control flow is not supposed to be here. */
3097 debug_rtx (x);
3098 gcc_unreachable ();
3099 }
3100
3101 break;
3102
3103 case POST_MODIFY:
3104 /* (post_modify (regA) (plus (regA) (regB)))
3105 (post_modify (regA) (plus (regA) (const_int)))
3106 We would like to extract
3107 regA and regB (or const_int) from plus rtx. */
3108 op0 = XEXP (XEXP (x, 1), 0);
3109 op1 = XEXP (XEXP (x, 1), 1);
3110
3111 /* Checking op0, forbid using static chain register ($r16)
3112 on reduced-set registers configuration. */
3113 if (TARGET_REDUCED_REGS
3114 && REG_P (op0)
3115 && REGNO (op0) == STATIC_CHAIN_REGNUM)
3116 sorry ("a nested function is not supported for reduced registers");
3117 /* Checking op1, forbid using static chain register ($r16)
3118 on reduced-set registers configuration. */
3119 if (TARGET_REDUCED_REGS
3120 && REG_P (op1)
3121 && REGNO (op1) == STATIC_CHAIN_REGNUM)
3122 sorry ("a nested function is not supported for reduced registers");
3123
3124 if (REG_P (op0) && REG_P (op1))
3125 {
3126 /* [Ra], Rb */
3127 fprintf (stream, "[%s], %s",
3128 reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
3129 }
3130 else if (REG_P (op0) && CONST_INT_P (op1))
3131 {
3132 /* [Ra], imm */
3133 fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC,
3134 reg_names[REGNO (op0)], INTVAL (op1));
3135 }
3136 else
3137 {
3138 /* The control flow is not supposed to be here. */
3139 debug_rtx (x);
3140 gcc_unreachable ();
3141 }
3142
3143 break;
3144
3145 case POST_INC:
3146 case POST_DEC:
3147 op0 = XEXP (x, 0);
3148
3149 /* Checking op0, forbid using static chain register ($r16)
3150 on reduced-set registers configuration. */
3151 if (TARGET_REDUCED_REGS
3152 && REG_P (op0)
3153 && REGNO (op0) == STATIC_CHAIN_REGNUM)
3154 sorry ("a nested function is not supported for reduced registers");
3155
3156 if (REG_P (op0))
3157 {
3158 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
3159 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
3160 We only need to deal with register Ra. */
3161 fprintf (stream, "[%s]", reg_names[REGNO (op0)]);
3162 }
3163 else
3164 {
3165 /* The control flow is not supposed to be here. */
3166 debug_rtx (x);
3167 gcc_unreachable ();
3168 }
3169
3170 break;
3171
3172 default :
3173 /* Generally, output_addr_const () is able to handle most cases.
3174 We want to see what CODE could appear,
3175 so we use gcc_unreachable() to stop it. */
3176 debug_rtx (x);
3177 gcc_unreachable ();
3178 break;
3179 }
3180}
3181
3182/* -- Assembler Commands for Exception Regions. */
3183
3184static rtx
3185nds32_dwarf_register_span (rtx reg)
3186{
3187 rtx dwarf_high, dwarf_low;
3188 rtx dwarf_single;
3189 machine_mode mode;
3190 int regno;
3191
3192 mode = GET_MODE (reg);
3193 regno = REGNO (reg);
3194
3195 /* We need to adjust dwarf register information for floating-point registers
3196 rather than using default register number mapping. */
3197 if (regno >= NDS32_FIRST_FPR_REGNUM
3198 && regno <= NDS32_LAST_FPR_REGNUM)
3199 {
3200 if (mode == DFmode || mode == SCmode)
3201 {
3202 /* By default, GCC maps increasing register numbers to increasing
3203 memory locations, but paired FPRs in NDS32 target are always
3204 big-endian, i.e.:
3205
3206 fd0 : fs0 fs1
3207 (MSB) (LSB)
3208
3209 We must return parallel rtx to represent such layout. */
3210 dwarf_high = gen_rtx_REG (word_mode, regno);
3211 dwarf_low = gen_rtx_REG (word_mode, regno + 1);
3212 return gen_rtx_PARALLEL (VOIDmode,
3213 gen_rtvec (2, dwarf_low, dwarf_high));
3214 }
3215 else if (mode == DCmode)
3216 {
3217 rtx dwarf_high_re = gen_rtx_REG (word_mode, regno);
3218 rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1);
3219 rtx dwarf_high_im = gen_rtx_REG (word_mode, regno);
3220 rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1);
3221 return gen_rtx_PARALLEL (VOIDmode,
3222 gen_rtvec (4, dwarf_low_re, dwarf_high_re,
3223 dwarf_high_im, dwarf_low_im));
3224 }
3225 else if (mode == SFmode || mode == SImode)
3226 {
3227 /* Create new dwarf information with adjusted register number. */
3228 dwarf_single = gen_rtx_REG (word_mode, regno);
3229 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, dwarf_single));
3230 }
3231 else
3232 {
3233 /* We should not be here. */
3234 gcc_unreachable ();
3235 }
3236 }
3237
3238 return NULL_RTX;
3239}
3240
3241/* Map internal gcc register numbers to DWARF2 register numbers. */
3242
3243unsigned int
3244nds32_dbx_register_number (unsigned int regno)
3245{
3246 /* The nds32 port in GDB maintains a mapping between dwarf register
3247 number and displayed register name. For backward compatibility to
3248 previous toolchain, currently our gdb still has four registers
3249 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler
3250 does not count those four registers in its register number table.
3251 So we have to add 4 on its register number and then create new
3252 dwarf information. Hopefully we can discard such workaround
3253 in the future. */
3254 if (NDS32_IS_FPR_REGNUM (regno))
3255 return regno + 4;
3256
3257 return regno;
3258}
3259
3260\f
3261/* Defining target-specific uses of __attribute__. */
3262
3263/* Add some checking after merging attributes. */
3264static tree
3265nds32_merge_decl_attributes (tree olddecl, tree newdecl)
3266{
3267 tree combined_attrs;
3268
3269 /* Create combined attributes. */
3270 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl),
3271 DECL_ATTRIBUTES (newdecl));
3272
3273 /* Since newdecl is acutally a duplicate of olddecl,
3274 we can take olddecl for some operations. */
3275 if (TREE_CODE (olddecl) == FUNCTION_DECL)
3276 {
3277 /* Check isr-specific attributes conflict. */
3278 nds32_check_isr_attrs_conflict (olddecl, combined_attrs);
3279 }
3280
3281 return combined_attrs;
3282}
3283
3284/* Add some checking when inserting attributes. */
3285static void
3286nds32_insert_attributes (tree decl, tree *attributes)
3287{
3288 /* For function declaration, we need to check isr-specific attributes:
3289 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
3290 2. Check valid integer value for interrupt/exception.
3291 3. Check valid integer value for reset.
3292 4. Check valid function for nmi/warm. */
3293 if (TREE_CODE (decl) == FUNCTION_DECL)
3294 {
3295 tree func_attrs;
3296 tree intr, excp, reset;
3297
3298 /* Pick up function attributes. */
3299 func_attrs = *attributes;
3300
3301 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */
3302 nds32_check_isr_attrs_conflict (decl, func_attrs);
3303
3304 /* Now we are starting to check valid id value
3305 for interrupt/exception/reset.
3306 Note that we ONLY check its validity here.
3307 To construct isr vector information, it is still performed
3308 by nds32_construct_isr_vectors_information(). */
3309 intr = lookup_attribute ("interrupt", func_attrs);
3310 excp = lookup_attribute ("exception", func_attrs);
3311 reset = lookup_attribute ("reset", func_attrs);
3312
3313 if (intr || excp)
3314 {
3315 /* Deal with interrupt/exception. */
3316 tree id_list;
3317 unsigned int lower_bound, upper_bound;
3318
3319 /* The way to handle interrupt or exception is the same,
3320 we just need to take care of actual vector number.
3321 For interrupt(0..63), the actual vector number is (9..72).
3322 For exception(1..8), the actual vector number is (1..8). */
3323 lower_bound = (intr) ? (0) : (1);
3324 upper_bound = (intr) ? (63) : (8);
3325
3326 /* Prepare id list so that we can traverse id value. */
3327 id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp));
3328
3329 /* 2. Check valid integer value for interrupt/exception. */
3330 while (id_list)
3331 {
3332 tree id;
3333
3334 /* Pick up each vector id value. */
3335 id = TREE_VALUE (id_list);
3336 /* Issue error if it is not a valid integer value. */
3337 if (TREE_CODE (id) != INTEGER_CST
3338 || wi::ltu_p (wi::to_wide (id), lower_bound)
3339 || wi::gtu_p (wi::to_wide (id), upper_bound))
3340 error ("invalid id value for interrupt/exception attribute");
3341
3342 /* Advance to next id. */
3343 id_list = TREE_CHAIN (id_list);
3344 }
3345 }
3346 else if (reset)
3347 {
3348 /* Deal with reset. */
3349 tree id_list;
3350 tree id;
3351 tree nmi, warm;
3352 unsigned int lower_bound;
3353 unsigned int upper_bound;
3354
3355 /* Prepare id_list and identify id value so that
3356 we can check if total number of vectors is valid. */
3357 id_list = TREE_VALUE (reset);
3358 id = TREE_VALUE (id_list);
3359
3360 /* The maximum numbers for user's interrupt is 64. */
3361 lower_bound = 0;
3362 upper_bound = 64;
3363
3364 /* 3. Check valid integer value for reset. */
3365 if (TREE_CODE (id) != INTEGER_CST
3366 || wi::ltu_p (wi::to_wide (id), lower_bound)
3367 || wi::gtu_p (wi::to_wide (id), upper_bound))
3368 error ("invalid id value for reset attribute");
3369
3370 /* 4. Check valid function for nmi/warm. */
3371 nmi = lookup_attribute ("nmi", func_attrs);
3372 warm = lookup_attribute ("warm", func_attrs);
3373
3374 if (nmi != NULL_TREE)
3375 {
3376 tree nmi_func_list;
3377 tree nmi_func;
3378
3379 nmi_func_list = TREE_VALUE (nmi);
3380 nmi_func = TREE_VALUE (nmi_func_list);
3381
3382 /* Issue error if it is not a valid nmi function. */
3383 if (TREE_CODE (nmi_func) != IDENTIFIER_NODE)
3384 error ("invalid nmi function for reset attribute");
3385 }
3386
3387 if (warm != NULL_TREE)
3388 {
3389 tree warm_func_list;
3390 tree warm_func;
3391
3392 warm_func_list = TREE_VALUE (warm);
3393 warm_func = TREE_VALUE (warm_func_list);
3394
3395 /* Issue error if it is not a valid warm function. */
3396 if (TREE_CODE (warm_func) != IDENTIFIER_NODE)
3397 error ("invalid warm function for reset attribute");
3398 }
3399 }
3400 else
3401 {
3402 /* No interrupt, exception, or reset attribute is set. */
3403 return;
3404 }
3405 }
3406}
3407
3408static bool
3409nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED,
3410 tree pop_target ATTRIBUTE_UNUSED)
3411{
3412 /* Currently, we do not parse any pragma target by ourself,
3413 so just simply return false. */
3414 return false;
3415}
3416
3417static void
3418nds32_option_override (void)
3419{
3420 /* After all the command options have been parsed,
3421 we shall deal with some flags for changing compiler settings. */
3422
3423 /* At first, we check if we have to strictly
3424 set some flags based on ISA family. */
3425 if (TARGET_ISA_V2)
3426 {
3427 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
3428 target_flags &= ~MASK_V3PUSH;
3429 }
3430 if (TARGET_ISA_V3)
3431 {
3432 /* Under V3 ISA, currently nothing should be strictly set. */
3433 }
3434 if (TARGET_ISA_V3M)
3435 {
3436 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
3437 target_flags |= MASK_REDUCED_REGS;
3438 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
3439 target_flags &= ~MASK_EXT_PERF;
3440 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
3441 target_flags &= ~MASK_EXT_PERF2;
3442 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
3443 target_flags &= ~MASK_EXT_STRING;
3444 }
3445
3446 /* See if we are using reduced-set registers:
3447 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
3448 If so, we must forbid using $r11~$r14, $r16~$r27. */
3449 if (TARGET_REDUCED_REGS)
3450 {
3451 int r;
3452
3453 /* Prevent register allocator from
3454 choosing it as doing register allocation. */
3455 for (r = 11; r <= 14; r++)
3456 fixed_regs[r] = call_used_regs[r] = 1;
3457 for (r = 16; r <= 27; r++)
3458 fixed_regs[r] = call_used_regs[r] = 1;
3459 }
3460
3461 if (!TARGET_16_BIT)
3462 {
3463 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */
3464 target_flags &= ~MASK_V3PUSH;
3465 }
3466
3467 if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE))
3468 {
3469 if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F)
3470 error ("Disable FPU ISA, "
3471 "the ABI option must be enable '-mfloat-abi=soft'");
3472 else
3473 error ("'-mabi=2fp+' option only support when FPU available, "
3474 "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'");
3475 }
3476
3477 /* Currently, we don't support PIC code generation yet. */
3478 if (flag_pic)
3479 sorry ("position-independent code not supported");
3480
3481 nds32_register_passes ();
3482}
3483
3484\f
3485/* Miscellaneous Parameters. */
3486
3487static rtx_insn *
3488nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED,
3489 vec<rtx> &inputs ATTRIBUTE_UNUSED,
3490 vec<const char *> &constraints ATTRIBUTE_UNUSED,
3491 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3492{
3493 clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM));
3494 SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM);
3495 return NULL;
3496}
3497
3498static void
3499nds32_init_builtins (void)
3500{
3501 nds32_init_builtins_impl ();
3502}
3503
3504static tree
3505nds32_builtin_decl (unsigned code, bool initialize_p)
3506{
3507 /* Implement in nds32-intrinsic.c. */
3508 return nds32_builtin_decl_impl (code, initialize_p);
3509}
3510
3511static rtx
3512nds32_expand_builtin (tree exp,
3513 rtx target,
3514 rtx subtarget,
3515 machine_mode mode,
3516 int ignore)
3517{
3518 return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore);
3519}
3520
3521
3522/* ------------------------------------------------------------------------ */
3523
3524/* PART 4: Implemet extern function definitions,
3525 the prototype is in nds32-protos.h. */
3526\f
3527/* Run-time Target Specification. */
3528
3529void
3530nds32_cpu_cpp_builtins(struct cpp_reader *pfile)
3531{
3532#define builtin_define(TXT) cpp_define (pfile, TXT)
3533#define builtin_assert(TXT) cpp_assert (pfile, TXT)
3534 builtin_define ("__nds32__");
3535 builtin_define ("__NDS32__");
3536
3537 if (TARGET_HARD_FLOAT)
3538 builtin_define ("__NDS32_ABI_2FP_PLUS__");
3539 else
3540 builtin_define ("__NDS32_ABI_2__");
3541
3542 if (TARGET_ISA_V2)
3543 builtin_define ("__NDS32_ISA_V2__");
3544 if (TARGET_ISA_V3)
3545 builtin_define ("__NDS32_ISA_V3__");
3546 if (TARGET_ISA_V3M)
3547 builtin_define ("__NDS32_ISA_V3M__");
3548
3549 if (TARGET_FPU_SINGLE)
3550 builtin_define ("__NDS32_EXT_FPU_SP__");
3551 if (TARGET_FPU_DOUBLE)
3552 builtin_define ("__NDS32_EXT_FPU_DP__");
3553
3554 if (TARGET_EXT_FPU_FMA)
3555 builtin_define ("__NDS32_EXT_FPU_FMA__");
3556 if (NDS32_EXT_FPU_DOT_E)
3557 builtin_define ("__NDS32_EXT_FPU_DOT_E__");
3558 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
3559 {
3560 switch (nds32_fp_regnum)
3561 {
3562 case 0:
3563 case 4:
3564 builtin_define ("__NDS32_EXT_FPU_CONFIG_0__");
3565 break;
3566 case 1:
3567 case 5:
3568 builtin_define ("__NDS32_EXT_FPU_CONFIG_1__");
3569 break;
3570 case 2:
3571 case 6:
3572 builtin_define ("__NDS32_EXT_FPU_CONFIG_2__");
3573 break;
3574 case 3:
3575 case 7:
3576 builtin_define ("__NDS32_EXT_FPU_CONFIG_3__");
3577 break;
3578 default:
3579 abort ();
3580 }
3581 }
3582
3583 if (TARGET_BIG_ENDIAN)
3584 builtin_define ("__NDS32_EB__");
3585 else
3586 builtin_define ("__NDS32_EL__");
3587
3588 if (TARGET_REDUCED_REGS)
3589 builtin_define ("__NDS32_REDUCED_REGS__");
3590 if (TARGET_CMOV)
3591 builtin_define ("__NDS32_CMOV__");
3592 if (TARGET_EXT_PERF)
3593 builtin_define ("__NDS32_EXT_PERF__");
3594 if (TARGET_EXT_PERF2)
3595 builtin_define ("__NDS32_EXT_PERF2__");
3596 if (TARGET_EXT_STRING)
3597 builtin_define ("__NDS32_EXT_STRING__");
3598 if (TARGET_16_BIT)
3599 builtin_define ("__NDS32_16_BIT__");
3600 if (TARGET_GP_DIRECT)
3601 builtin_define ("__NDS32_GP_DIRECT__");
3602 if (TARGET_VH)
3603 builtin_define ("__NDS32_VH__");
3604
3605 if (TARGET_BIG_ENDIAN)
3606 builtin_define ("__big_endian__");
3607
3608 builtin_assert ("cpu=nds32");
3609 builtin_assert ("machine=nds32");
3610
3611 if (TARGET_HARD_FLOAT)
3612 builtin_define ("__NDS32_ABI_2FP_PLUS");
3613 else
3614 builtin_define ("__NDS32_ABI_2");
3615
3616#undef builtin_define
3617#undef builtin_assert
3618}
3619
3620\f
3621/* Defining Data Structures for Per-function Information. */
3622
3623void
3624nds32_init_expanders (void)
3625{
3626 /* Arrange to initialize and mark the machine per-function status. */
3627 init_machine_status = nds32_init_machine_status;
3628}
3629
3630\f
3631/* Register Usage. */
3632
3633/* -- Order of Allocation of Registers. */
3634
3635void
3636nds32_adjust_reg_alloc_order (void)
3637{
3638 const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER;
3639
3640 /* Copy the default register allocation order, which is designed
3641 to optimize for code size. */
3642 memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order));
3643
3644 /* Adjust few register allocation order when optimizing for speed. */
3645 if (!optimize_size)
3646 {
3647 memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed,
3648 sizeof (nds32_reg_alloc_order_for_speed));
3649 }
3650}
3651
3652/* -- How Values Fit in Registers. */
3653
3654static unsigned
3655nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED,
3656 machine_mode mode)
3657{
3658 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
3659}
3660
3661/* Implement TARGET_HARD_REGNO_MODE_OK. */
3662
3663static bool
3664nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
3665{
3666 if (regno > FIRST_PSEUDO_REGISTER)
3667 return true;
3668
3669 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno))
3670 {
3671 if (NDS32_IS_EXT_FPR_REGNUM(regno))
3672 return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode));
3673 else if (mode == SFmode || mode == SImode)
3674 return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno);
3675 else if (mode == DFmode)
3676 return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno);
3677
3678 return false;
3679 }
3680
3681 /* Restrict double-word quantities to even register pairs. */
3682 if (regno <= NDS32_LAST_GPR_REGNUM)
3683 return (targetm.hard_regno_nregs (regno, mode) == 1
3684 || !((regno) & 1));
3685
3686 return false;
3687}
3688
3689#undef TARGET_HARD_REGNO_MODE_OK
3690#define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
3691
3692/* Implement TARGET_MODES_TIEABLE_P. We can use general registers to
3693 tie QI/HI/SI modes together. */
3694
3695static bool
3696nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2)
3697{
3698 if ((GET_MODE_CLASS (mode1) == MODE_INT
3699 && GET_MODE_CLASS (mode2) == MODE_INT)
3700 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
3701 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
3702 return true;
3703
3704 if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2))
3705 {
3706 if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE)
3707 && (mode1 == DFmode || mode2 == DFmode))
3708 return false;
3709 else
3710 return true;
3711 }
3712
3713 return false;
3714}
3715
3716#undef TARGET_MODES_TIEABLE_P
3717#define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p
3718\f
3719/* Register Classes. */
3720
3721enum reg_class
3722nds32_regno_reg_class (int regno)
3723{
3724 /* Refer to nds32.h for more register class details. */
3725
3726 if (regno >= 0 && regno <= 7)
3727 return LOW_REGS;
3728 else if (regno >= 8 && regno <= 11)
3729 return MIDDLE_REGS;
3730 else if (regno >= 12 && regno <= 14)
3731 return HIGH_REGS;
3732 else if (regno == 15)
3733 return R15_TA_REG;
3734 else if (regno >= 16 && regno <= 19)
3735 return MIDDLE_REGS;
3736 else if (regno >= 20 && regno <= 31)
3737 return HIGH_REGS;
3738 else if (regno == 32 || regno == 33)
3739 {
3740 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't
3741 know how to allocate register for $SFP and $AP, just tell IRA they
3742 are GENERAL_REGS, and ARM do this hack too. */
3743 return GENERAL_REGS;
3744 }
3745 else if (regno >= 34 && regno <= 97)
3746 return FP_REGS;
3747 else
3748 return NO_REGS;
3749}
3750
3751\f
3752/* Stack Layout and Calling Conventions. */
3753
3754/* -- Basic Stack Layout. */
3755
3756rtx
3757nds32_return_addr_rtx (int count,
3758 rtx frameaddr ATTRIBUTE_UNUSED)
3759{
3760 /* There is no way to determine the return address
3761 if frameaddr is the frame that has 'count' steps
3762 up from current frame. */
3763 if (count != 0)
3764 return NULL_RTX;
3765
3766 /* If count == 0, it means we are at current frame,
3767 the return address is $r30 ($lp). */
3768 return get_hard_reg_initial_val (Pmode, LP_REGNUM);
3769}
3770
3771/* -- Eliminating Frame Pointer and Arg Pointer. */
3772
3773HOST_WIDE_INT
3774nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg)
3775{
3776 HOST_WIDE_INT offset;
3777
3778 /* Compute and setup stack frame size.
3779 The result will be in cfun->machine. */
3780 nds32_compute_stack_frame ();
3781
3782 /* Remember to consider
3783 cfun->machine->callee_saved_area_gpr_padding_bytes
3784 when calculating offset. */
3785 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
3786 {
3787 offset = (cfun->machine->fp_size
3788 + cfun->machine->gp_size
3789 + cfun->machine->lp_size
3790 + cfun->machine->callee_saved_gpr_regs_size
3791 + cfun->machine->callee_saved_area_gpr_padding_bytes
3792 + cfun->machine->callee_saved_fpr_regs_size
3793 + cfun->machine->local_size
3794 + cfun->machine->out_args_size);
3795 }
3796 else if (from_reg == ARG_POINTER_REGNUM
3797 && to_reg == HARD_FRAME_POINTER_REGNUM)
3798 {
3799 offset = 0;
3800 }
3801 else if (from_reg == FRAME_POINTER_REGNUM
3802 && to_reg == STACK_POINTER_REGNUM)
3803 {
3804 offset = (cfun->machine->local_size + cfun->machine->out_args_size);
3805 }
3806 else if (from_reg == FRAME_POINTER_REGNUM
3807 && to_reg == HARD_FRAME_POINTER_REGNUM)
3808 {
3809 offset = (-1) * (cfun->machine->fp_size
3810 + cfun->machine->gp_size
3811 + cfun->machine->lp_size
3812 + cfun->machine->callee_saved_gpr_regs_size
3813 + cfun->machine->callee_saved_area_gpr_padding_bytes
3814 + cfun->machine->callee_saved_fpr_regs_size);
3815 }
3816 else
3817 {
3818 gcc_unreachable ();
3819 }
3820
3821 return offset;
3822}
3823
3824/* -- Passing Arguments in Registers. */
3825
3826void
3827nds32_init_cumulative_args (CUMULATIVE_ARGS *cum,
3828 tree fntype ATTRIBUTE_UNUSED,
3829 rtx libname ATTRIBUTE_UNUSED,
3830 tree fndecl ATTRIBUTE_UNUSED,
3831 int n_named_args ATTRIBUTE_UNUSED)
3832{
3833 /* Initial available registers. The values are offset against
3834 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM
3835 for passing arguments. */
3836 cum->gpr_offset = 0;
3837 cum->fpr_offset = 0;
3838}
3839
3840/* -- Function Entry and Exit. */
3841
3842/* Function for normal multiple push prologue. */
3843void
3844nds32_expand_prologue (void)
3845{
3846 int fp_adjust;
3847 int sp_adjust;
3848 unsigned Rb, Re;
3849
3850 /* Compute and setup stack frame size.
3851 The result will be in cfun->machine. */
3852 nds32_compute_stack_frame ();
3853
3854 /* If this is a variadic function, first we need to push argument
3855 registers that hold the unnamed argument value. */
3856 if (cfun->machine->va_args_size != 0)
3857 {
3858 Rb = cfun->machine->va_args_first_regno;
3859 Re = cfun->machine->va_args_last_regno;
3860 /* No need to push $fp, $gp, or $lp. */
3861 nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true);
3862
3863 /* We may also need to adjust stack pointer for padding bytes
3864 because varargs may cause $sp not 8-byte aligned. */
3865 if (cfun->machine->va_args_area_padding_bytes)
3866 {
3867 /* Generate sp adjustment instruction. */
3868 sp_adjust = cfun->machine->va_args_area_padding_bytes;
3869
3870 nds32_emit_adjust_frame (stack_pointer_rtx,
3871 stack_pointer_rtx,
3872 -1 * sp_adjust);
3873 }
3874 }
3875
3876 /* If the function is 'naked',
3877 we do not have to generate prologue code fragment. */
3878 if (cfun->machine->naked_p)
3879 return;
3880
3881 /* Get callee_first_regno and callee_last_regno. */
3882 Rb = cfun->machine->callee_saved_first_gpr_regno;
3883 Re = cfun->machine->callee_saved_last_gpr_regno;
3884
3885 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
3886 to be saved, we don't have to create multiple push instruction.
3887 Otherwise, a multiple push instruction is needed. */
3888 if (!(Rb == SP_REGNUM && Re == SP_REGNUM
3889 && cfun->machine->fp_size == 0
3890 && cfun->machine->gp_size == 0
3891 && cfun->machine->lp_size == 0))
3892 {
3893 /* Create multiple push instruction rtx. */
3894 nds32_emit_stack_push_multiple (
3895 Rb, Re,
3896 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size,
3897 false);
3898 }
3899
3900 /* Check frame_pointer_needed to see
3901 if we shall emit fp adjustment instruction. */
3902 if (frame_pointer_needed)
3903 {
3904 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
3905 + (4 * callee-saved-registers)
3906 Note: No need to adjust
3907 cfun->machine->callee_saved_area_gpr_padding_bytes,
3908 because, at this point, stack pointer is just
3909 at the position after push instruction. */
3910 fp_adjust = cfun->machine->fp_size
3911 + cfun->machine->gp_size
3912 + cfun->machine->lp_size
3913 + cfun->machine->callee_saved_gpr_regs_size;
3914
3915 nds32_emit_adjust_frame (hard_frame_pointer_rtx,
3916 stack_pointer_rtx,
3917 fp_adjust);
3918 }
3919
3920 /* Save fpu registers. */
3921 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
3922 {
3923 /* When $sp moved to bottom of stack, we need to check whether
3924 the range of offset in the FPU instruction. */
3925 int fpr_offset = cfun->machine->local_size
3926 + cfun->machine->out_args_size
3927 + cfun->machine->callee_saved_fpr_regs_size;
3928
3929 /* Check FPU instruction offset imm14s. */
3930 if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset)))
3931 {
3932 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
3933 + cfun->machine->callee_saved_fpr_regs_size;
3934
3935 /* Save fpu registers, need to allocate stack space
3936 for fpu callee registers. And now $sp position
3937 on callee saved fpr registers. */
3938 nds32_emit_adjust_frame (stack_pointer_rtx,
3939 stack_pointer_rtx,
3940 -1 * fpr_space);
3941
3942 /* Emit fpu store instruction, using [$sp + offset] store
3943 fpu registers. */
3944 nds32_emit_push_fpr_callee_saved (0);
3945
3946 /* Adjust $sp = $sp - local_size - out_args_size. */
3947 sp_adjust = cfun->machine->local_size
3948 + cfun->machine->out_args_size;
3949
3950 /* Allocate stack space for local size and out args size. */
3951 nds32_emit_adjust_frame (stack_pointer_rtx,
3952 stack_pointer_rtx,
3953 -1 * sp_adjust);
3954 }
3955 else
3956 {
3957 /* Offset range in Is14, so $sp moved to bottom of stack. */
3958
3959 /* Adjust $sp = $sp - local_size - out_args_size
3960 - callee_saved_area_gpr_padding_bytes
3961 - callee_saved_fpr_regs_size. */
3962 sp_adjust = cfun->machine->local_size
3963 + cfun->machine->out_args_size
3964 + cfun->machine->callee_saved_area_gpr_padding_bytes
3965 + cfun->machine->callee_saved_fpr_regs_size;
3966
3967 nds32_emit_adjust_frame (stack_pointer_rtx,
3968 stack_pointer_rtx,
3969 -1 * sp_adjust);
3970
3971 /* Emit fpu store instruction, using [$sp + offset] store
3972 fpu registers. */
3973 int fpr_position = cfun->machine->out_args_size
3974 + cfun->machine->local_size;
3975 nds32_emit_push_fpr_callee_saved (fpr_position);
3976 }
3977 }
3978 else
3979 {
3980 /* Adjust $sp = $sp - local_size - out_args_size
3981 - callee_saved_area_gpr_padding_bytes. */
3982 sp_adjust = cfun->machine->local_size
3983 + cfun->machine->out_args_size
3984 + cfun->machine->callee_saved_area_gpr_padding_bytes;
3985
3986 /* sp_adjust value may be out of range of the addi instruction,
3987 create alternative add behavior with TA_REGNUM if necessary,
3988 using NEGATIVE value to tell that we are decreasing address. */
3989 nds32_emit_adjust_frame (stack_pointer_rtx,
3990 stack_pointer_rtx,
3991 -1 * sp_adjust);
3992 }
3993
3994 /* Prevent the instruction scheduler from
3995 moving instructions across the boundary. */
3996 emit_insn (gen_blockage ());
3997}
3998
3999/* Function for normal multiple pop epilogue. */
4000void
4001nds32_expand_epilogue (bool sibcall_p)
4002{
4003 int sp_adjust;
4004 unsigned Rb, Re;
4005
4006 /* Compute and setup stack frame size.
4007 The result will be in cfun->machine. */
4008 nds32_compute_stack_frame ();
4009
4010 /* Prevent the instruction scheduler from
4011 moving instructions across the boundary. */
4012 emit_insn (gen_blockage ());
4013
4014 /* If the function is 'naked', we do not have to generate
4015 epilogue code fragment BUT 'ret' instruction.
4016 However, if this function is also a variadic function,
4017 we need to create adjust stack pointer before 'ret' instruction. */
4018 if (cfun->machine->naked_p)
4019 {
4020 /* If this is a variadic function, we do not have to restore argument
4021 registers but need to adjust stack pointer back to previous stack
4022 frame location before return. */
4023 if (cfun->machine->va_args_size != 0)
4024 {
4025 /* Generate sp adjustment instruction.
4026 We need to consider padding bytes here. */
4027 sp_adjust = cfun->machine->va_args_size
4028 + cfun->machine->va_args_area_padding_bytes;
4029
4030 nds32_emit_adjust_frame (stack_pointer_rtx,
4031 stack_pointer_rtx,
4032 sp_adjust);
4033 }
4034
4035 /* Generate return instruction by using 'return_internal' pattern.
4036 Make sure this instruction is after gen_blockage(). */
4037 if (!sibcall_p)
4038 emit_jump_insn (gen_return_internal ());
4039 return;
4040 }
4041
4042 if (frame_pointer_needed)
4043 {
4044 /* Restore fpu registers. */
4045 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4046 {
4047 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes;
4048
4049 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4050 - (4 * callee-saved-registers)
4051 - (4 * exception-handling-data-registers)
4052 - (4 * callee-saved-gpr-registers padding byte)
4053 - (4 * callee-saved-fpr-registers)
4054 Note: we want to adjust stack pointer
4055 to the position for callee-saved fpr register,
4056 And restore fpu register use .bi instruction to adjust $sp
4057 from callee-saved fpr register to pop instruction. */
4058 sp_adjust = cfun->machine->fp_size
4059 + cfun->machine->gp_size
4060 + cfun->machine->lp_size
4061 + cfun->machine->callee_saved_gpr_regs_size
4062 + cfun->machine->callee_saved_area_gpr_padding_bytes
4063 + cfun->machine->callee_saved_fpr_regs_size;
4064
4065 nds32_emit_adjust_frame (stack_pointer_rtx,
4066 hard_frame_pointer_rtx,
4067 -1 * sp_adjust);
4068
4069 /* Emit fpu load instruction, using .bi instruction
4070 load fpu registers. */
4071 nds32_emit_pop_fpr_callee_saved (gpr_padding);
4072 }
4073 else
4074 {
4075 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4076 - (4 * callee-saved-registers)
4077 - (4 * exception-handling-data-registers)
4078 Note: No need to adjust
4079 cfun->machine->callee_saved_area_gpr_padding_bytes,
4080 because we want to adjust stack pointer
4081 to the position for pop instruction. */
4082 sp_adjust = cfun->machine->fp_size
4083 + cfun->machine->gp_size
4084 + cfun->machine->lp_size
4085 + cfun->machine->callee_saved_gpr_regs_size;
4086
4087 nds32_emit_adjust_frame (stack_pointer_rtx,
4088 hard_frame_pointer_rtx,
4089 -1 * sp_adjust);
4090 }
4091 }
4092 else
4093 {
4094 /* Restore fpu registers. */
4095 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4096 {
4097 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes;
4098
4099 /* Adjust $sp = $sp + local_size + out_args_size. */
4100 sp_adjust = cfun->machine->local_size
4101 + cfun->machine->out_args_size;
4102
4103 nds32_emit_adjust_frame (stack_pointer_rtx,
4104 stack_pointer_rtx,
4105 sp_adjust);
4106
4107 /* Emit fpu load instruction, using .bi instruction
4108 load fpu registers, and adjust $sp from callee-saved fpr register
4109 to callee-saved gpr register. */
4110 nds32_emit_pop_fpr_callee_saved (gpr_padding);
4111 }
4112 else
4113 {
4114 /* If frame pointer is NOT needed,
4115 we cannot calculate the sp adjustment from frame pointer.
4116 Instead, we calculate the adjustment by local_size,
4117 out_args_size, and callee_saved_area_gpr_padding_bytes.
4118 Notice that such sp adjustment value may be out of range,
4119 so we have to deal with it as well. */
4120
4121 /* Adjust $sp = $sp + local_size + out_args_size
4122 + callee_saved_area_gpr_padding_bytes. */
4123 sp_adjust = cfun->machine->local_size
4124 + cfun->machine->out_args_size
4125 + cfun->machine->callee_saved_area_gpr_padding_bytes;
4126
4127 nds32_emit_adjust_frame (stack_pointer_rtx,
4128 stack_pointer_rtx,
4129 sp_adjust);
4130 }
4131 }
4132
4133 /* Get callee_first_regno and callee_last_regno. */
4134 Rb = cfun->machine->callee_saved_first_gpr_regno;
4135 Re = cfun->machine->callee_saved_last_gpr_regno;
4136
4137 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4138 to be saved, we don't have to create multiple pop instruction.
4139 Otherwise, a multiple pop instruction is needed. */
4140 if (!(Rb == SP_REGNUM && Re == SP_REGNUM
4141 && cfun->machine->fp_size == 0
4142 && cfun->machine->gp_size == 0
4143 && cfun->machine->lp_size == 0))
4144 {
4145 /* Create multiple pop instruction rtx. */
4146 nds32_emit_stack_pop_multiple (
4147 Rb, Re,
4148 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size);
4149 }
4150
4151 /* If this is a variadic function, we do not have to restore argument
4152 registers but need to adjust stack pointer back to previous stack
4153 frame location before return. */
4154 if (cfun->machine->va_args_size != 0)
4155 {
4156 /* Generate sp adjustment instruction.
4157 We need to consider padding bytes here. */
4158 sp_adjust = cfun->machine->va_args_size
4159 + cfun->machine->va_args_area_padding_bytes;
4160
4161 nds32_emit_adjust_frame (stack_pointer_rtx,
4162 stack_pointer_rtx,
4163 sp_adjust);
4164 }
4165
4166 /* Generate return instruction. */
4167 if (!sibcall_p)
4168 emit_jump_insn (gen_return_internal ());
4169}
4170
4171/* Function for v3push prologue. */
4172void
4173nds32_expand_prologue_v3push (void)
4174{
4175 int fp_adjust;
4176 int sp_adjust;
4177 int fpr_space = 0;
4178 unsigned Rb, Re;
4179
4180 /* Compute and setup stack frame size.
4181 The result will be in cfun->machine. */
4182 nds32_compute_stack_frame ();
4183
4184 if (cfun->machine->callee_saved_gpr_regs_size > 0)
4185 df_set_regs_ever_live (FP_REGNUM, 1);
4186
4187 /* If the function is 'naked',
4188 we do not have to generate prologue code fragment. */
4189 if (cfun->machine->naked_p)
4190 return;
4191
4192 /* Get callee_first_regno and callee_last_regno. */
4193 Rb = cfun->machine->callee_saved_first_gpr_regno;
4194 Re = cfun->machine->callee_saved_last_gpr_regno;
4195
4196 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
4197 where imm8u has to be 8-byte alignment. */
4198 sp_adjust = cfun->machine->local_size
4199 + cfun->machine->out_args_size
4200 + cfun->machine->callee_saved_area_gpr_padding_bytes
4201 + cfun->machine->callee_saved_fpr_regs_size;
4202
4203 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
4204 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
4205 {
4206 /* We can use 'push25 Re,imm8u'. */
4207
4208 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
4209 the pattern 'stack_v3push' is implemented in nds32.md. */
4210 nds32_emit_stack_v3push (Rb, Re, sp_adjust);
4211
4212 /* Save fpu registers. */
4213 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4214 {
4215 /* Calculate fpr position. */
4216 int fpr_position = cfun->machine->local_size
4217 + cfun->machine->out_args_size;
4218 /* Emit fpu store instruction, using [$sp + offset] store
4219 fpu registers. */
4220 nds32_emit_push_fpr_callee_saved (fpr_position);
4221 }
4222
4223 /* Check frame_pointer_needed to see
4224 if we shall emit fp adjustment instruction. */
4225 if (frame_pointer_needed)
4226 {
4227 /* adjust $fp = $sp + 4 ($fp size)
4228 + 4 ($gp size)
4229 + 4 ($lp size)
4230 + (4 * n) (callee-saved registers)
4231 + sp_adjust ('push25 Re,imm8u')
4232 Note: Since we use 'push25 Re,imm8u',
4233 the position of stack pointer is further
4234 changed after push instruction.
4235 Hence, we need to take sp_adjust value
4236 into consideration. */
4237 fp_adjust = cfun->machine->fp_size
4238 + cfun->machine->gp_size
4239 + cfun->machine->lp_size
4240 + cfun->machine->callee_saved_gpr_regs_size
4241 + sp_adjust;
4242
4243 nds32_emit_adjust_frame (hard_frame_pointer_rtx,
4244 stack_pointer_rtx,
4245 fp_adjust);
4246 }
4247 }
4248 else
4249 {
4250 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4251 {
4252 /* Calculate fpr space. */
4253 fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
4254 + cfun->machine->callee_saved_fpr_regs_size;
4255
4256 /* We have to use 'push25 Re, fpr_space', to pre-allocate
4257 callee saved fpr registers space. */
4258 nds32_emit_stack_v3push (Rb, Re, fpr_space);
4259 nds32_emit_push_fpr_callee_saved (0);
4260 }
4261 else
4262 {
4263 /* We have to use 'push25 Re,0' and
4264 expand one more instruction to adjust $sp later. */
4265
4266 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
4267 the pattern 'stack_v3push' is implemented in nds32.md. */
4268 nds32_emit_stack_v3push (Rb, Re, 0);
4269 }
4270
4271 /* Check frame_pointer_needed to see
4272 if we shall emit fp adjustment instruction. */
4273 if (frame_pointer_needed)
4274 {
4275 /* adjust $fp = $sp + 4 ($fp size)
4276 + 4 ($gp size)
4277 + 4 ($lp size)
4278 + (4 * n) (callee-saved registers)
4279 Note: Since we use 'push25 Re,0',
4280 the stack pointer is just at the position
4281 after push instruction.
4282 No need to take sp_adjust into consideration. */
4283 fp_adjust = cfun->machine->fp_size
4284 + cfun->machine->gp_size
4285 + cfun->machine->lp_size
4286 + cfun->machine->callee_saved_gpr_regs_size;
4287
4288 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4289 {
4290 /* We use 'push25 Re, fpr_space', the $sp is
4291 on callee saved fpr position, so need to consider
4292 fpr space. */
4293 fp_adjust = fp_adjust + fpr_space;
4294 }
4295
4296 nds32_emit_adjust_frame (hard_frame_pointer_rtx,
4297 stack_pointer_rtx,
4298 fp_adjust);
4299 }
4300
4301 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4302 {
4303 /* We use 'push25 Re, fpr_space',
4304 the $sp is on callee saved fpr position,
4305 no need to consider fpr space. */
4306 sp_adjust = sp_adjust - fpr_space;
4307 }
4308
4309 /* Because we use 'push25 Re,0',
4310 we need to expand one more instruction to adjust $sp.
4311 using NEGATIVE value to tell that we are decreasing address. */
4312 nds32_emit_adjust_frame (stack_pointer_rtx,
4313 stack_pointer_rtx,
4314 -1 * sp_adjust);
4315 }
4316
4317 /* Prevent the instruction scheduler from
4318 moving instructions across the boundary. */
4319 emit_insn (gen_blockage ());
4320}
4321
4322/* Function for v3pop epilogue. */
4323void
4324nds32_expand_epilogue_v3pop (bool sibcall_p)
4325{
4326 int sp_adjust;
4327 unsigned Rb, Re;
4328
4329 /* Compute and setup stack frame size.
4330 The result will be in cfun->machine. */
4331 nds32_compute_stack_frame ();
4332
4333 /* Prevent the instruction scheduler from
4334 moving instructions across the boundary. */
4335 emit_insn (gen_blockage ());
4336
4337 /* If the function is 'naked', we do not have to generate
4338 epilogue code fragment BUT 'ret' instruction. */
4339 if (cfun->machine->naked_p)
4340 {
4341 /* Generate return instruction by using 'return_internal' pattern.
4342 Make sure this instruction is after gen_blockage(). */
4343 if (!sibcall_p)
4344 emit_jump_insn (gen_return_internal ());
4345 return;
4346 }
4347
4348 /* Get callee_first_regno and callee_last_regno. */
4349 Rb = cfun->machine->callee_saved_first_gpr_regno;
4350 Re = cfun->machine->callee_saved_last_gpr_regno;
4351
4352 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
4353 where imm8u has to be 8-byte alignment. */
4354 sp_adjust = cfun->machine->local_size
4355 + cfun->machine->out_args_size
4356 + cfun->machine->callee_saved_area_gpr_padding_bytes
4357 + cfun->machine->callee_saved_fpr_regs_size;
4358
4359 /* We have to consider alloca issue as well.
4360 If the function does call alloca(), the stack pointer is not fixed.
4361 In that case, we cannot use 'pop25 Re,imm8u' directly.
4362 We have to caculate stack pointer from frame pointer
4363 and then use 'pop25 Re,0'.
4364 Of course, the frame_pointer_needed should be nonzero
4365 if the function calls alloca(). */
4366 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
4367 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
4368 && !cfun->calls_alloca)
4369 {
4370 /* Restore fpu registers. */
4371 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4372 {
4373 int fpr_position = cfun->machine->local_size
4374 + cfun->machine->out_args_size;
4375 /* Emit fpu load instruction, using [$sp + offset] restore
4376 fpu registers. */
4377 nds32_emit_v3pop_fpr_callee_saved (fpr_position);
4378 }
4379
4380 /* We can use 'pop25 Re,imm8u'. */
4381
4382 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
4383 the pattern 'stack_v3pop' is implementad in nds32.md. */
4384 nds32_emit_stack_v3pop (Rb, Re, sp_adjust);
4385 }
4386 else
4387 {
4388 /* We have to use 'pop25 Re,0', and prior to it,
4389 we must expand one more instruction to adjust $sp. */
4390
4391 if (frame_pointer_needed)
4392 {
4393 /* adjust $sp = $fp - 4 ($fp size)
4394 - 4 ($gp size)
4395 - 4 ($lp size)
4396 - (4 * n) (callee-saved registers)
4397 Note: No need to adjust
4398 cfun->machine->callee_saved_area_gpr_padding_bytes,
4399 because we want to adjust stack pointer
4400 to the position for pop instruction. */
4401 sp_adjust = cfun->machine->fp_size
4402 + cfun->machine->gp_size
4403 + cfun->machine->lp_size
4404 + cfun->machine->callee_saved_gpr_regs_size;
4405
4406 /* Restore fpu registers. */
4407 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4408 {
4409 /* Set $sp to callee saved fpr position, we need to restore
4410 fpr registers. */
4411 sp_adjust = sp_adjust
4412 + cfun->machine->callee_saved_area_gpr_padding_bytes
4413 + cfun->machine->callee_saved_fpr_regs_size;
4414
4415 nds32_emit_adjust_frame (stack_pointer_rtx,
4416 hard_frame_pointer_rtx,
4417 -1 * sp_adjust);
4418
4419 /* Emit fpu load instruction, using [$sp + offset] restore
4420 fpu registers. */
4421 nds32_emit_v3pop_fpr_callee_saved (0);
4422 }
4423 else
4424 {
4425 nds32_emit_adjust_frame (stack_pointer_rtx,
4426 hard_frame_pointer_rtx,
4427 -1 * sp_adjust);
4428 }
4429 }
4430 else
4431 {
4432 /* If frame pointer is NOT needed,
4433 we cannot calculate the sp adjustment from frame pointer.
4434 Instead, we calculate the adjustment by local_size,
4435 out_args_size, and callee_saved_area_padding_bytes.
4436 Notice that such sp adjustment value may be out of range,
4437 so we have to deal with it as well. */
4438
4439 /* Adjust $sp = $sp + local_size + out_args_size
4440 + callee_saved_area_gpr_padding_bytes
4441 + callee_saved_fpr_regs_size. */
4442 sp_adjust = cfun->machine->local_size
4443 + cfun->machine->out_args_size
4444 + cfun->machine->callee_saved_area_gpr_padding_bytes
4445 + cfun->machine->callee_saved_fpr_regs_size;
4446
4447 /* Restore fpu registers. */
4448 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4449 {
4450 /* Set $sp to callee saved fpr position, we need to restore
4451 fpr registers. */
4452 sp_adjust = sp_adjust
4453 - cfun->machine->callee_saved_area_gpr_padding_bytes
4454 - cfun->machine->callee_saved_fpr_regs_size;
4455
4456 nds32_emit_adjust_frame (stack_pointer_rtx,
4457 stack_pointer_rtx,
4458 sp_adjust);
4459
4460 /* Emit fpu load instruction, using [$sp + offset] restore
4461 fpu registers. */
4462 nds32_emit_v3pop_fpr_callee_saved (0);
4463 }
4464 else
4465 {
4466 /* sp_adjust value may be out of range of the addi instruction,
4467 create alternative add behavior with TA_REGNUM if necessary,
4468 using POSITIVE value to tell that we are increasing
4469 address. */
4470 nds32_emit_adjust_frame (stack_pointer_rtx,
4471 stack_pointer_rtx,
4472 sp_adjust);
4473 }
4474 }
4475
4476 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)
4477 {
4478 /* We have fpr need to restore, so $sp is set on callee saved fpr
4479 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */
4480 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes
4481 + cfun->machine->callee_saved_fpr_regs_size;
4482 nds32_emit_stack_v3pop (Rb, Re, fpr_space);
4483 }
4484 else
4485 {
4486 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
4487 the pattern 'stack_v3pop' is implementad in nds32.md. */
4488 nds32_emit_stack_v3pop (Rb, Re, 0);
4489 }
4490 }
4491 /* Generate return instruction. */
4492 emit_jump_insn (gen_pop25return ());
4493}
4494
4495/* Return nonzero if this function is known to have a null epilogue.
4496 This allows the optimizer to omit jumps to jumps if no stack
4497 was created. */
4498int
4499nds32_can_use_return_insn (void)
4500{
4501 int sp_adjust;
4502
4503 /* Prior to reloading, we can't tell how many registers must be saved.
4504 Thus we can not determine whether this function has null epilogue. */
4505 if (!reload_completed)
4506 return 0;
4507
4508 sp_adjust = cfun->machine->local_size
4509 + cfun->machine->out_args_size
4510 + cfun->machine->callee_saved_area_gpr_padding_bytes
4511 + cfun->machine->callee_saved_fpr_regs_size;
4512 if (!cfun->machine->fp_as_gp_p
4513 && satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
4514 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
4515 && !cfun->calls_alloca
4516 && NDS32_V3PUSH_AVAILABLE_P
4517 && !(TARGET_HARD_FLOAT
4518 && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM)))
4519 return 1;
4520
4521 /* If no stack was created, two conditions must be satisfied:
4522 1. This is a naked function.
4523 So there is no callee-saved, local size, or outgoing size.
4524 2. This is NOT a variadic function.
4525 So there is no pushing arguement registers into the stack. */
4526 return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0));
4527}
4528
4529/* ------------------------------------------------------------------------ */
4530
4531/* Function to test 333-form for load/store instructions.
4532 This is auxiliary extern function for auxiliary macro in nds32.h.
4533 Because it is a little complicated, we use function instead of macro. */
4534bool
4535nds32_ls_333_p (rtx rt, rtx ra, rtx imm, machine_mode mode)
4536{
4537 if (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS
4538 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
4539 {
4540 if (GET_MODE_SIZE (mode) == 4)
4541 return satisfies_constraint_Iu05 (imm);
4542
4543 if (GET_MODE_SIZE (mode) == 2)
4544 return satisfies_constraint_Iu04 (imm);
4545
4546 if (GET_MODE_SIZE (mode) == 1)
4547 return satisfies_constraint_Iu03 (imm);
4548 }
4549
4550 return false;
4551}
4552
4553bool
4554nds32_split_double_word_load_store_p(rtx *operands, bool load_p)
4555{
4556 rtx mem = load_p ? operands[1] : operands[0];
4557 /* Do split at split2 if -O0 or schedule 2 not enable. */
4558 if (optimize == 0 || !flag_schedule_insns_after_reload)
4559 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem);
4560
4561 /* Split double word load store after copy propgation. */
4562 if (current_pass == NULL)
4563 return false;
4564
4565 const char *pass_name = current_pass->name;
4566 if (pass_name && ((strcmp (pass_name, "split4") == 0)
4567 || (strcmp (pass_name, "split5") == 0)))
4568 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem);
4569
4570 return false;
4571}
4572
4573static bool
4574nds32_use_blocks_for_constant_p (machine_mode mode,
4575 const_rtx x ATTRIBUTE_UNUSED)
4576{
4577 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
4578 && (mode == DFmode || mode == SFmode))
4579 return true;
4580 else
4581 return false;
4582}
4583
4584/* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */
4585int
4586nds32_target_alignment (rtx_insn *label)
4587{
4588 rtx_insn *insn;
4589
4590 if (optimize_size)
4591 return 0;
4592
4593 insn = next_active_insn (label);
4594
4595 if (insn == 0)
4596 return 0;
4597 else if ((get_attr_length (insn) % 4) == 0)
4598 return 2;
4599 else
4600 return 0;
4601}
4602
4603/* ------------------------------------------------------------------------ */
4604
4605/* PART 5: Initialize target hook structure and definitions. */
4606\f
4607/* Controlling the Compilation Driver. */
4608
4609\f
4610/* Run-time Target Specification. */
4611
4612\f
4613/* Defining Data Structures for Per-function Information. */
4614
4615\f
4616/* Storage Layout. */
4617
4618#undef TARGET_PROMOTE_FUNCTION_MODE
4619#define TARGET_PROMOTE_FUNCTION_MODE \
4620 default_promote_function_mode_always_promote
4621
4622\f
4623/* Layout of Source Language Data Types. */
4624
4625\f
4626/* Register Usage. */
4627
4628/* -- Basic Characteristics of Registers. */
4629
4630#undef TARGET_CONDITIONAL_REGISTER_USAGE
4631#define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage
4632
4633/* -- Order of Allocation of Registers. */
4634
4635/* -- How Values Fit in Registers. */
4636
4637#undef TARGET_HARD_REGNO_NREGS
4638#define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs
4639
4640/* -- Handling Leaf Functions. */
4641
4642/* -- Registers That Form a Stack. */
4643
4644\f
4645/* Register Classes. */
4646
4647#undef TARGET_CLASS_MAX_NREGS
4648#define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
4649
4650#undef TARGET_REGISTER_PRIORITY
4651#define TARGET_REGISTER_PRIORITY nds32_register_priority
4652
4653#undef TARGET_CAN_CHANGE_MODE_CLASS
4654#define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class
4655
4656\f
4657/* Obsolete Macros for Defining Constraints. */
4658
4659\f
4660/* Stack Layout and Calling Conventions. */
4661
4662/* -- Basic Stack Layout. */
4663
4664/* -- Exception Handling Support. */
4665
4666/* -- Specifying How Stack Checking is Done. */
4667
4668/* -- Registers That Address the Stack Frame. */
4669
4670/* -- Eliminating Frame Pointer and Arg Pointer. */
4671
4672#undef TARGET_CAN_ELIMINATE
4673#define TARGET_CAN_ELIMINATE nds32_can_eliminate
4674
4675/* -- Passing Function Arguments on the Stack. */
4676
4677/* -- Passing Arguments in Registers. */
4678
4679#undef TARGET_FUNCTION_ARG
4680#define TARGET_FUNCTION_ARG nds32_function_arg
4681
4682#undef TARGET_MUST_PASS_IN_STACK
4683#define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack
4684
4685#undef TARGET_ARG_PARTIAL_BYTES
4686#define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes
4687
4688#undef TARGET_FUNCTION_ARG_ADVANCE
4689#define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
4690
4691#undef TARGET_FUNCTION_ARG_BOUNDARY
4692#define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
4693
4694/* -- How Scalar Function Values Are Returned. */
4695
4696#undef TARGET_FUNCTION_VALUE
4697#define TARGET_FUNCTION_VALUE nds32_function_value
4698
4699#undef TARGET_LIBCALL_VALUE
4700#define TARGET_LIBCALL_VALUE nds32_libcall_value
4701
4702#undef TARGET_FUNCTION_VALUE_REGNO_P
4703#define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
4704
4705/* -- How Large Values Are Returned. */
4706
4707#undef TARGET_RETURN_IN_MEMORY
4708#define TARGET_RETURN_IN_MEMORY nds32_return_in_memory
4709
4710/* -- Caller-Saves Register Allocation. */
4711
4712/* -- Function Entry and Exit. */
4713
4714#undef TARGET_ASM_FUNCTION_PROLOGUE
4715#define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
4716
4717#undef TARGET_ASM_FUNCTION_END_PROLOGUE
4718#define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
4719
4720#undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
4721#define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
4722
4723#undef TARGET_ASM_FUNCTION_EPILOGUE
4724#define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
4725
4726#undef TARGET_ASM_OUTPUT_MI_THUNK
4727#define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
4728
4729#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
4730#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
4731
4732/* -- Generating Code for Profiling. */
4733
4734/* -- Permitting tail calls. */
4735
4736#undef TARGET_FUNCTION_OK_FOR_SIBCALL
4737#define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall
4738
4739#undef TARGET_WARN_FUNC_RETURN
4740#define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
4741
4742/* Stack smashing protection. */
4743
4744\f
4745/* Implementing the Varargs Macros. */
4746
4747#undef TARGET_SETUP_INCOMING_VARARGS
4748#define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
4749
4750#undef TARGET_STRICT_ARGUMENT_NAMING
4751#define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
4752
4753\f
4754/* Trampolines for Nested Functions. */
4755
4756#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
4757#define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
4758
4759#undef TARGET_TRAMPOLINE_INIT
4760#define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
4761
4762\f
4763/* Implicit Calls to Library Routines. */
4764
4765\f
4766/* Addressing Modes. */
4767
4768#undef TARGET_LEGITIMATE_ADDRESS_P
4769#define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
4770
4771\f
4772/* Anchored Addresses. */
4773
4774\f
4775/* Condition Code Status. */
4776
4777/* -- Representation of condition codes using (cc0). */
4778
4779/* -- Representation of condition codes using registers. */
4780
4781#undef TARGET_CANONICALIZE_COMPARISON
4782#define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison
4783
4784/* -- Macros to control conditional execution. */
4785
4786\f
4787/* Describing Relative Costs of Operations. */
4788
4789#undef TARGET_REGISTER_MOVE_COST
4790#define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
4791
4792#undef TARGET_MEMORY_MOVE_COST
4793#define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
4794
4795#undef TARGET_RTX_COSTS
4796#define TARGET_RTX_COSTS nds32_rtx_costs
4797
4798#undef TARGET_ADDRESS_COST
4799#define TARGET_ADDRESS_COST nds32_address_cost
4800
4801\f
4802/* Adjusting the Instruction Scheduler. */
4803
4804\f
4805/* Dividing the Output into Sections (Texts, Data, . . . ). */
4806
4807#undef TARGET_ENCODE_SECTION_INFO
4808#define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info
4809
4810\f
4811/* Position Independent Code. */
4812
4813\f
4814/* Defining the Output Assembler Language. */
4815
4816/* -- The Overall Framework of an Assembler File. */
4817
4818#undef TARGET_ASM_FILE_START
4819#define TARGET_ASM_FILE_START nds32_asm_file_start
4820#undef TARGET_ASM_FILE_END
4821#define TARGET_ASM_FILE_END nds32_asm_file_end
4822
4823/* -- Output of Data. */
4824
4825#undef TARGET_ASM_ALIGNED_HI_OP
4826#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
4827
4828#undef TARGET_ASM_ALIGNED_SI_OP
4829#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
4830
4831/* -- Output of Uninitialized Variables. */
4832
4833/* -- Output and Generation of Labels. */
4834
4835#undef TARGET_ASM_GLOBALIZE_LABEL
4836#define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
4837
4838/* -- How Initialization Functions Are Handled. */
4839
4840/* -- Macros Controlling Initialization Routines. */
4841
4842/* -- Output of Assembler Instructions. */
4843
4844#undef TARGET_PRINT_OPERAND
4845#define TARGET_PRINT_OPERAND nds32_print_operand
4846#undef TARGET_PRINT_OPERAND_ADDRESS
4847#define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
4848
4849/* -- Output of Dispatch Tables. */
4850
4851/* -- Assembler Commands for Exception Regions. */
4852
4853#undef TARGET_DWARF_REGISTER_SPAN
4854#define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span
4855
4856/* -- Assembler Commands for Alignment. */
4857
4858\f
4859/* Controlling Debugging Information Format. */
4860
4861/* -- Macros Affecting All Debugging Formats. */
4862
4863/* -- Specific Options for DBX Output. */
4864
4865/* -- Open-Ended Hooks for DBX Format. */
4866
4867/* -- File Names in DBX Format. */
4868
4869/* -- Macros for DWARF Output. */
4870
4871/* -- Macros for VMS Debug Format. */
4872
4873\f
4874/* Cross Compilation and Floating Point. */
4875
4876\f
4877/* Mode Switching Instructions. */
4878
4879\f
4880/* Defining target-specific uses of __attribute__. */
4881
4882#undef TARGET_ATTRIBUTE_TABLE
4883#define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
4884
4885#undef TARGET_MERGE_DECL_ATTRIBUTES
4886#define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
4887
4888#undef TARGET_INSERT_ATTRIBUTES
4889#define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
4890
4891#undef TARGET_OPTION_PRAGMA_PARSE
4892#define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
4893
4894#undef TARGET_OPTION_OVERRIDE
4895#define TARGET_OPTION_OVERRIDE nds32_option_override
4896
4897\f
4898/* Emulating TLS. */
4899
4900\f
4901/* Defining coprocessor specifics for MIPS targets. */
4902
4903\f
4904/* Parameters for Precompiled Header Validity Checking. */
4905
4906\f
4907/* C++ ABI parameters. */
4908
4909\f
4910/* Adding support for named address spaces. */
4911
4912\f
4913/* Miscellaneous Parameters. */
4914
4915#undef TARGET_MD_ASM_ADJUST
4916#define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust
4917
4918#undef TARGET_INIT_BUILTINS
4919#define TARGET_INIT_BUILTINS nds32_init_builtins
4920
4921#undef TARGET_BUILTIN_DECL
4922#define TARGET_BUILTIN_DECL nds32_builtin_decl
4923
4924#undef TARGET_EXPAND_BUILTIN
4925#define TARGET_EXPAND_BUILTIN nds32_expand_builtin
4926
4927
4928#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
4929#define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p
4930
4931\f
4932/* ------------------------------------------------------------------------ */
4933
4934/* Initialize the GCC target structure. */
4935
4936struct gcc_target targetm = TARGET_INITIALIZER;
4937
4938/* ------------------------------------------------------------------------ */
Mirror of https://gcc.gnu.org/git/gcc.git