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1 | ;; Machine description for RISC-V for GNU compiler. | |
2 | ;; Copyright (C) 2011-2022 Free Software Foundation, Inc. | |
3 | ;; Contributed by Andrew Waterman (andrew@sifive.com). | |
4 | ;; Based on MIPS target for GNU compiler. | |
5 | ||
6 | ;; This file is part of GCC. | |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 3, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | ||
23 | ;; Keep this list and the one above riscv_print_operand in sync. | |
24 | ;; The special asm out single letter directives following a '%' are: | |
25 | ;; h -- Print the high-part relocation associated with OP, after stripping | |
26 | ;; any outermost HIGH. | |
27 | ;; R -- Print the low-part relocation associated with OP. | |
28 | ;; C -- Print the integer branch condition for comparison OP. | |
29 | ;; A -- Print the atomic operation suffix for memory model OP. | |
30 | ;; F -- Print a FENCE if the memory model requires a release. | |
31 | ;; z -- Print x0 if OP is zero, otherwise print OP normally. | |
32 | ;; i -- Print i if the operand is not a register. | |
33 | ;; S -- Print shift-index of single-bit mask OP. | |
34 | ;; T -- Print shift-index of inverted single-bit mask OP. | |
35 | ;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. | |
36 | ||
37 | (define_c_enum "unspec" [ | |
38 | ;; Override return address for exception handling. | |
39 | UNSPEC_EH_RETURN | |
40 | ||
41 | ;; Symbolic accesses. The order of this list must match that of | |
42 | ;; enum riscv_symbol_type in riscv-protos.h. | |
43 | UNSPEC_ADDRESS_FIRST | |
44 | UNSPEC_PCREL | |
45 | UNSPEC_LOAD_GOT | |
46 | UNSPEC_TLS | |
47 | UNSPEC_TLS_LE | |
48 | UNSPEC_TLS_IE | |
49 | UNSPEC_TLS_GD | |
50 | ||
51 | ;; High part of PC-relative address. | |
52 | UNSPEC_AUIPC | |
53 | ||
54 | ;; Floating-point unspecs. | |
55 | UNSPEC_FLT_QUIET | |
56 | UNSPEC_FLE_QUIET | |
57 | UNSPEC_COPYSIGN | |
58 | UNSPEC_LRINT | |
59 | UNSPEC_LROUND | |
60 | UNSPEC_FMIN | |
61 | UNSPEC_FMAX | |
62 | ||
63 | ;; Stack tie | |
64 | UNSPEC_TIE | |
65 | ||
66 | ;; OR-COMBINE | |
67 | UNSPEC_ORC_B | |
68 | ]) | |
69 | ||
70 | (define_c_enum "unspecv" [ | |
71 | ;; Register save and restore. | |
72 | UNSPECV_GPR_SAVE | |
73 | UNSPECV_GPR_RESTORE | |
74 | ||
75 | ;; Floating-point unspecs. | |
76 | UNSPECV_FRFLAGS | |
77 | UNSPECV_FSFLAGS | |
78 | UNSPECV_FSNVSNAN | |
79 | ||
80 | ;; Interrupt handler instructions. | |
81 | UNSPECV_MRET | |
82 | UNSPECV_SRET | |
83 | UNSPECV_URET | |
84 | ||
85 | ;; Blockage and synchronization. | |
86 | UNSPECV_BLOCKAGE | |
87 | UNSPECV_FENCE | |
88 | UNSPECV_FENCE_I | |
89 | ||
90 | ;; Stack Smash Protector | |
91 | UNSPEC_SSP_SET | |
92 | UNSPEC_SSP_TEST | |
93 | ||
94 | ;; CMO instructions. | |
95 | UNSPECV_CLEAN | |
96 | UNSPECV_FLUSH | |
97 | UNSPECV_INVAL | |
98 | UNSPECV_ZERO | |
99 | UNSPECV_PREI | |
100 | ||
101 | ;; Zihintpause unspec | |
102 | UNSPECV_PAUSE | |
103 | ]) | |
104 | ||
105 | (define_constants | |
106 | [(RETURN_ADDR_REGNUM 1) | |
107 | (GP_REGNUM 3) | |
108 | (TP_REGNUM 4) | |
109 | (T0_REGNUM 5) | |
110 | (T1_REGNUM 6) | |
111 | (S0_REGNUM 8) | |
112 | (S1_REGNUM 9) | |
113 | (S2_REGNUM 18) | |
114 | (S3_REGNUM 19) | |
115 | (S4_REGNUM 20) | |
116 | (S5_REGNUM 21) | |
117 | (S6_REGNUM 22) | |
118 | (S7_REGNUM 23) | |
119 | (S8_REGNUM 24) | |
120 | (S9_REGNUM 25) | |
121 | (S10_REGNUM 26) | |
122 | (S11_REGNUM 27) | |
123 | ||
124 | (NORMAL_RETURN 0) | |
125 | (SIBCALL_RETURN 1) | |
126 | (EXCEPTION_RETURN 2) | |
127 | (VL_REGNUM 66) | |
128 | (VTYPE_REGNUM 67) | |
129 | ]) | |
130 | ||
131 | (include "predicates.md") | |
132 | (include "constraints.md") | |
133 | (include "iterators.md") | |
134 | ||
135 | ;; .................... | |
136 | ;; | |
137 | ;; Attributes | |
138 | ;; | |
139 | ;; .................... | |
140 | ||
141 | (define_attr "got" "unset,xgot_high,load" | |
142 | (const_string "unset")) | |
143 | ||
144 | ;; Classification of moves, extensions and truncations. Most values | |
145 | ;; are as for "type" (see below) but there are also the following | |
146 | ;; move-specific values: | |
147 | ;; | |
148 | ;; andi a single ANDI instruction | |
149 | ;; shift_shift a shift left followed by a shift right | |
150 | ;; | |
151 | ;; This attribute is used to determine the instruction's length and | |
152 | ;; scheduling type. For doubleword moves, the attribute always describes | |
153 | ;; the split instructions; in some cases, it is more appropriate for the | |
154 | ;; scheduling type to be "multi" instead. | |
155 | (define_attr "move_type" | |
156 | "unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove, | |
157 | const,logical,arith,andi,shift_shift,rdvlenb" | |
158 | (const_string "unknown")) | |
159 | ||
160 | ;; Main data type used by the insn | |
161 | (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF, | |
162 | VNx1BI,VNx2BI,VNx4BI,VNx8BI,VNx16BI,VNx32BI,VNx64BI, | |
163 | VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI, | |
164 | VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI, | |
165 | VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI, | |
166 | VNx1DI,VNx2DI,VNx4DI,VNx8DI, | |
167 | VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF, | |
168 | VNx1DF,VNx2DF,VNx4DF,VNx8DF" | |
169 | (const_string "unknown")) | |
170 | ||
171 | ;; True if the main data type is twice the size of a word. | |
172 | (define_attr "dword_mode" "no,yes" | |
173 | (cond [(and (eq_attr "mode" "DI,DF") | |
174 | (eq (symbol_ref "TARGET_64BIT") (const_int 0))) | |
175 | (const_string "yes") | |
176 | ||
177 | (and (eq_attr "mode" "TI,TF") | |
178 | (ne (symbol_ref "TARGET_64BIT") (const_int 0))) | |
179 | (const_string "yes")] | |
180 | (const_string "no"))) | |
181 | ||
182 | ;; ISA attributes. | |
183 | (define_attr "ext" "base,f,d,vector" | |
184 | (const_string "base")) | |
185 | ||
186 | ;; True if the extension is enabled. | |
187 | (define_attr "ext_enabled" "no,yes" | |
188 | (cond [(eq_attr "ext" "base") | |
189 | (const_string "yes") | |
190 | ||
191 | (and (eq_attr "ext" "f") | |
192 | (match_test "TARGET_HARD_FLOAT")) | |
193 | (const_string "yes") | |
194 | ||
195 | (and (eq_attr "ext" "d") | |
196 | (match_test "TARGET_DOUBLE_FLOAT")) | |
197 | (const_string "yes") | |
198 | ||
199 | (and (eq_attr "ext" "vector") | |
200 | (match_test "TARGET_VECTOR")) | |
201 | (const_string "yes") | |
202 | ] | |
203 | (const_string "no"))) | |
204 | ||
205 | ;; Attribute to control enable or disable instructions. | |
206 | (define_attr "enabled" "no,yes" | |
207 | (cond [(eq_attr "ext_enabled" "no") | |
208 | (const_string "no")] | |
209 | (const_string "yes"))) | |
210 | ||
211 | ;; Classification of each insn. | |
212 | ;; branch conditional branch | |
213 | ;; jump unconditional jump | |
214 | ;; call unconditional call | |
215 | ;; load load instruction(s) | |
216 | ;; fpload floating point load | |
217 | ;; store store instruction(s) | |
218 | ;; fpstore floating point store | |
219 | ;; mtc transfer to coprocessor | |
220 | ;; mfc transfer from coprocessor | |
221 | ;; const load constant | |
222 | ;; arith integer arithmetic instructions | |
223 | ;; auipc integer addition to PC | |
224 | ;; logical integer logical instructions | |
225 | ;; shift integer shift instructions | |
226 | ;; slt set less than instructions | |
227 | ;; imul integer multiply | |
228 | ;; idiv integer divide | |
229 | ;; move integer register move (addi rd, rs1, 0) | |
230 | ;; fmove floating point register move | |
231 | ;; fadd floating point add/subtract | |
232 | ;; fmul floating point multiply | |
233 | ;; fmadd floating point multiply-add | |
234 | ;; fdiv floating point divide | |
235 | ;; fcmp floating point compare | |
236 | ;; fcvt floating point convert | |
237 | ;; fsqrt floating point square root | |
238 | ;; multi multiword sequence (or user asm statements) | |
239 | ;; nop no operation | |
240 | ;; ghost an instruction that produces no real code | |
241 | ;; bitmanip bit manipulation instructions | |
242 | ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. | |
243 | ;; rdvlenb vector byte length vlenb csrr read | |
244 | ;; rdvl vector length vl csrr read | |
245 | ;; vsetvl vector configuration-setting instrucions | |
246 | ;; 7. Vector Loads and Stores | |
247 | ;; vlde vector unit-stride load instructions | |
248 | ;; vste vector unit-stride store instructions | |
249 | ;; vldm vector unit-stride mask load instructions | |
250 | ;; vstm vector unit-stride mask store instructions | |
251 | ;; vlds vector strided load instructions | |
252 | ;; vsts vector strided store instructions | |
253 | ;; vldux vector unordered indexed load instructions | |
254 | ;; vldox vector ordered indexed load instructions | |
255 | ;; vstux vector unordered indexed store instructions | |
256 | ;; vstox vector ordered indexed store instructions | |
257 | ;; vldff vector unit-stride fault-only-first load instructions | |
258 | ;; vldr vector whole register load instructions | |
259 | ;; vstr vector whole register store instructions | |
260 | ;; 11. Vector integer arithmetic instructions | |
261 | ;; vialu vector single-width integer add and subtract and logical nstructions | |
262 | ;; viwalu vector widening integer add/subtract | |
263 | ;; vext vector integer extension | |
264 | ;; vicalu vector arithmetic with carry or borrow instructions | |
265 | ;; vshift vector single-width bit shift instructions | |
266 | ;; vnshift vector narrowing integer shift instructions | |
267 | ;; vicmp vector integer comparison/min/max instructions | |
268 | ;; vimul vector single-width integer multiply instructions | |
269 | ;; vidiv vector single-width integer divide instructions | |
270 | ;; viwmul vector widening integer multiply instructions | |
271 | ;; vimuladd vector single-width integer multiply-add instructions | |
272 | ;; viwmuladd vector widening integer multiply-add instructions | |
273 | ;; vimerge vector integer merge instructions | |
274 | ;; vimov vector integer move vector instructions | |
275 | ;; 12. Vector fixed-point arithmetic instructions | |
276 | ;; vsalu vector single-width saturating add and subtract and logical instructions | |
277 | ;; vaalu vector single-width averaging add and subtract and logical instructions | |
278 | ;; vsmul vector single-width fractional multiply with rounding and saturation instructions | |
279 | ;; vsshift vector single-width scaling shift instructions | |
280 | ;; vnclip vector narrowing fixed-point clip instructions | |
281 | ;; 13. Vector floating-point instructions | |
282 | ;; vfalu vector single-width floating-point add/subtract instructions | |
283 | ;; vfwalu vector widening floating-point add/subtract instructions | |
284 | ;; vfmul vector single-width floating-point multiply instructions | |
285 | ;; vfdiv vector single-width floating-point divide instructions | |
286 | ;; vfwmul vector widening floating-point multiply instructions | |
287 | ;; vfmuladd vector single-width floating-point multiply-add instructions | |
288 | ;; vfwmuladd vector widening floating-point multiply-add instructions | |
289 | ;; vfsqrt vector floating-point square-root instructions | |
290 | ;; vfrecp vector floating-point reciprocal square-root instructions | |
291 | ;; vfcmp vector floating-point comparison/min/max instructions | |
292 | ;; vfsgnj vector floating-point sign-injection instructions | |
293 | ;; vfclass vector floating-point classify instruction | |
294 | ;; vfmerge vector floating-point merge instruction | |
295 | ;; vfmov vector floating-point move instruction | |
296 | ;; vfcvtitof vector single-width integer to floating-point instruction | |
297 | ;; vfcvtftoi vector single-width floating-point to integer instruction | |
298 | ;; vfwcvtitof vector widening integer to floating-point instruction | |
299 | ;; vfwcvtftoi vector widening floating-point to integer instruction | |
300 | ;; vfwcvtftof vector widening floating-point to floating-point instruction | |
301 | ;; vfncvtitof vector narrowing integer to floating-point instruction | |
302 | ;; vfncvtftoi vector narrowing floating-point to integer instruction | |
303 | ;; vfncvtftof vector narrowing floating-point to floating-point instruction | |
304 | ;; 14. Vector reduction operations | |
305 | ;; vired vector single-width integer reduction instructions | |
306 | ;; viwred vector widening integer reduction instructions | |
307 | ;; vfred vector single-width floating-point un-ordered reduction instruction | |
308 | ;; vfredo vector single-width floating-point ordered reduction instruction | |
309 | ;; vfwred vector widening floating-point un-ordered reduction instruction | |
310 | ;; vfwredo vector widening floating-point ordered reduction instruction | |
311 | ;; 15. Vector mask instructions | |
312 | ;; vmalu vector mask-register logical instructions | |
313 | ;; vmpop vector mask population count | |
314 | ;; vmffs vector find-first-set mask bit | |
315 | ;; vmsfs vector set mask bit | |
316 | ;; vmiota vector iota | |
317 | ;; vmidx vector element index instruction | |
318 | ;; 16. Vector permutation instructions | |
319 | ;; vimovvx integer scalar move instructions | |
320 | ;; vimovxv integer scalar move instructions | |
321 | ;; vfmovvf floating-point scalar move instructions | |
322 | ;; vfmovfv floating-point scalar move instructions | |
323 | ;; vislide vector slide instructions | |
324 | ;; vislide1 vector slide instructions | |
325 | ;; vfslide1 vector slide instructions | |
326 | ;; vgather vector register gather instructions | |
327 | ;; vcompress vector compress instruction | |
328 | ;; vmov whole vector register move | |
329 | (define_attr "type" | |
330 | "unknown,branch,jump,call,load,fpload,store,fpstore, | |
331 | mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, | |
332 | fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, | |
333 | atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, | |
334 | vldux,vldox,vstux,vstox,vldff,vldr,vstr, | |
335 | vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, | |
336 | vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, | |
337 | vsalu,vaalu,vsmul,vsshift,vnclip, | |
338 | vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp, | |
339 | vfcmp,vfsgnj,vfclass,vfmerge,vfmov, | |
340 | vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi, | |
341 | vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof, | |
342 | vired,viwred,vfred,vfredo,vfwred,vfwredo, | |
343 | vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, | |
344 | vislide,vislide1,vfslide1,vgather,vcompress,vmov" | |
345 | (cond [(eq_attr "got" "load") (const_string "load") | |
346 | ||
347 | ;; If a doubleword move uses these expensive instructions, | |
348 | ;; it is usually better to schedule them in the same way | |
349 | ;; as the singleword form, rather than as "multi". | |
350 | (eq_attr "move_type" "load") (const_string "load") | |
351 | (eq_attr "move_type" "fpload") (const_string "fpload") | |
352 | (eq_attr "move_type" "store") (const_string "store") | |
353 | (eq_attr "move_type" "fpstore") (const_string "fpstore") | |
354 | (eq_attr "move_type" "mtc") (const_string "mtc") | |
355 | (eq_attr "move_type" "mfc") (const_string "mfc") | |
356 | ||
357 | ;; These types of move are always single insns. | |
358 | (eq_attr "move_type" "fmove") (const_string "fmove") | |
359 | (eq_attr "move_type" "arith") (const_string "arith") | |
360 | (eq_attr "move_type" "logical") (const_string "logical") | |
361 | (eq_attr "move_type" "andi") (const_string "logical") | |
362 | ||
363 | ;; These types of move are always split. | |
364 | (eq_attr "move_type" "shift_shift") | |
365 | (const_string "multi") | |
366 | ||
367 | ;; These types of move are split for doubleword modes only. | |
368 | (and (eq_attr "move_type" "move,const") | |
369 | (eq_attr "dword_mode" "yes")) | |
370 | (const_string "multi") | |
371 | (eq_attr "move_type" "move") (const_string "move") | |
372 | (eq_attr "move_type" "const") (const_string "const") | |
373 | (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] | |
374 | (const_string "unknown"))) | |
375 | ||
376 | ;; Length of instruction in bytes. | |
377 | (define_attr "length" "" | |
378 | (cond [ | |
379 | ;; Branches further than +/- 4 KiB require two instructions. | |
380 | (eq_attr "type" "branch") | |
381 | (if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 4088)) | |
382 | (le (minus (pc) (match_dup 0)) (const_int 4092))) | |
383 | (const_int 4) | |
384 | (const_int 8)) | |
385 | ||
386 | ;; Conservatively assume calls take two instructions (AUIPC + JALR). | |
387 | ;; The linker will opportunistically relax the sequence to JAL. | |
388 | (eq_attr "type" "call") (const_int 8) | |
389 | ||
390 | ;; "Ghost" instructions occupy no space. | |
391 | (eq_attr "type" "ghost") (const_int 0) | |
392 | ||
393 | (eq_attr "got" "load") (const_int 8) | |
394 | ||
395 | ;; SHIFT_SHIFTs are decomposed into two separate instructions. | |
396 | (eq_attr "move_type" "shift_shift") | |
397 | (const_int 8) | |
398 | ||
399 | ;; Check for doubleword moves that are decomposed into two | |
400 | ;; instructions. | |
401 | (and (eq_attr "move_type" "mtc,mfc,move") | |
402 | (eq_attr "dword_mode" "yes")) | |
403 | (const_int 8) | |
404 | ||
405 | ;; Doubleword CONST{,N} moves are split into two word | |
406 | ;; CONST{,N} moves. | |
407 | (and (eq_attr "move_type" "const") | |
408 | (eq_attr "dword_mode" "yes")) | |
409 | (symbol_ref "riscv_split_const_insns (operands[1]) * 4") | |
410 | ||
411 | ;; Otherwise, constants, loads and stores are handled by external | |
412 | ;; routines. | |
413 | (eq_attr "move_type" "load,fpload") | |
414 | (symbol_ref "riscv_load_store_insns (operands[1], insn) * 4") | |
415 | (eq_attr "move_type" "store,fpstore") | |
416 | (symbol_ref "riscv_load_store_insns (operands[0], insn) * 4") | |
417 | ] (const_int 4))) | |
418 | ||
419 | ;; Is copying of this instruction disallowed? | |
420 | (define_attr "cannot_copy" "no,yes" (const_string "no")) | |
421 | ||
422 | ;; Microarchitectures we know how to tune for. | |
423 | ;; Keep this in sync with enum riscv_microarchitecture. | |
424 | (define_attr "tune" | |
425 | "generic,sifive_7" | |
426 | (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) | |
427 | ||
428 | ;; Describe a user's asm statement. | |
429 | (define_asm_attributes | |
430 | [(set_attr "type" "multi")]) | |
431 | ||
432 | ;; Ghost instructions produce no real code and introduce no hazards. | |
433 | ;; They exist purely to express an effect on dataflow. | |
434 | (define_insn_reservation "ghost" 0 | |
435 | (eq_attr "type" "ghost") | |
436 | "nothing") | |
437 | ||
438 | ;; | |
439 | ;; .................... | |
440 | ;; | |
441 | ;; ADDITION | |
442 | ;; | |
443 | ;; .................... | |
444 | ;; | |
445 | ||
446 | (define_insn "add<mode>3" | |
447 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
448 | (plus:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
449 | (match_operand:ANYF 2 "register_operand" " f")))] | |
450 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
451 | "fadd.<fmt>\t%0,%1,%2" | |
452 | [(set_attr "type" "fadd") | |
453 | (set_attr "mode" "<UNITMODE>")]) | |
454 | ||
455 | (define_insn "addsi3" | |
456 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
457 | (plus:SI (match_operand:SI 1 "register_operand" " r,r") | |
458 | (match_operand:SI 2 "arith_operand" " r,I")))] | |
459 | "" | |
460 | "add%i2%~\t%0,%1,%2" | |
461 | [(set_attr "type" "arith") | |
462 | (set_attr "mode" "SI")]) | |
463 | ||
464 | (define_insn "adddi3" | |
465 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
466 | (plus:DI (match_operand:DI 1 "register_operand" " r,r") | |
467 | (match_operand:DI 2 "arith_operand" " r,I")))] | |
468 | "TARGET_64BIT" | |
469 | "add%i2\t%0,%1,%2" | |
470 | [(set_attr "type" "arith") | |
471 | (set_attr "mode" "DI")]) | |
472 | ||
473 | (define_expand "addv<mode>4" | |
474 | [(set (match_operand:GPR 0 "register_operand" "=r,r") | |
475 | (plus:GPR (match_operand:GPR 1 "register_operand" " r,r") | |
476 | (match_operand:GPR 2 "arith_operand" " r,I"))) | |
477 | (label_ref (match_operand 3 "" ""))] | |
478 | "" | |
479 | { | |
480 | if (TARGET_64BIT && <MODE>mode == SImode) | |
481 | { | |
482 | rtx t3 = gen_reg_rtx (DImode); | |
483 | rtx t4 = gen_reg_rtx (DImode); | |
484 | rtx t5 = gen_reg_rtx (DImode); | |
485 | rtx t6 = gen_reg_rtx (DImode); | |
486 | ||
487 | emit_insn (gen_addsi3 (operands[0], operands[1], operands[2])); | |
488 | if (GET_CODE (operands[1]) != CONST_INT) | |
489 | emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0)); | |
490 | else | |
491 | t4 = operands[1]; | |
492 | if (GET_CODE (operands[2]) != CONST_INT) | |
493 | emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0)); | |
494 | else | |
495 | t5 = operands[2]; | |
496 | emit_insn (gen_adddi3 (t3, t4, t5)); | |
497 | emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0)); | |
498 | ||
499 | riscv_expand_conditional_branch (operands[3], NE, t6, t3); | |
500 | } | |
501 | else | |
502 | { | |
503 | rtx t3 = gen_reg_rtx (<MODE>mode); | |
504 | rtx t4 = gen_reg_rtx (<MODE>mode); | |
505 | ||
506 | emit_insn (gen_add3_insn (operands[0], operands[1], operands[2])); | |
507 | rtx cmp1 = gen_rtx_LT (<MODE>mode, operands[2], const0_rtx); | |
508 | emit_insn (gen_cstore<mode>4 (t3, cmp1, operands[2], const0_rtx)); | |
509 | rtx cmp2 = gen_rtx_LT (<MODE>mode, operands[0], operands[1]); | |
510 | ||
511 | emit_insn (gen_cstore<mode>4 (t4, cmp2, operands[0], operands[1])); | |
512 | riscv_expand_conditional_branch (operands[3], NE, t3, t4); | |
513 | } | |
514 | DONE; | |
515 | }) | |
516 | ||
517 | (define_expand "uaddv<mode>4" | |
518 | [(set (match_operand:GPR 0 "register_operand" "=r,r") | |
519 | (plus:GPR (match_operand:GPR 1 "register_operand" " r,r") | |
520 | (match_operand:GPR 2 "arith_operand" " r,I"))) | |
521 | (label_ref (match_operand 3 "" ""))] | |
522 | "" | |
523 | { | |
524 | if (TARGET_64BIT && <MODE>mode == SImode) | |
525 | { | |
526 | rtx t3 = gen_reg_rtx (DImode); | |
527 | rtx t4 = gen_reg_rtx (DImode); | |
528 | ||
529 | if (GET_CODE (operands[1]) != CONST_INT) | |
530 | emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0)); | |
531 | else | |
532 | t3 = operands[1]; | |
533 | emit_insn (gen_addsi3 (operands[0], operands[1], operands[2])); | |
534 | emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0)); | |
535 | ||
536 | riscv_expand_conditional_branch (operands[3], LTU, t4, t3); | |
537 | } | |
538 | else | |
539 | { | |
540 | emit_insn (gen_add3_insn (operands[0], operands[1], operands[2])); | |
541 | riscv_expand_conditional_branch (operands[3], LTU, operands[0], | |
542 | operands[1]); | |
543 | } | |
544 | ||
545 | DONE; | |
546 | }) | |
547 | ||
548 | (define_insn "*addsi3_extended" | |
549 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
550 | (sign_extend:DI | |
551 | (plus:SI (match_operand:SI 1 "register_operand" " r,r") | |
552 | (match_operand:SI 2 "arith_operand" " r,I"))))] | |
553 | "TARGET_64BIT" | |
554 | "add%i2w\t%0,%1,%2" | |
555 | [(set_attr "type" "arith") | |
556 | (set_attr "mode" "SI")]) | |
557 | ||
558 | (define_insn "*addsi3_extended2" | |
559 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
560 | (sign_extend:DI | |
561 | (match_operator:SI 3 "subreg_lowpart_operator" | |
562 | [(plus:DI (match_operand:DI 1 "register_operand" " r,r") | |
563 | (match_operand:DI 2 "arith_operand" " r,I"))])))] | |
564 | "TARGET_64BIT" | |
565 | "add%i2w\t%0,%1,%2" | |
566 | [(set_attr "type" "arith") | |
567 | (set_attr "mode" "SI")]) | |
568 | ||
569 | ;; | |
570 | ;; .................... | |
571 | ;; | |
572 | ;; SUBTRACTION | |
573 | ;; | |
574 | ;; .................... | |
575 | ;; | |
576 | ||
577 | (define_insn "sub<mode>3" | |
578 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
579 | (minus:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
580 | (match_operand:ANYF 2 "register_operand" " f")))] | |
581 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
582 | "fsub.<fmt>\t%0,%1,%2" | |
583 | [(set_attr "type" "fadd") | |
584 | (set_attr "mode" "<UNITMODE>")]) | |
585 | ||
586 | (define_insn "subdi3" | |
587 | [(set (match_operand:DI 0 "register_operand" "= r") | |
588 | (minus:DI (match_operand:DI 1 "reg_or_0_operand" " rJ") | |
589 | (match_operand:DI 2 "register_operand" " r")))] | |
590 | "TARGET_64BIT" | |
591 | "sub\t%0,%z1,%2" | |
592 | [(set_attr "type" "arith") | |
593 | (set_attr "mode" "DI")]) | |
594 | ||
595 | (define_insn "subsi3" | |
596 | [(set (match_operand:SI 0 "register_operand" "= r") | |
597 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") | |
598 | (match_operand:SI 2 "register_operand" " r")))] | |
599 | "" | |
600 | "sub%~\t%0,%z1,%2" | |
601 | [(set_attr "type" "arith") | |
602 | (set_attr "mode" "SI")]) | |
603 | ||
604 | (define_expand "subv<mode>4" | |
605 | [(set (match_operand:GPR 0 "register_operand" "= r") | |
606 | (minus:GPR (match_operand:GPR 1 "reg_or_0_operand" " rJ") | |
607 | (match_operand:GPR 2 "register_operand" " r"))) | |
608 | (label_ref (match_operand 3 "" ""))] | |
609 | "" | |
610 | { | |
611 | if (TARGET_64BIT && <MODE>mode == SImode) | |
612 | { | |
613 | rtx t3 = gen_reg_rtx (DImode); | |
614 | rtx t4 = gen_reg_rtx (DImode); | |
615 | rtx t5 = gen_reg_rtx (DImode); | |
616 | rtx t6 = gen_reg_rtx (DImode); | |
617 | ||
618 | emit_insn (gen_subsi3 (operands[0], operands[1], operands[2])); | |
619 | if (GET_CODE (operands[1]) != CONST_INT) | |
620 | emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0)); | |
621 | else | |
622 | t4 = operands[1]; | |
623 | if (GET_CODE (operands[2]) != CONST_INT) | |
624 | emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0)); | |
625 | else | |
626 | t5 = operands[2]; | |
627 | emit_insn (gen_subdi3 (t3, t4, t5)); | |
628 | emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0)); | |
629 | ||
630 | riscv_expand_conditional_branch (operands[3], NE, t6, t3); | |
631 | } | |
632 | else | |
633 | { | |
634 | rtx t3 = gen_reg_rtx (<MODE>mode); | |
635 | rtx t4 = gen_reg_rtx (<MODE>mode); | |
636 | ||
637 | emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2])); | |
638 | ||
639 | rtx cmp1 = gen_rtx_LT (<MODE>mode, operands[2], const0_rtx); | |
640 | emit_insn (gen_cstore<mode>4 (t3, cmp1, operands[2], const0_rtx)); | |
641 | ||
642 | rtx cmp2 = gen_rtx_LT (<MODE>mode, operands[1], operands[0]); | |
643 | emit_insn (gen_cstore<mode>4 (t4, cmp2, operands[1], operands[0])); | |
644 | ||
645 | riscv_expand_conditional_branch (operands[3], NE, t3, t4); | |
646 | } | |
647 | ||
648 | DONE; | |
649 | }) | |
650 | ||
651 | (define_expand "usubv<mode>4" | |
652 | [(set (match_operand:GPR 0 "register_operand" "= r") | |
653 | (minus:GPR (match_operand:GPR 1 "reg_or_0_operand" " rJ") | |
654 | (match_operand:GPR 2 "register_operand" " r"))) | |
655 | (label_ref (match_operand 3 "" ""))] | |
656 | "" | |
657 | { | |
658 | if (TARGET_64BIT && <MODE>mode == SImode) | |
659 | { | |
660 | rtx t3 = gen_reg_rtx (DImode); | |
661 | rtx t4 = gen_reg_rtx (DImode); | |
662 | ||
663 | if (GET_CODE (operands[1]) != CONST_INT) | |
664 | emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0)); | |
665 | else | |
666 | t3 = operands[1]; | |
667 | emit_insn (gen_subsi3 (operands[0], operands[1], operands[2])); | |
668 | emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0)); | |
669 | ||
670 | riscv_expand_conditional_branch (operands[3], LTU, t3, t4); | |
671 | } | |
672 | else | |
673 | { | |
674 | emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2])); | |
675 | riscv_expand_conditional_branch (operands[3], LTU, operands[1], | |
676 | operands[0]); | |
677 | } | |
678 | ||
679 | DONE; | |
680 | }) | |
681 | ||
682 | ||
683 | (define_insn "*subsi3_extended" | |
684 | [(set (match_operand:DI 0 "register_operand" "= r") | |
685 | (sign_extend:DI | |
686 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") | |
687 | (match_operand:SI 2 "register_operand" " r"))))] | |
688 | "TARGET_64BIT" | |
689 | "subw\t%0,%z1,%2" | |
690 | [(set_attr "type" "arith") | |
691 | (set_attr "mode" "SI")]) | |
692 | ||
693 | (define_insn "*subsi3_extended2" | |
694 | [(set (match_operand:DI 0 "register_operand" "= r") | |
695 | (sign_extend:DI | |
696 | (match_operator:SI 3 "subreg_lowpart_operator" | |
697 | [(minus:DI (match_operand:DI 1 "reg_or_0_operand" " rJ") | |
698 | (match_operand:DI 2 "register_operand" " r"))])))] | |
699 | "TARGET_64BIT" | |
700 | "subw\t%0,%z1,%2" | |
701 | [(set_attr "type" "arith") | |
702 | (set_attr "mode" "SI")]) | |
703 | ||
704 | (define_insn "negdi2" | |
705 | [(set (match_operand:DI 0 "register_operand" "=r") | |
706 | (neg:DI (match_operand:DI 1 "register_operand" " r")))] | |
707 | "TARGET_64BIT" | |
708 | "neg\t%0,%1" | |
709 | [(set_attr "type" "arith") | |
710 | (set_attr "mode" "DI")]) | |
711 | ||
712 | (define_insn "negsi2" | |
713 | [(set (match_operand:SI 0 "register_operand" "=r") | |
714 | (neg:SI (match_operand:SI 1 "register_operand" " r")))] | |
715 | "" | |
716 | "neg%~\t%0,%1" | |
717 | [(set_attr "type" "arith") | |
718 | (set_attr "mode" "SI")]) | |
719 | ||
720 | (define_insn "*negsi2_extended" | |
721 | [(set (match_operand:DI 0 "register_operand" "=r") | |
722 | (sign_extend:DI | |
723 | (neg:SI (match_operand:SI 1 "register_operand" " r"))))] | |
724 | "TARGET_64BIT" | |
725 | "negw\t%0,%1" | |
726 | [(set_attr "type" "arith") | |
727 | (set_attr "mode" "SI")]) | |
728 | ||
729 | (define_insn "*negsi2_extended2" | |
730 | [(set (match_operand:DI 0 "register_operand" "=r") | |
731 | (sign_extend:DI | |
732 | (match_operator:SI 2 "subreg_lowpart_operator" | |
733 | [(neg:DI (match_operand:DI 1 "register_operand" " r"))])))] | |
734 | "TARGET_64BIT" | |
735 | "negw\t%0,%1" | |
736 | [(set_attr "type" "arith") | |
737 | (set_attr "mode" "SI")]) | |
738 | ||
739 | ;; | |
740 | ;; .................... | |
741 | ;; | |
742 | ;; MULTIPLICATION | |
743 | ;; | |
744 | ;; .................... | |
745 | ;; | |
746 | ||
747 | (define_insn "mul<mode>3" | |
748 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
749 | (mult:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
750 | (match_operand:ANYF 2 "register_operand" " f")))] | |
751 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
752 | "fmul.<fmt>\t%0,%1,%2" | |
753 | [(set_attr "type" "fmul") | |
754 | (set_attr "mode" "<UNITMODE>")]) | |
755 | ||
756 | (define_insn "mulsi3" | |
757 | [(set (match_operand:SI 0 "register_operand" "=r") | |
758 | (mult:SI (match_operand:SI 1 "register_operand" " r") | |
759 | (match_operand:SI 2 "register_operand" " r")))] | |
760 | "TARGET_ZMMUL || TARGET_MUL" | |
761 | "mul%~\t%0,%1,%2" | |
762 | [(set_attr "type" "imul") | |
763 | (set_attr "mode" "SI")]) | |
764 | ||
765 | (define_insn "muldi3" | |
766 | [(set (match_operand:DI 0 "register_operand" "=r") | |
767 | (mult:DI (match_operand:DI 1 "register_operand" " r") | |
768 | (match_operand:DI 2 "register_operand" " r")))] | |
769 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
770 | "mul\t%0,%1,%2" | |
771 | [(set_attr "type" "imul") | |
772 | (set_attr "mode" "DI")]) | |
773 | ||
774 | (define_expand "mulv<mode>4" | |
775 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
776 | (mult:GPR (match_operand:GPR 1 "register_operand" " r") | |
777 | (match_operand:GPR 2 "register_operand" " r"))) | |
778 | (label_ref (match_operand 3 "" ""))] | |
779 | "TARGET_ZMMUL || TARGET_MUL" | |
780 | { | |
781 | if (TARGET_64BIT && <MODE>mode == SImode) | |
782 | { | |
783 | rtx t3 = gen_reg_rtx (DImode); | |
784 | rtx t4 = gen_reg_rtx (DImode); | |
785 | rtx t5 = gen_reg_rtx (DImode); | |
786 | rtx t6 = gen_reg_rtx (DImode); | |
787 | ||
788 | if (GET_CODE (operands[1]) != CONST_INT) | |
789 | emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0)); | |
790 | else | |
791 | t4 = operands[1]; | |
792 | if (GET_CODE (operands[2]) != CONST_INT) | |
793 | emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0)); | |
794 | else | |
795 | t5 = operands[2]; | |
796 | emit_insn (gen_muldi3 (t3, t4, t5)); | |
797 | ||
798 | emit_move_insn (operands[0], gen_lowpart (SImode, t3)); | |
799 | emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0)); | |
800 | ||
801 | riscv_expand_conditional_branch (operands[3], NE, t6, t3); | |
802 | } | |
803 | else | |
804 | { | |
805 | rtx hp = gen_reg_rtx (<MODE>mode); | |
806 | rtx lp = gen_reg_rtx (<MODE>mode); | |
807 | ||
808 | emit_insn (gen_smul<mode>3_highpart (hp, operands[1], operands[2])); | |
809 | emit_insn (gen_mul<mode>3 (operands[0], operands[1], operands[2])); | |
810 | emit_insn (gen_ashr<mode>3 (lp, operands[0], | |
811 | GEN_INT (BITS_PER_WORD - 1))); | |
812 | ||
813 | riscv_expand_conditional_branch (operands[3], NE, hp, lp); | |
814 | } | |
815 | ||
816 | DONE; | |
817 | }) | |
818 | ||
819 | (define_expand "umulv<mode>4" | |
820 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
821 | (mult:GPR (match_operand:GPR 1 "register_operand" " r") | |
822 | (match_operand:GPR 2 "register_operand" " r"))) | |
823 | (label_ref (match_operand 3 "" ""))] | |
824 | "TARGET_ZMMUL || TARGET_MUL" | |
825 | { | |
826 | if (TARGET_64BIT && <MODE>mode == SImode) | |
827 | { | |
828 | rtx t3 = gen_reg_rtx (DImode); | |
829 | rtx t4 = gen_reg_rtx (DImode); | |
830 | rtx t5 = gen_reg_rtx (DImode); | |
831 | rtx t6 = gen_reg_rtx (DImode); | |
832 | rtx t7 = gen_reg_rtx (DImode); | |
833 | rtx t8 = gen_reg_rtx (DImode); | |
834 | ||
835 | if (GET_CODE (operands[1]) != CONST_INT) | |
836 | emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0)); | |
837 | else | |
838 | t3 = operands[1]; | |
839 | if (GET_CODE (operands[2]) != CONST_INT) | |
840 | emit_insn (gen_extend_insn (t4, operands[2], DImode, SImode, 0)); | |
841 | else | |
842 | t4 = operands[2]; | |
843 | ||
844 | emit_insn (gen_ashldi3 (t5, t3, GEN_INT (32))); | |
845 | emit_insn (gen_ashldi3 (t6, t4, GEN_INT (32))); | |
846 | emit_insn (gen_umuldi3_highpart (t7, t5, t6)); | |
847 | emit_move_insn (operands[0], gen_lowpart (SImode, t7)); | |
848 | emit_insn (gen_lshrdi3 (t8, t7, GEN_INT (32))); | |
849 | ||
850 | riscv_expand_conditional_branch (operands[3], NE, t8, const0_rtx); | |
851 | } | |
852 | else | |
853 | { | |
854 | rtx hp = gen_reg_rtx (<MODE>mode); | |
855 | ||
856 | emit_insn (gen_umul<mode>3_highpart (hp, operands[1], operands[2])); | |
857 | emit_insn (gen_mul<mode>3 (operands[0], operands[1], operands[2])); | |
858 | ||
859 | riscv_expand_conditional_branch (operands[3], NE, hp, const0_rtx); | |
860 | } | |
861 | ||
862 | DONE; | |
863 | }) | |
864 | ||
865 | (define_insn "*mulsi3_extended" | |
866 | [(set (match_operand:DI 0 "register_operand" "=r") | |
867 | (sign_extend:DI | |
868 | (mult:SI (match_operand:SI 1 "register_operand" " r") | |
869 | (match_operand:SI 2 "register_operand" " r"))))] | |
870 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
871 | "mulw\t%0,%1,%2" | |
872 | [(set_attr "type" "imul") | |
873 | (set_attr "mode" "SI")]) | |
874 | ||
875 | (define_insn "*mulsi3_extended2" | |
876 | [(set (match_operand:DI 0 "register_operand" "=r") | |
877 | (sign_extend:DI | |
878 | (match_operator:SI 3 "subreg_lowpart_operator" | |
879 | [(mult:DI (match_operand:DI 1 "register_operand" " r") | |
880 | (match_operand:DI 2 "register_operand" " r"))])))] | |
881 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
882 | "mulw\t%0,%1,%2" | |
883 | [(set_attr "type" "imul") | |
884 | (set_attr "mode" "SI")]) | |
885 | ||
886 | ;; | |
887 | ;; ........................ | |
888 | ;; | |
889 | ;; MULTIPLICATION HIGH-PART | |
890 | ;; | |
891 | ;; ........................ | |
892 | ;; | |
893 | ||
894 | ||
895 | (define_expand "<u>mulditi3" | |
896 | [(set (match_operand:TI 0 "register_operand") | |
897 | (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) | |
898 | (any_extend:TI (match_operand:DI 2 "register_operand"))))] | |
899 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
900 | { | |
901 | rtx low = gen_reg_rtx (DImode); | |
902 | emit_insn (gen_muldi3 (low, operands[1], operands[2])); | |
903 | ||
904 | rtx high = gen_reg_rtx (DImode); | |
905 | emit_insn (gen_<su>muldi3_highpart (high, operands[1], operands[2])); | |
906 | ||
907 | emit_move_insn (gen_lowpart (DImode, operands[0]), low); | |
908 | emit_move_insn (gen_highpart (DImode, operands[0]), high); | |
909 | DONE; | |
910 | }) | |
911 | ||
912 | (define_insn "<su>muldi3_highpart" | |
913 | [(set (match_operand:DI 0 "register_operand" "=r") | |
914 | (truncate:DI | |
915 | (lshiftrt:TI | |
916 | (mult:TI (any_extend:TI | |
917 | (match_operand:DI 1 "register_operand" " r")) | |
918 | (any_extend:TI | |
919 | (match_operand:DI 2 "register_operand" " r"))) | |
920 | (const_int 64))))] | |
921 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
922 | "mulh<u>\t%0,%1,%2" | |
923 | [(set_attr "type" "imul") | |
924 | (set_attr "mode" "DI")]) | |
925 | ||
926 | (define_expand "usmulditi3" | |
927 | [(set (match_operand:TI 0 "register_operand") | |
928 | (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand")) | |
929 | (sign_extend:TI (match_operand:DI 2 "register_operand"))))] | |
930 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
931 | { | |
932 | rtx low = gen_reg_rtx (DImode); | |
933 | emit_insn (gen_muldi3 (low, operands[1], operands[2])); | |
934 | ||
935 | rtx high = gen_reg_rtx (DImode); | |
936 | emit_insn (gen_usmuldi3_highpart (high, operands[1], operands[2])); | |
937 | ||
938 | emit_move_insn (gen_lowpart (DImode, operands[0]), low); | |
939 | emit_move_insn (gen_highpart (DImode, operands[0]), high); | |
940 | DONE; | |
941 | }) | |
942 | ||
943 | (define_insn "usmuldi3_highpart" | |
944 | [(set (match_operand:DI 0 "register_operand" "=r") | |
945 | (truncate:DI | |
946 | (lshiftrt:TI | |
947 | (mult:TI (zero_extend:TI | |
948 | (match_operand:DI 1 "register_operand" "r")) | |
949 | (sign_extend:TI | |
950 | (match_operand:DI 2 "register_operand" " r"))) | |
951 | (const_int 64))))] | |
952 | "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" | |
953 | "mulhsu\t%0,%2,%1" | |
954 | [(set_attr "type" "imul") | |
955 | (set_attr "mode" "DI")]) | |
956 | ||
957 | (define_expand "<u>mulsidi3" | |
958 | [(set (match_operand:DI 0 "register_operand" "=r") | |
959 | (mult:DI (any_extend:DI | |
960 | (match_operand:SI 1 "register_operand" " r")) | |
961 | (any_extend:DI | |
962 | (match_operand:SI 2 "register_operand" " r"))))] | |
963 | "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" | |
964 | { | |
965 | rtx temp = gen_reg_rtx (SImode); | |
966 | emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); | |
967 | emit_insn (gen_<su>mulsi3_highpart (riscv_subword (operands[0], true), | |
968 | operands[1], operands[2])); | |
969 | emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); | |
970 | DONE; | |
971 | }) | |
972 | ||
973 | (define_insn "<su>mulsi3_highpart" | |
974 | [(set (match_operand:SI 0 "register_operand" "=r") | |
975 | (truncate:SI | |
976 | (lshiftrt:DI | |
977 | (mult:DI (any_extend:DI | |
978 | (match_operand:SI 1 "register_operand" " r")) | |
979 | (any_extend:DI | |
980 | (match_operand:SI 2 "register_operand" " r"))) | |
981 | (const_int 32))))] | |
982 | "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" | |
983 | "mulh<u>\t%0,%1,%2" | |
984 | [(set_attr "type" "imul") | |
985 | (set_attr "mode" "SI")]) | |
986 | ||
987 | ||
988 | (define_expand "usmulsidi3" | |
989 | [(set (match_operand:DI 0 "register_operand" "=r") | |
990 | (mult:DI (zero_extend:DI | |
991 | (match_operand:SI 1 "register_operand" " r")) | |
992 | (sign_extend:DI | |
993 | (match_operand:SI 2 "register_operand" " r"))))] | |
994 | "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" | |
995 | { | |
996 | rtx temp = gen_reg_rtx (SImode); | |
997 | emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); | |
998 | emit_insn (gen_usmulsi3_highpart (riscv_subword (operands[0], true), | |
999 | operands[1], operands[2])); | |
1000 | emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); | |
1001 | DONE; | |
1002 | }) | |
1003 | ||
1004 | (define_insn "usmulsi3_highpart" | |
1005 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1006 | (truncate:SI | |
1007 | (lshiftrt:DI | |
1008 | (mult:DI (zero_extend:DI | |
1009 | (match_operand:SI 1 "register_operand" " r")) | |
1010 | (sign_extend:DI | |
1011 | (match_operand:SI 2 "register_operand" " r"))) | |
1012 | (const_int 32))))] | |
1013 | "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" | |
1014 | "mulhsu\t%0,%2,%1" | |
1015 | [(set_attr "type" "imul") | |
1016 | (set_attr "mode" "SI")]) | |
1017 | ||
1018 | ;; | |
1019 | ;; .................... | |
1020 | ;; | |
1021 | ;; DIVISION and REMAINDER | |
1022 | ;; | |
1023 | ;; .................... | |
1024 | ;; | |
1025 | ||
1026 | (define_insn "<optab>si3" | |
1027 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1028 | (any_div:SI (match_operand:SI 1 "register_operand" " r") | |
1029 | (match_operand:SI 2 "register_operand" " r")))] | |
1030 | "TARGET_DIV" | |
1031 | "<insn>%i2%~\t%0,%1,%2" | |
1032 | [(set_attr "type" "idiv") | |
1033 | (set_attr "mode" "SI")]) | |
1034 | ||
1035 | (define_insn "<optab>di3" | |
1036 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1037 | (any_div:DI (match_operand:DI 1 "register_operand" " r") | |
1038 | (match_operand:DI 2 "register_operand" " r")))] | |
1039 | "TARGET_DIV && TARGET_64BIT" | |
1040 | "<insn>%i2\t%0,%1,%2" | |
1041 | [(set_attr "type" "idiv") | |
1042 | (set_attr "mode" "DI")]) | |
1043 | ||
1044 | (define_insn "*<optab>si3_extended" | |
1045 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1046 | (sign_extend:DI | |
1047 | (any_div:SI (match_operand:SI 1 "register_operand" " r") | |
1048 | (match_operand:SI 2 "register_operand" " r"))))] | |
1049 | "TARGET_DIV && TARGET_64BIT" | |
1050 | "<insn>%i2w\t%0,%1,%2" | |
1051 | [(set_attr "type" "idiv") | |
1052 | (set_attr "mode" "DI")]) | |
1053 | ||
1054 | (define_insn "div<mode>3" | |
1055 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1056 | (div:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
1057 | (match_operand:ANYF 2 "register_operand" " f")))] | |
1058 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" | |
1059 | "fdiv.<fmt>\t%0,%1,%2" | |
1060 | [(set_attr "type" "fdiv") | |
1061 | (set_attr "mode" "<UNITMODE>")]) | |
1062 | ||
1063 | ;; | |
1064 | ;; .................... | |
1065 | ;; | |
1066 | ;; SQUARE ROOT | |
1067 | ;; | |
1068 | ;; .................... | |
1069 | ||
1070 | (define_insn "sqrt<mode>2" | |
1071 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1072 | (sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))] | |
1073 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" | |
1074 | { | |
1075 | return "fsqrt.<fmt>\t%0,%1"; | |
1076 | } | |
1077 | [(set_attr "type" "fsqrt") | |
1078 | (set_attr "mode" "<UNITMODE>")]) | |
1079 | ||
1080 | ;; Floating point multiply accumulate instructions. | |
1081 | ||
1082 | ;; a * b + c | |
1083 | (define_insn "fma<mode>4" | |
1084 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1085 | (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
1086 | (match_operand:ANYF 2 "register_operand" " f") | |
1087 | (match_operand:ANYF 3 "register_operand" " f")))] | |
1088 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1089 | "fmadd.<fmt>\t%0,%1,%2,%3" | |
1090 | [(set_attr "type" "fmadd") | |
1091 | (set_attr "mode" "<UNITMODE>")]) | |
1092 | ||
1093 | ;; a * b - c | |
1094 | (define_insn "fms<mode>4" | |
1095 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1096 | (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
1097 | (match_operand:ANYF 2 "register_operand" " f") | |
1098 | (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] | |
1099 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1100 | "fmsub.<fmt>\t%0,%1,%2,%3" | |
1101 | [(set_attr "type" "fmadd") | |
1102 | (set_attr "mode" "<UNITMODE>")]) | |
1103 | ||
1104 | ;; -a * b - c | |
1105 | (define_insn "fnms<mode>4" | |
1106 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1107 | (fma:ANYF | |
1108 | (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) | |
1109 | (match_operand:ANYF 2 "register_operand" " f") | |
1110 | (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] | |
1111 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1112 | "fnmadd.<fmt>\t%0,%1,%2,%3" | |
1113 | [(set_attr "type" "fmadd") | |
1114 | (set_attr "mode" "<UNITMODE>")]) | |
1115 | ||
1116 | ;; -a * b + c | |
1117 | (define_insn "fnma<mode>4" | |
1118 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1119 | (fma:ANYF | |
1120 | (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) | |
1121 | (match_operand:ANYF 2 "register_operand" " f") | |
1122 | (match_operand:ANYF 3 "register_operand" " f")))] | |
1123 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1124 | "fnmsub.<fmt>\t%0,%1,%2,%3" | |
1125 | [(set_attr "type" "fmadd") | |
1126 | (set_attr "mode" "<UNITMODE>")]) | |
1127 | ||
1128 | ;; -(-a * b - c), modulo signed zeros | |
1129 | (define_insn "*fma<mode>4" | |
1130 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1131 | (neg:ANYF | |
1132 | (fma:ANYF | |
1133 | (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) | |
1134 | (match_operand:ANYF 2 "register_operand" " f") | |
1135 | (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] | |
1136 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" | |
1137 | "fmadd.<fmt>\t%0,%1,%2,%3" | |
1138 | [(set_attr "type" "fmadd") | |
1139 | (set_attr "mode" "<UNITMODE>")]) | |
1140 | ||
1141 | ;; -(-a * b + c), modulo signed zeros | |
1142 | (define_insn "*fms<mode>4" | |
1143 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1144 | (neg:ANYF | |
1145 | (fma:ANYF | |
1146 | (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) | |
1147 | (match_operand:ANYF 2 "register_operand" " f") | |
1148 | (match_operand:ANYF 3 "register_operand" " f"))))] | |
1149 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" | |
1150 | "fmsub.<fmt>\t%0,%1,%2,%3" | |
1151 | [(set_attr "type" "fmadd") | |
1152 | (set_attr "mode" "<UNITMODE>")]) | |
1153 | ||
1154 | ;; -(a * b + c), modulo signed zeros | |
1155 | (define_insn "*fnms<mode>4" | |
1156 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1157 | (neg:ANYF | |
1158 | (fma:ANYF | |
1159 | (match_operand:ANYF 1 "register_operand" " f") | |
1160 | (match_operand:ANYF 2 "register_operand" " f") | |
1161 | (match_operand:ANYF 3 "register_operand" " f"))))] | |
1162 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" | |
1163 | "fnmadd.<fmt>\t%0,%1,%2,%3" | |
1164 | [(set_attr "type" "fmadd") | |
1165 | (set_attr "mode" "<UNITMODE>")]) | |
1166 | ||
1167 | ;; -(a * b - c), modulo signed zeros | |
1168 | (define_insn "*fnma<mode>4" | |
1169 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1170 | (neg:ANYF | |
1171 | (fma:ANYF | |
1172 | (match_operand:ANYF 1 "register_operand" " f") | |
1173 | (match_operand:ANYF 2 "register_operand" " f") | |
1174 | (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] | |
1175 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" | |
1176 | "fnmsub.<fmt>\t%0,%1,%2,%3" | |
1177 | [(set_attr "type" "fmadd") | |
1178 | (set_attr "mode" "<UNITMODE>")]) | |
1179 | ||
1180 | ;; | |
1181 | ;; .................... | |
1182 | ;; | |
1183 | ;; SIGN INJECTION | |
1184 | ;; | |
1185 | ;; .................... | |
1186 | ||
1187 | (define_insn "abs<mode>2" | |
1188 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1189 | (abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))] | |
1190 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1191 | "fabs.<fmt>\t%0,%1" | |
1192 | [(set_attr "type" "fmove") | |
1193 | (set_attr "mode" "<UNITMODE>")]) | |
1194 | ||
1195 | (define_insn "copysign<mode>3" | |
1196 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1197 | (unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f") | |
1198 | (match_operand:ANYF 2 "register_operand" " f")] | |
1199 | UNSPEC_COPYSIGN))] | |
1200 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1201 | "fsgnj.<fmt>\t%0,%1,%2" | |
1202 | [(set_attr "type" "fmove") | |
1203 | (set_attr "mode" "<UNITMODE>")]) | |
1204 | ||
1205 | (define_insn "neg<mode>2" | |
1206 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1207 | (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))] | |
1208 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1209 | "fneg.<fmt>\t%0,%1" | |
1210 | [(set_attr "type" "fmove") | |
1211 | (set_attr "mode" "<UNITMODE>")]) | |
1212 | ||
1213 | ;; | |
1214 | ;; .................... | |
1215 | ;; | |
1216 | ;; MIN/MAX | |
1217 | ;; | |
1218 | ;; .................... | |
1219 | ||
1220 | (define_insn "fmin<mode>3" | |
1221 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1222 | (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) | |
1223 | (use (match_operand:ANYF 2 "register_operand" " f"))] | |
1224 | UNSPEC_FMIN))] | |
1225 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)" | |
1226 | "fmin.<fmt>\t%0,%1,%2" | |
1227 | [(set_attr "type" "fmove") | |
1228 | (set_attr "mode" "<UNITMODE>")]) | |
1229 | ||
1230 | (define_insn "fmax<mode>3" | |
1231 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1232 | (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) | |
1233 | (use (match_operand:ANYF 2 "register_operand" " f"))] | |
1234 | UNSPEC_FMAX))] | |
1235 | "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)" | |
1236 | "fmax.<fmt>\t%0,%1,%2" | |
1237 | [(set_attr "type" "fmove") | |
1238 | (set_attr "mode" "<UNITMODE>")]) | |
1239 | ||
1240 | (define_insn "smin<mode>3" | |
1241 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1242 | (smin:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
1243 | (match_operand:ANYF 2 "register_operand" " f")))] | |
1244 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1245 | "fmin.<fmt>\t%0,%1,%2" | |
1246 | [(set_attr "type" "fmove") | |
1247 | (set_attr "mode" "<UNITMODE>")]) | |
1248 | ||
1249 | (define_insn "smax<mode>3" | |
1250 | [(set (match_operand:ANYF 0 "register_operand" "=f") | |
1251 | (smax:ANYF (match_operand:ANYF 1 "register_operand" " f") | |
1252 | (match_operand:ANYF 2 "register_operand" " f")))] | |
1253 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1254 | "fmax.<fmt>\t%0,%1,%2" | |
1255 | [(set_attr "type" "fmove") | |
1256 | (set_attr "mode" "<UNITMODE>")]) | |
1257 | ||
1258 | ;; | |
1259 | ;; .................... | |
1260 | ;; | |
1261 | ;; LOGICAL | |
1262 | ;; | |
1263 | ;; .................... | |
1264 | ;; | |
1265 | ||
1266 | ;; For RV64, we don't expose the SImode operations to the rtl expanders, | |
1267 | ;; but SImode versions exist for combine. | |
1268 | ||
1269 | (define_insn "<optab><mode>3" | |
1270 | [(set (match_operand:X 0 "register_operand" "=r,r") | |
1271 | (any_bitwise:X (match_operand:X 1 "register_operand" "%r,r") | |
1272 | (match_operand:X 2 "arith_operand" " r,I")))] | |
1273 | "" | |
1274 | "<insn>%i2\t%0,%1,%2" | |
1275 | [(set_attr "type" "logical") | |
1276 | (set_attr "mode" "<MODE>")]) | |
1277 | ||
1278 | (define_insn "*<optab>si3_internal" | |
1279 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
1280 | (any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r") | |
1281 | (match_operand:SI 2 "arith_operand" " r,I")))] | |
1282 | "TARGET_64BIT" | |
1283 | "<insn>%i2\t%0,%1,%2" | |
1284 | [(set_attr "type" "logical") | |
1285 | (set_attr "mode" "SI")]) | |
1286 | ||
1287 | (define_insn "one_cmpl<mode>2" | |
1288 | [(set (match_operand:X 0 "register_operand" "=r") | |
1289 | (not:X (match_operand:X 1 "register_operand" " r")))] | |
1290 | "" | |
1291 | "not\t%0,%1" | |
1292 | [(set_attr "type" "logical") | |
1293 | (set_attr "mode" "<MODE>")]) | |
1294 | ||
1295 | (define_insn "*one_cmplsi2_internal" | |
1296 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1297 | (not:SI (match_operand:SI 1 "register_operand" " r")))] | |
1298 | "TARGET_64BIT" | |
1299 | "not\t%0,%1" | |
1300 | [(set_attr "type" "logical") | |
1301 | (set_attr "mode" "SI")]) | |
1302 | ||
1303 | ;; | |
1304 | ;; .................... | |
1305 | ;; | |
1306 | ;; TRUNCATION | |
1307 | ;; | |
1308 | ;; .................... | |
1309 | ||
1310 | (define_insn "truncdfsf2" | |
1311 | [(set (match_operand:SF 0 "register_operand" "=f") | |
1312 | (float_truncate:SF | |
1313 | (match_operand:DF 1 "register_operand" " f")))] | |
1314 | "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" | |
1315 | "fcvt.s.d\t%0,%1" | |
1316 | [(set_attr "type" "fcvt") | |
1317 | (set_attr "mode" "SF")]) | |
1318 | ||
1319 | (define_insn "truncsfhf2" | |
1320 | [(set (match_operand:HF 0 "register_operand" "=f") | |
1321 | (float_truncate:HF | |
1322 | (match_operand:SF 1 "register_operand" " f")))] | |
1323 | "TARGET_ZFHMIN || TARGET_ZHINXMIN" | |
1324 | "fcvt.h.s\t%0,%1" | |
1325 | [(set_attr "type" "fcvt") | |
1326 | (set_attr "mode" "HF")]) | |
1327 | ||
1328 | (define_insn "truncdfhf2" | |
1329 | [(set (match_operand:HF 0 "register_operand" "=f") | |
1330 | (float_truncate:HF | |
1331 | (match_operand:DF 1 "register_operand" " f")))] | |
1332 | "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) || | |
1333 | (TARGET_ZHINXMIN && TARGET_ZDINX)" | |
1334 | "fcvt.h.d\t%0,%1" | |
1335 | [(set_attr "type" "fcvt") | |
1336 | (set_attr "mode" "HF")]) | |
1337 | ||
1338 | ;; | |
1339 | ;; .................... | |
1340 | ;; | |
1341 | ;; ZERO EXTENSION | |
1342 | ;; | |
1343 | ;; .................... | |
1344 | ||
1345 | ;; Extension insns. | |
1346 | ||
1347 | (define_expand "zero_extendsidi2" | |
1348 | [(set (match_operand:DI 0 "register_operand") | |
1349 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] | |
1350 | "TARGET_64BIT") | |
1351 | ||
1352 | (define_insn_and_split "*zero_extendsidi2_internal" | |
1353 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
1354 | (zero_extend:DI | |
1355 | (match_operand:SI 1 "nonimmediate_operand" " r,m")))] | |
1356 | "TARGET_64BIT && !TARGET_ZBA" | |
1357 | "@ | |
1358 | # | |
1359 | lwu\t%0,%1" | |
1360 | "&& reload_completed | |
1361 | && REG_P (operands[1]) | |
1362 | && !paradoxical_subreg_p (operands[0])" | |
1363 | [(set (match_dup 0) | |
1364 | (ashift:DI (match_dup 1) (const_int 32))) | |
1365 | (set (match_dup 0) | |
1366 | (lshiftrt:DI (match_dup 0) (const_int 32)))] | |
1367 | { operands[1] = gen_lowpart (DImode, operands[1]); } | |
1368 | [(set_attr "move_type" "shift_shift,load") | |
1369 | (set_attr "mode" "DI")]) | |
1370 | ||
1371 | (define_expand "zero_extendhi<GPR:mode>2" | |
1372 | [(set (match_operand:GPR 0 "register_operand") | |
1373 | (zero_extend:GPR | |
1374 | (match_operand:HI 1 "nonimmediate_operand")))] | |
1375 | "") | |
1376 | ||
1377 | (define_insn_and_split "*zero_extendhi<GPR:mode>2" | |
1378 | [(set (match_operand:GPR 0 "register_operand" "=r,r") | |
1379 | (zero_extend:GPR | |
1380 | (match_operand:HI 1 "nonimmediate_operand" " r,m")))] | |
1381 | "!TARGET_ZBB" | |
1382 | "@ | |
1383 | # | |
1384 | lhu\t%0,%1" | |
1385 | "&& reload_completed | |
1386 | && REG_P (operands[1]) | |
1387 | && !paradoxical_subreg_p (operands[0])" | |
1388 | [(set (match_dup 0) | |
1389 | (ashift:GPR (match_dup 1) (match_dup 2))) | |
1390 | (set (match_dup 0) | |
1391 | (lshiftrt:GPR (match_dup 0) (match_dup 2)))] | |
1392 | { | |
1393 | operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]); | |
1394 | operands[2] = GEN_INT(GET_MODE_BITSIZE(<GPR:MODE>mode) - 16); | |
1395 | } | |
1396 | [(set_attr "move_type" "shift_shift,load") | |
1397 | (set_attr "mode" "<GPR:MODE>")]) | |
1398 | ||
1399 | (define_insn "zero_extendqi<SUPERQI:mode>2" | |
1400 | [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") | |
1401 | (zero_extend:SUPERQI | |
1402 | (match_operand:QI 1 "nonimmediate_operand" " r,m")))] | |
1403 | "" | |
1404 | "@ | |
1405 | andi\t%0,%1,0xff | |
1406 | lbu\t%0,%1" | |
1407 | [(set_attr "move_type" "andi,load") | |
1408 | (set_attr "mode" "<SUPERQI:MODE>")]) | |
1409 | ||
1410 | ;; | |
1411 | ;; .................... | |
1412 | ;; | |
1413 | ;; SIGN EXTENSION | |
1414 | ;; | |
1415 | ;; .................... | |
1416 | ||
1417 | (define_insn "extendsidi2" | |
1418 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
1419 | (sign_extend:DI | |
1420 | (match_operand:SI 1 "nonimmediate_operand" " r,m")))] | |
1421 | "TARGET_64BIT" | |
1422 | "@ | |
1423 | sext.w\t%0,%1 | |
1424 | lw\t%0,%1" | |
1425 | [(set_attr "move_type" "move,load") | |
1426 | (set_attr "mode" "DI")]) | |
1427 | ||
1428 | (define_expand "extend<SHORT:mode><SUPERQI:mode>2" | |
1429 | [(set (match_operand:SUPERQI 0 "register_operand") | |
1430 | (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand")))] | |
1431 | "") | |
1432 | ||
1433 | (define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2" | |
1434 | [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") | |
1435 | (sign_extend:SUPERQI | |
1436 | (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] | |
1437 | "!TARGET_ZBB" | |
1438 | "@ | |
1439 | # | |
1440 | l<SHORT:size>\t%0,%1" | |
1441 | "&& reload_completed | |
1442 | && REG_P (operands[1]) | |
1443 | && !paradoxical_subreg_p (operands[0])" | |
1444 | [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) | |
1445 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] | |
1446 | { | |
1447 | operands[0] = gen_lowpart (SImode, operands[0]); | |
1448 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1449 | operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) | |
1450 | - GET_MODE_BITSIZE (<SHORT:MODE>mode)); | |
1451 | } | |
1452 | [(set_attr "move_type" "shift_shift,load") | |
1453 | (set_attr "mode" "SI")]) | |
1454 | ||
1455 | (define_insn "extendhfsf2" | |
1456 | [(set (match_operand:SF 0 "register_operand" "=f") | |
1457 | (float_extend:SF | |
1458 | (match_operand:HF 1 "register_operand" " f")))] | |
1459 | "TARGET_ZFHMIN || TARGET_ZHINXMIN" | |
1460 | "fcvt.s.h\t%0,%1" | |
1461 | [(set_attr "type" "fcvt") | |
1462 | (set_attr "mode" "SF")]) | |
1463 | ||
1464 | (define_insn "extendsfdf2" | |
1465 | [(set (match_operand:DF 0 "register_operand" "=f") | |
1466 | (float_extend:DF | |
1467 | (match_operand:SF 1 "register_operand" " f")))] | |
1468 | "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" | |
1469 | "fcvt.d.s\t%0,%1" | |
1470 | [(set_attr "type" "fcvt") | |
1471 | (set_attr "mode" "DF")]) | |
1472 | ||
1473 | (define_insn "extendhfdf2" | |
1474 | [(set (match_operand:DF 0 "register_operand" "=f") | |
1475 | (float_extend:DF | |
1476 | (match_operand:HF 1 "register_operand" " f")))] | |
1477 | "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) || | |
1478 | (TARGET_ZHINXMIN && TARGET_ZDINX)" | |
1479 | "fcvt.d.h\t%0,%1" | |
1480 | [(set_attr "type" "fcvt") | |
1481 | (set_attr "mode" "DF")]) | |
1482 | ||
1483 | ;; 16-bit floating point moves | |
1484 | (define_expand "movhf" | |
1485 | [(set (match_operand:HF 0 "") | |
1486 | (match_operand:HF 1 ""))] | |
1487 | "" | |
1488 | { | |
1489 | if (riscv_legitimize_move (HFmode, operands[0], operands[1])) | |
1490 | DONE; | |
1491 | }) | |
1492 | ||
1493 | (define_insn "*movhf_hardfloat" | |
1494 | [(set (match_operand:HF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r, *r,*r,*m") | |
1495 | (match_operand:HF 1 "move_operand" " f,G,m,f,G,*r,*f,*G*r,*m,*r"))] | |
1496 | "TARGET_ZFHMIN | |
1497 | && (register_operand (operands[0], HFmode) | |
1498 | || reg_or_0_operand (operands[1], HFmode))" | |
1499 | { return riscv_output_move (operands[0], operands[1]); } | |
1500 | [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") | |
1501 | (set_attr "mode" "HF")]) | |
1502 | ||
1503 | (define_insn "*movhf_softfloat" | |
1504 | [(set (match_operand:HF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r") | |
1505 | (match_operand:HF 1 "move_operand" " f,Gr,m,r,*r,*f"))] | |
1506 | "!TARGET_ZFHMIN | |
1507 | && (register_operand (operands[0], HFmode) | |
1508 | || reg_or_0_operand (operands[1], HFmode))" | |
1509 | { return riscv_output_move (operands[0], operands[1]); } | |
1510 | [(set_attr "move_type" "fmove,move,load,store,mtc,mfc") | |
1511 | (set_attr "mode" "HF")]) | |
1512 | ||
1513 | ;; | |
1514 | ;; .................... | |
1515 | ;; | |
1516 | ;; CONVERSIONS | |
1517 | ;; | |
1518 | ;; .................... | |
1519 | ||
1520 | (define_insn "fix_trunc<ANYF:mode><GPR:mode>2" | |
1521 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
1522 | (fix:GPR | |
1523 | (match_operand:ANYF 1 "register_operand" " f")))] | |
1524 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1525 | "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz" | |
1526 | [(set_attr "type" "fcvt") | |
1527 | (set_attr "mode" "<ANYF:MODE>")]) | |
1528 | ||
1529 | (define_insn "fixuns_trunc<ANYF:mode><GPR:mode>2" | |
1530 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
1531 | (unsigned_fix:GPR | |
1532 | (match_operand:ANYF 1 "register_operand" " f")))] | |
1533 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1534 | "fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz" | |
1535 | [(set_attr "type" "fcvt") | |
1536 | (set_attr "mode" "<ANYF:MODE>")]) | |
1537 | ||
1538 | (define_insn "float<GPR:mode><ANYF:mode>2" | |
1539 | [(set (match_operand:ANYF 0 "register_operand" "= f") | |
1540 | (float:ANYF | |
1541 | (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] | |
1542 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1543 | "fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1" | |
1544 | [(set_attr "type" "fcvt") | |
1545 | (set_attr "mode" "<ANYF:MODE>")]) | |
1546 | ||
1547 | (define_insn "floatuns<GPR:mode><ANYF:mode>2" | |
1548 | [(set (match_operand:ANYF 0 "register_operand" "= f") | |
1549 | (unsigned_float:ANYF | |
1550 | (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] | |
1551 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1552 | "fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1" | |
1553 | [(set_attr "type" "fcvt") | |
1554 | (set_attr "mode" "<ANYF:MODE>")]) | |
1555 | ||
1556 | (define_insn "l<rint_pattern><ANYF:mode><GPR:mode>2" | |
1557 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
1558 | (unspec:GPR | |
1559 | [(match_operand:ANYF 1 "register_operand" " f")] | |
1560 | RINT))] | |
1561 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
1562 | "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>" | |
1563 | [(set_attr "type" "fcvt") | |
1564 | (set_attr "mode" "<ANYF:MODE>")]) | |
1565 | ||
1566 | ;; | |
1567 | ;; .................... | |
1568 | ;; | |
1569 | ;; DATA MOVEMENT | |
1570 | ;; | |
1571 | ;; .................... | |
1572 | ||
1573 | ;; Lower-level instructions for loading an address from the GOT. | |
1574 | ;; We could use MEMs, but an unspec gives more optimization | |
1575 | ;; opportunities. | |
1576 | ||
1577 | (define_insn "got_load<mode>" | |
1578 | [(set (match_operand:P 0 "register_operand" "=r") | |
1579 | (unspec:P | |
1580 | [(match_operand:P 1 "symbolic_operand" "")] | |
1581 | UNSPEC_LOAD_GOT))] | |
1582 | "" | |
1583 | "la\t%0,%1" | |
1584 | [(set_attr "got" "load") | |
1585 | (set_attr "mode" "<MODE>")]) | |
1586 | ||
1587 | (define_insn "tls_add_tp_le<mode>" | |
1588 | [(set (match_operand:P 0 "register_operand" "=r") | |
1589 | (unspec:P | |
1590 | [(match_operand:P 1 "register_operand" "r") | |
1591 | (match_operand:P 2 "register_operand" "r") | |
1592 | (match_operand:P 3 "symbolic_operand" "")] | |
1593 | UNSPEC_TLS_LE))] | |
1594 | "" | |
1595 | "add\t%0,%1,%2,%%tprel_add(%3)" | |
1596 | [(set_attr "type" "arith") | |
1597 | (set_attr "mode" "<MODE>")]) | |
1598 | ||
1599 | (define_insn "got_load_tls_gd<mode>" | |
1600 | [(set (match_operand:P 0 "register_operand" "=r") | |
1601 | (unspec:P | |
1602 | [(match_operand:P 1 "symbolic_operand" "")] | |
1603 | UNSPEC_TLS_GD))] | |
1604 | "" | |
1605 | "la.tls.gd\t%0,%1" | |
1606 | [(set_attr "got" "load") | |
1607 | (set_attr "mode" "<MODE>")]) | |
1608 | ||
1609 | (define_insn "got_load_tls_ie<mode>" | |
1610 | [(set (match_operand:P 0 "register_operand" "=r") | |
1611 | (unspec:P | |
1612 | [(match_operand:P 1 "symbolic_operand" "")] | |
1613 | UNSPEC_TLS_IE))] | |
1614 | "" | |
1615 | "la.tls.ie\t%0,%1" | |
1616 | [(set_attr "got" "load") | |
1617 | (set_attr "mode" "<MODE>")]) | |
1618 | ||
1619 | (define_insn "auipc<mode>" | |
1620 | [(set (match_operand:P 0 "register_operand" "=r") | |
1621 | (unspec:P | |
1622 | [(match_operand:P 1 "symbolic_operand" "") | |
1623 | (match_operand:P 2 "const_int_operand") | |
1624 | (pc)] | |
1625 | UNSPEC_AUIPC))] | |
1626 | "" | |
1627 | ".LA%2: auipc\t%0,%h1" | |
1628 | [(set_attr "type" "auipc") | |
1629 | (set_attr "cannot_copy" "yes")]) | |
1630 | ||
1631 | ;; Instructions for adding the low 12 bits of an address to a register. | |
1632 | ;; Operand 2 is the address: riscv_print_operand works out which relocation | |
1633 | ;; should be applied. | |
1634 | ||
1635 | (define_insn "*low<mode>" | |
1636 | [(set (match_operand:P 0 "register_operand" "=r") | |
1637 | (lo_sum:P (match_operand:P 1 "register_operand" " r") | |
1638 | (match_operand:P 2 "symbolic_operand" "")))] | |
1639 | "" | |
1640 | "addi\t%0,%1,%R2" | |
1641 | [(set_attr "type" "arith") | |
1642 | (set_attr "mode" "<MODE>")]) | |
1643 | ||
1644 | ;; Allow combine to split complex const_int load sequences, using operand 2 | |
1645 | ;; to store the intermediate results. See move_operand for details. | |
1646 | (define_split | |
1647 | [(set (match_operand:GPR 0 "register_operand") | |
1648 | (match_operand:GPR 1 "splittable_const_int_operand")) | |
1649 | (clobber (match_operand:GPR 2 "register_operand"))] | |
1650 | "" | |
1651 | [(const_int 0)] | |
1652 | { | |
1653 | riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), | |
1654 | <GPR:MODE>mode, TRUE); | |
1655 | DONE; | |
1656 | }) | |
1657 | ||
1658 | ;; Likewise, for symbolic operands. | |
1659 | (define_split | |
1660 | [(set (match_operand:P 0 "register_operand") | |
1661 | (match_operand:P 1)) | |
1662 | (clobber (match_operand:P 2 "register_operand"))] | |
1663 | "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)" | |
1664 | [(set (match_dup 0) (match_dup 3))] | |
1665 | { | |
1666 | riscv_split_symbol (operands[2], operands[1], | |
1667 | MAX_MACHINE_MODE, &operands[3], TRUE); | |
1668 | }) | |
1669 | ||
1670 | ;; 64-bit integer moves | |
1671 | ||
1672 | (define_expand "movdi" | |
1673 | [(set (match_operand:DI 0 "") | |
1674 | (match_operand:DI 1 ""))] | |
1675 | "" | |
1676 | { | |
1677 | if (riscv_legitimize_move (DImode, operands[0], operands[1])) | |
1678 | DONE; | |
1679 | }) | |
1680 | ||
1681 | (define_insn "*movdi_32bit" | |
1682 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m,r") | |
1683 | (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))] | |
1684 | "!TARGET_64BIT | |
1685 | && (register_operand (operands[0], DImode) | |
1686 | || reg_or_0_operand (operands[1], DImode))" | |
1687 | { return riscv_output_move (operands[0], operands[1]); } | |
1688 | [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") | |
1689 | (set_attr "mode" "DI") | |
1690 | (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) | |
1691 | ||
1692 | (define_insn "*movdi_64bit" | |
1693 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r") | |
1694 | (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))] | |
1695 | "TARGET_64BIT | |
1696 | && (register_operand (operands[0], DImode) | |
1697 | || reg_or_0_operand (operands[1], DImode))" | |
1698 | { return riscv_output_move (operands[0], operands[1]); } | |
1699 | [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") | |
1700 | (set_attr "mode" "DI") | |
1701 | (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) | |
1702 | ||
1703 | ;; 32-bit Integer moves | |
1704 | ||
1705 | (define_expand "mov<mode>" | |
1706 | [(set (match_operand:MOVE32 0 "") | |
1707 | (match_operand:MOVE32 1 ""))] | |
1708 | "" | |
1709 | { | |
1710 | if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1])) | |
1711 | DONE; | |
1712 | }) | |
1713 | ||
1714 | (define_insn "*movsi_internal" | |
1715 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m,r") | |
1716 | (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,vp"))] | |
1717 | "(register_operand (operands[0], SImode) | |
1718 | || reg_or_0_operand (operands[1], SImode))" | |
1719 | { return riscv_output_move (operands[0], operands[1]); } | |
1720 | [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") | |
1721 | (set_attr "mode" "SI") | |
1722 | (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) | |
1723 | ||
1724 | ;; 16-bit Integer moves | |
1725 | ||
1726 | ;; Unlike most other insns, the move insns can't be split with | |
1727 | ;; different predicates, because register spilling and other parts of | |
1728 | ;; the compiler, have memoized the insn number already. | |
1729 | ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. | |
1730 | ||
1731 | (define_expand "movhi" | |
1732 | [(set (match_operand:HI 0 "") | |
1733 | (match_operand:HI 1 ""))] | |
1734 | "" | |
1735 | { | |
1736 | if (riscv_legitimize_move (HImode, operands[0], operands[1])) | |
1737 | DONE; | |
1738 | }) | |
1739 | ||
1740 | (define_insn "*movhi_internal" | |
1741 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") | |
1742 | (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f,vp"))] | |
1743 | "(register_operand (operands[0], HImode) | |
1744 | || reg_or_0_operand (operands[1], HImode))" | |
1745 | { return riscv_output_move (operands[0], operands[1]); } | |
1746 | [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") | |
1747 | (set_attr "mode" "HI") | |
1748 | (set_attr "ext" "base,base,base,base,f,f,vector")]) | |
1749 | ||
1750 | ;; HImode constant generation; see riscv_move_integer for details. | |
1751 | ;; si+si->hi without truncation is legal because of | |
1752 | ;; TARGET_TRULY_NOOP_TRUNCATION. | |
1753 | ||
1754 | (define_insn "*add<mode>hi3" | |
1755 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1756 | (plus:HI (match_operand:HISI 1 "register_operand" " r,r") | |
1757 | (match_operand:HISI 2 "arith_operand" " r,I")))] | |
1758 | "" | |
1759 | "add%i2%~\t%0,%1,%2" | |
1760 | [(set_attr "type" "arith") | |
1761 | (set_attr "mode" "HI")]) | |
1762 | ||
1763 | (define_insn "*xor<mode>hi3" | |
1764 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
1765 | (xor:HI (match_operand:HISI 1 "register_operand" " r,r") | |
1766 | (match_operand:HISI 2 "arith_operand" " r,I")))] | |
1767 | "" | |
1768 | "xor%i2\t%0,%1,%2" | |
1769 | [(set_attr "type" "logical") | |
1770 | (set_attr "mode" "HI")]) | |
1771 | ||
1772 | ;; 8-bit Integer moves | |
1773 | ||
1774 | (define_expand "movqi" | |
1775 | [(set (match_operand:QI 0 "") | |
1776 | (match_operand:QI 1 ""))] | |
1777 | "" | |
1778 | { | |
1779 | if (riscv_legitimize_move (QImode, operands[0], operands[1])) | |
1780 | DONE; | |
1781 | }) | |
1782 | ||
1783 | (define_insn "*movqi_internal" | |
1784 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") | |
1785 | (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f,vp"))] | |
1786 | "(register_operand (operands[0], QImode) | |
1787 | || reg_or_0_operand (operands[1], QImode))" | |
1788 | { return riscv_output_move (operands[0], operands[1]); } | |
1789 | [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") | |
1790 | (set_attr "mode" "QI") | |
1791 | (set_attr "ext" "base,base,base,base,f,f,vector")]) | |
1792 | ||
1793 | ;; 32-bit floating point moves | |
1794 | ||
1795 | (define_expand "movsf" | |
1796 | [(set (match_operand:SF 0 "") | |
1797 | (match_operand:SF 1 ""))] | |
1798 | "" | |
1799 | { | |
1800 | if (riscv_legitimize_move (SFmode, operands[0], operands[1])) | |
1801 | DONE; | |
1802 | }) | |
1803 | ||
1804 | (define_insn "*movsf_hardfloat" | |
1805 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r, *r,*r,*m") | |
1806 | (match_operand:SF 1 "move_operand" " f,G,m,f,G,*r,*f,*G*r,*m,*r"))] | |
1807 | "TARGET_HARD_FLOAT | |
1808 | && (register_operand (operands[0], SFmode) | |
1809 | || reg_or_0_operand (operands[1], SFmode))" | |
1810 | { return riscv_output_move (operands[0], operands[1]); } | |
1811 | [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") | |
1812 | (set_attr "mode" "SF")]) | |
1813 | ||
1814 | (define_insn "*movsf_softfloat" | |
1815 | [(set (match_operand:SF 0 "nonimmediate_operand" "= r,r,m") | |
1816 | (match_operand:SF 1 "move_operand" " Gr,m,r"))] | |
1817 | "!TARGET_HARD_FLOAT | |
1818 | && (register_operand (operands[0], SFmode) | |
1819 | || reg_or_0_operand (operands[1], SFmode))" | |
1820 | { return riscv_output_move (operands[0], operands[1]); } | |
1821 | [(set_attr "move_type" "move,load,store") | |
1822 | (set_attr "mode" "SF")]) | |
1823 | ||
1824 | ;; 64-bit floating point moves | |
1825 | ||
1826 | (define_expand "movdf" | |
1827 | [(set (match_operand:DF 0 "") | |
1828 | (match_operand:DF 1 ""))] | |
1829 | "" | |
1830 | { | |
1831 | if (riscv_legitimize_move (DFmode, operands[0], operands[1])) | |
1832 | DONE; | |
1833 | }) | |
1834 | ||
1835 | ;; In RV32, we lack fmv.x.d and fmv.d.x. Go through memory instead. | |
1836 | ;; (However, we can still use fcvt.d.w to zero a floating-point register.) | |
1837 | (define_insn "*movdf_hardfloat_rv32" | |
1838 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m, *r,*r,*m") | |
1839 | (match_operand:DF 1 "move_operand" " f,G,m,f,G,*r*G,*m,*r"))] | |
1840 | "!TARGET_64BIT && TARGET_DOUBLE_FLOAT | |
1841 | && (register_operand (operands[0], DFmode) | |
1842 | || reg_or_0_operand (operands[1], DFmode))" | |
1843 | { return riscv_output_move (operands[0], operands[1]); } | |
1844 | [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,move,load,store") | |
1845 | (set_attr "mode" "DF")]) | |
1846 | ||
1847 | (define_insn "*movdf_hardfloat_rv64" | |
1848 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r, *r,*r,*m") | |
1849 | (match_operand:DF 1 "move_operand" " f,G,m,f,G,*r,*f,*r*G,*m,*r"))] | |
1850 | "TARGET_64BIT && TARGET_DOUBLE_FLOAT | |
1851 | && (register_operand (operands[0], DFmode) | |
1852 | || reg_or_0_operand (operands[1], DFmode))" | |
1853 | { return riscv_output_move (operands[0], operands[1]); } | |
1854 | [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") | |
1855 | (set_attr "mode" "DF")]) | |
1856 | ||
1857 | (define_insn "*movdf_softfloat" | |
1858 | [(set (match_operand:DF 0 "nonimmediate_operand" "= r,r, m") | |
1859 | (match_operand:DF 1 "move_operand" " rG,m,rG"))] | |
1860 | "!TARGET_DOUBLE_FLOAT | |
1861 | && (register_operand (operands[0], DFmode) | |
1862 | || reg_or_0_operand (operands[1], DFmode))" | |
1863 | { return riscv_output_move (operands[0], operands[1]); } | |
1864 | [(set_attr "move_type" "move,load,store") | |
1865 | (set_attr "mode" "DF")]) | |
1866 | ||
1867 | (define_split | |
1868 | [(set (match_operand:MOVE64 0 "nonimmediate_operand") | |
1869 | (match_operand:MOVE64 1 "move_operand"))] | |
1870 | "reload_completed | |
1871 | && riscv_split_64bit_move_p (operands[0], operands[1])" | |
1872 | [(const_int 0)] | |
1873 | { | |
1874 | riscv_split_doubleword_move (operands[0], operands[1]); | |
1875 | DONE; | |
1876 | }) | |
1877 | ||
1878 | (define_expand "cpymemsi" | |
1879 | [(parallel [(set (match_operand:BLK 0 "general_operand") | |
1880 | (match_operand:BLK 1 "general_operand")) | |
1881 | (use (match_operand:SI 2 "")) | |
1882 | (use (match_operand:SI 3 "const_int_operand"))])] | |
1883 | "" | |
1884 | { | |
1885 | if (riscv_expand_block_move (operands[0], operands[1], operands[2])) | |
1886 | DONE; | |
1887 | else | |
1888 | FAIL; | |
1889 | }) | |
1890 | ||
1891 | ;; Expand in-line code to clear the instruction cache between operand[0] and | |
1892 | ;; operand[1]. | |
1893 | (define_expand "clear_cache" | |
1894 | [(match_operand 0 "pmode_register_operand") | |
1895 | (match_operand 1 "pmode_register_operand")] | |
1896 | "" | |
1897 | { | |
1898 | #ifdef ICACHE_FLUSH_FUNC | |
1899 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, ICACHE_FLUSH_FUNC), | |
1900 | LCT_NORMAL, VOIDmode, operands[0], Pmode, | |
1901 | operands[1], Pmode, const0_rtx, Pmode); | |
1902 | #else | |
1903 | if (TARGET_ZIFENCEI) | |
1904 | emit_insn (gen_fence_i ()); | |
1905 | #endif | |
1906 | DONE; | |
1907 | }) | |
1908 | ||
1909 | (define_insn "fence" | |
1910 | [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)] | |
1911 | "" | |
1912 | "%|fence%-") | |
1913 | ||
1914 | (define_insn "fence_i" | |
1915 | [(unspec_volatile [(const_int 0)] UNSPECV_FENCE_I)] | |
1916 | "TARGET_ZIFENCEI" | |
1917 | "fence.i") | |
1918 | ||
1919 | (define_insn "riscv_pause" | |
1920 | [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)] | |
1921 | "" | |
1922 | "pause") | |
1923 | ||
1924 | ;; | |
1925 | ;; .................... | |
1926 | ;; | |
1927 | ;; SHIFTS | |
1928 | ;; | |
1929 | ;; .................... | |
1930 | ||
1931 | ;; Use a QImode shift count, to avoid generating sign or zero extend | |
1932 | ;; instructions for shift counts, and to avoid dropping subregs. | |
1933 | ;; expand_shift_1 can do this automatically when SHIFT_COUNT_TRUNCATED is | |
1934 | ;; defined, but use of that is discouraged. | |
1935 | ||
1936 | (define_insn "<optab>si3" | |
1937 | [(set (match_operand:SI 0 "register_operand" "= r") | |
1938 | (any_shift:SI | |
1939 | (match_operand:SI 1 "register_operand" " r") | |
1940 | (match_operand:QI 2 "arith_operand" " rI")))] | |
1941 | "" | |
1942 | { | |
1943 | if (GET_CODE (operands[2]) == CONST_INT) | |
1944 | operands[2] = GEN_INT (INTVAL (operands[2]) | |
1945 | & (GET_MODE_BITSIZE (SImode) - 1)); | |
1946 | ||
1947 | return "<insn>%i2%~\t%0,%1,%2"; | |
1948 | } | |
1949 | [(set_attr "type" "shift") | |
1950 | (set_attr "mode" "SI")]) | |
1951 | ||
1952 | (define_insn_and_split "*<optab>si3_mask" | |
1953 | [(set (match_operand:SI 0 "register_operand" "= r") | |
1954 | (any_shift:SI | |
1955 | (match_operand:SI 1 "register_operand" " r") | |
1956 | (match_operator 4 "subreg_lowpart_operator" | |
1957 | [(and:SI | |
1958 | (match_operand:SI 2 "register_operand" "r") | |
1959 | (match_operand 3 "const_int_operand"))])))] | |
1960 | "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1)) | |
1961 | == GET_MODE_BITSIZE (SImode)-1" | |
1962 | "#" | |
1963 | "&& 1" | |
1964 | [(set (match_dup 0) | |
1965 | (any_shift:SI (match_dup 1) | |
1966 | (match_dup 2)))] | |
1967 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
1968 | [(set_attr "type" "shift") | |
1969 | (set_attr "mode" "SI")]) | |
1970 | ||
1971 | (define_insn_and_split "*<optab>si3_mask_1" | |
1972 | [(set (match_operand:SI 0 "register_operand" "= r") | |
1973 | (any_shift:SI | |
1974 | (match_operand:SI 1 "register_operand" " r") | |
1975 | (match_operator 4 "subreg_lowpart_operator" | |
1976 | [(and:DI | |
1977 | (match_operand:DI 2 "register_operand" "r") | |
1978 | (match_operand 3 "const_int_operand"))])))] | |
1979 | "TARGET_64BIT | |
1980 | && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1)) | |
1981 | == GET_MODE_BITSIZE (SImode)-1" | |
1982 | "#" | |
1983 | "&& 1" | |
1984 | [(set (match_dup 0) | |
1985 | (any_shift:SI (match_dup 1) | |
1986 | (match_dup 2)))] | |
1987 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
1988 | [(set_attr "type" "shift") | |
1989 | (set_attr "mode" "SI")]) | |
1990 | ||
1991 | (define_insn "<optab>di3" | |
1992 | [(set (match_operand:DI 0 "register_operand" "= r") | |
1993 | (any_shift:DI | |
1994 | (match_operand:DI 1 "register_operand" " r") | |
1995 | (match_operand:QI 2 "arith_operand" " rI")))] | |
1996 | "TARGET_64BIT" | |
1997 | { | |
1998 | if (GET_CODE (operands[2]) == CONST_INT) | |
1999 | operands[2] = GEN_INT (INTVAL (operands[2]) | |
2000 | & (GET_MODE_BITSIZE (DImode) - 1)); | |
2001 | ||
2002 | return "<insn>%i2\t%0,%1,%2"; | |
2003 | } | |
2004 | [(set_attr "type" "shift") | |
2005 | (set_attr "mode" "DI")]) | |
2006 | ||
2007 | (define_insn_and_split "*<optab>di3_mask" | |
2008 | [(set (match_operand:DI 0 "register_operand" "= r") | |
2009 | (any_shift:DI | |
2010 | (match_operand:DI 1 "register_operand" " r") | |
2011 | (match_operator 4 "subreg_lowpart_operator" | |
2012 | [(and:SI | |
2013 | (match_operand:SI 2 "register_operand" "r") | |
2014 | (match_operand 3 "const_int_operand"))])))] | |
2015 | "TARGET_64BIT | |
2016 | && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) | |
2017 | == GET_MODE_BITSIZE (DImode)-1" | |
2018 | "#" | |
2019 | "&& 1" | |
2020 | [(set (match_dup 0) | |
2021 | (any_shift:DI (match_dup 1) | |
2022 | (match_dup 2)))] | |
2023 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
2024 | [(set_attr "type" "shift") | |
2025 | (set_attr "mode" "DI")]) | |
2026 | ||
2027 | (define_insn_and_split "*<optab>di3_mask_1" | |
2028 | [(set (match_operand:DI 0 "register_operand" "= r") | |
2029 | (any_shift:DI | |
2030 | (match_operand:DI 1 "register_operand" " r") | |
2031 | (match_operator 4 "subreg_lowpart_operator" | |
2032 | [(and:DI | |
2033 | (match_operand:DI 2 "register_operand" "r") | |
2034 | (match_operand 3 "const_int_operand"))])))] | |
2035 | "TARGET_64BIT | |
2036 | && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) | |
2037 | == GET_MODE_BITSIZE (DImode)-1" | |
2038 | "#" | |
2039 | "&& 1" | |
2040 | [(set (match_dup 0) | |
2041 | (any_shift:DI (match_dup 1) | |
2042 | (match_dup 2)))] | |
2043 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
2044 | [(set_attr "type" "shift") | |
2045 | (set_attr "mode" "DI")]) | |
2046 | ||
2047 | (define_insn "*<optab>si3_extend" | |
2048 | [(set (match_operand:DI 0 "register_operand" "= r") | |
2049 | (sign_extend:DI | |
2050 | (any_shift:SI (match_operand:SI 1 "register_operand" " r") | |
2051 | (match_operand:QI 2 "arith_operand" " rI"))))] | |
2052 | "TARGET_64BIT" | |
2053 | { | |
2054 | if (GET_CODE (operands[2]) == CONST_INT) | |
2055 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
2056 | ||
2057 | return "<insn>%i2w\t%0,%1,%2"; | |
2058 | } | |
2059 | [(set_attr "type" "shift") | |
2060 | (set_attr "mode" "SI")]) | |
2061 | ||
2062 | (define_insn_and_split "*<optab>si3_extend_mask" | |
2063 | [(set (match_operand:DI 0 "register_operand" "= r") | |
2064 | (sign_extend:DI | |
2065 | (any_shift:SI | |
2066 | (match_operand:SI 1 "register_operand" " r") | |
2067 | (match_operator 4 "subreg_lowpart_operator" | |
2068 | [(and:SI | |
2069 | (match_operand:SI 2 "register_operand" " r") | |
2070 | (match_operand 3 "const_int_operand"))]))))] | |
2071 | "TARGET_64BIT | |
2072 | && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1)) | |
2073 | == GET_MODE_BITSIZE (SImode)-1" | |
2074 | "#" | |
2075 | "&& 1" | |
2076 | [(set (match_dup 0) | |
2077 | (sign_extend:DI | |
2078 | (any_shift:SI (match_dup 1) | |
2079 | (match_dup 2))))] | |
2080 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
2081 | [(set_attr "type" "shift") | |
2082 | (set_attr "mode" "SI")]) | |
2083 | ||
2084 | (define_insn_and_split "*<optab>si3_extend_mask_1" | |
2085 | [(set (match_operand:DI 0 "register_operand" "= r") | |
2086 | (sign_extend:DI | |
2087 | (any_shift:SI | |
2088 | (match_operand:SI 1 "register_operand" " r") | |
2089 | (match_operator 4 "subreg_lowpart_operator" | |
2090 | [(and:DI | |
2091 | (match_operand:DI 2 "register_operand" " r") | |
2092 | (match_operand 3 "const_int_operand"))]))))] | |
2093 | "TARGET_64BIT | |
2094 | && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1)) | |
2095 | == GET_MODE_BITSIZE (SImode)-1" | |
2096 | "#" | |
2097 | "&& 1" | |
2098 | [(set (match_dup 0) | |
2099 | (sign_extend:DI | |
2100 | (any_shift:SI (match_dup 1) | |
2101 | (match_dup 2))))] | |
2102 | "operands[2] = gen_lowpart (QImode, operands[2]);" | |
2103 | [(set_attr "type" "shift") | |
2104 | (set_attr "mode" "SI")]) | |
2105 | ||
2106 | ;; Non-canonical, but can be formed by ree when combine is not successful at | |
2107 | ;; producing one of the two canonical patterns below. | |
2108 | (define_insn "*lshrsi3_zero_extend_1" | |
2109 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2110 | (zero_extend:DI | |
2111 | (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") | |
2112 | (match_operand 2 "const_int_operand"))))] | |
2113 | "TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0" | |
2114 | { | |
2115 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
2116 | ||
2117 | return "srliw\t%0,%1,%2"; | |
2118 | } | |
2119 | [(set_attr "type" "shift") | |
2120 | (set_attr "mode" "SI")]) | |
2121 | ||
2122 | ;; Canonical form for a zero-extend of a logical right shift. | |
2123 | (define_insn "*lshrsi3_zero_extend_2" | |
2124 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2125 | (zero_extract:DI (match_operand:DI 1 "register_operand" " r") | |
2126 | (match_operand 2 "const_int_operand") | |
2127 | (match_operand 3 "const_int_operand")))] | |
2128 | "(TARGET_64BIT && (INTVAL (operands[3]) > 0) | |
2129 | && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))" | |
2130 | { | |
2131 | return "srliw\t%0,%1,%3"; | |
2132 | } | |
2133 | [(set_attr "type" "shift") | |
2134 | (set_attr "mode" "SI")]) | |
2135 | ||
2136 | ;; Canonical form for a zero-extend of a logical right shift when the | |
2137 | ;; shift count is 31. | |
2138 | (define_insn "*lshrsi3_zero_extend_3" | |
2139 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2140 | (lt:DI (match_operand:SI 1 "register_operand" " r") | |
2141 | (const_int 0)))] | |
2142 | "TARGET_64BIT" | |
2143 | { | |
2144 | return "srliw\t%0,%1,31"; | |
2145 | } | |
2146 | [(set_attr "type" "shift") | |
2147 | (set_attr "mode" "SI")]) | |
2148 | ||
2149 | ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into | |
2150 | ;; two logical shifts. Otherwise it requires 3 instructions: lui, | |
2151 | ;; xor/addi/srli, and. | |
2152 | ||
2153 | ;; Generating a temporary for the shift output gives better combiner results; | |
2154 | ;; and also fixes a problem where op0 could be a paradoxical reg and shifting | |
2155 | ;; by amounts larger than the size of the SUBREG_REG doesn't work. | |
2156 | (define_split | |
2157 | [(set (match_operand:GPR 0 "register_operand") | |
2158 | (and:GPR (match_operand:GPR 1 "register_operand") | |
2159 | (match_operand:GPR 2 "p2m1_shift_operand"))) | |
2160 | (clobber (match_operand:GPR 3 "register_operand"))] | |
2161 | "" | |
2162 | [(set (match_dup 3) | |
2163 | (ashift:GPR (match_dup 1) (match_dup 2))) | |
2164 | (set (match_dup 0) | |
2165 | (lshiftrt:GPR (match_dup 3) (match_dup 2)))] | |
2166 | { | |
2167 | /* Op2 is a VOIDmode constant, so get the mode size from op1. */ | |
2168 | operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant () | |
2169 | - exact_log2 (INTVAL (operands[2]) + 1)); | |
2170 | }) | |
2171 | ||
2172 | ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be | |
2173 | ;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and. | |
2174 | (define_split | |
2175 | [(set (match_operand:DI 0 "register_operand") | |
2176 | (and:DI (match_operand:DI 1 "register_operand") | |
2177 | (match_operand:DI 2 "high_mask_shift_operand"))) | |
2178 | (clobber (match_operand:DI 3 "register_operand"))] | |
2179 | "TARGET_64BIT" | |
2180 | [(set (match_dup 3) | |
2181 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
2182 | (set (match_dup 0) | |
2183 | (ashift:DI (match_dup 3) (match_dup 2)))] | |
2184 | { | |
2185 | operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2]))); | |
2186 | }) | |
2187 | ||
2188 | ;; Handle SImode to DImode zero-extend combined with a left shift. This can | |
2189 | ;; occur when unsigned int is used for array indexing. Split this into two | |
2190 | ;; shifts. Otherwise we can get 3 shifts. | |
2191 | ||
2192 | (define_insn_and_split "zero_extendsidi2_shifted" | |
2193 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2194 | (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") | |
2195 | (match_operand:QI 2 "immediate_operand" "I")) | |
2196 | (match_operand 3 "immediate_operand" ""))) | |
2197 | (clobber (match_scratch:DI 4 "=&r"))] | |
2198 | "TARGET_64BIT && !TARGET_ZBA | |
2199 | && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" | |
2200 | "#" | |
2201 | "&& reload_completed" | |
2202 | [(set (match_dup 4) | |
2203 | (ashift:DI (match_dup 1) (const_int 32))) | |
2204 | (set (match_dup 0) | |
2205 | (lshiftrt:DI (match_dup 4) (match_dup 5)))] | |
2206 | "operands[5] = GEN_INT (32 - (INTVAL (operands [2])));" | |
2207 | [(set_attr "type" "shift") | |
2208 | (set_attr "mode" "DI")]) | |
2209 | ||
2210 | ;; | |
2211 | ;; .................... | |
2212 | ;; | |
2213 | ;; CONDITIONAL BRANCHES | |
2214 | ;; | |
2215 | ;; .................... | |
2216 | ||
2217 | ;; Conditional branches | |
2218 | ||
2219 | (define_insn "*branch<mode>" | |
2220 | [(set (pc) | |
2221 | (if_then_else | |
2222 | (match_operator 1 "order_operator" | |
2223 | [(match_operand:X 2 "register_operand" "r") | |
2224 | (match_operand:X 3 "reg_or_0_operand" "rJ")]) | |
2225 | (label_ref (match_operand 0 "" "")) | |
2226 | (pc)))] | |
2227 | "" | |
2228 | "b%C1\t%2,%z3,%0" | |
2229 | [(set_attr "type" "branch") | |
2230 | (set_attr "mode" "none")]) | |
2231 | ||
2232 | ;; Patterns for implementations that optimize short forward branches. | |
2233 | ||
2234 | (define_expand "mov<mode>cc" | |
2235 | [(set (match_operand:GPR 0 "register_operand") | |
2236 | (if_then_else:GPR (match_operand 1 "comparison_operator") | |
2237 | (match_operand:GPR 2 "register_operand") | |
2238 | (match_operand:GPR 3 "sfb_alu_operand")))] | |
2239 | "TARGET_SFB_ALU" | |
2240 | { | |
2241 | rtx cmp = operands[1]; | |
2242 | /* We only handle word mode integer compares for now. */ | |
2243 | if (GET_MODE (XEXP (cmp, 0)) != word_mode) | |
2244 | FAIL; | |
2245 | riscv_expand_conditional_move (operands[0], operands[2], operands[3], | |
2246 | GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1)); | |
2247 | DONE; | |
2248 | }) | |
2249 | ||
2250 | (define_insn "*mov<GPR:mode><X:mode>cc" | |
2251 | [(set (match_operand:GPR 0 "register_operand" "=r,r") | |
2252 | (if_then_else:GPR | |
2253 | (match_operator 5 "order_operator" | |
2254 | [(match_operand:X 1 "register_operand" "r,r") | |
2255 | (match_operand:X 2 "reg_or_0_operand" "rJ,rJ")]) | |
2256 | (match_operand:GPR 3 "register_operand" "0,0") | |
2257 | (match_operand:GPR 4 "sfb_alu_operand" "rJ,IL")))] | |
2258 | "TARGET_SFB_ALU" | |
2259 | "@ | |
2260 | b%C5\t%1,%z2,1f\t# movcc\;mv\t%0,%z4\n1: | |
2261 | b%C5\t%1,%z2,1f\t# movcc\;li\t%0,%4\n1:" | |
2262 | [(set_attr "length" "8") | |
2263 | (set_attr "type" "sfb_alu") | |
2264 | (set_attr "mode" "<GPR:MODE>")]) | |
2265 | ||
2266 | ;; Used to implement built-in functions. | |
2267 | (define_expand "condjump" | |
2268 | [(set (pc) | |
2269 | (if_then_else (match_operand 0) | |
2270 | (label_ref (match_operand 1)) | |
2271 | (pc)))]) | |
2272 | ||
2273 | (define_expand "@cbranch<mode>4" | |
2274 | [(set (pc) | |
2275 | (if_then_else (match_operator 0 "comparison_operator" | |
2276 | [(match_operand:BR 1 "register_operand") | |
2277 | (match_operand:BR 2 "nonmemory_operand")]) | |
2278 | (label_ref (match_operand 3 "")) | |
2279 | (pc)))] | |
2280 | "" | |
2281 | { | |
2282 | riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]), | |
2283 | operands[1], operands[2]); | |
2284 | DONE; | |
2285 | }) | |
2286 | ||
2287 | (define_expand "@cbranch<mode>4" | |
2288 | [(set (pc) | |
2289 | (if_then_else (match_operator 0 "fp_branch_comparison" | |
2290 | [(match_operand:ANYF 1 "register_operand") | |
2291 | (match_operand:ANYF 2 "register_operand")]) | |
2292 | (label_ref (match_operand 3 "")) | |
2293 | (pc)))] | |
2294 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2295 | { | |
2296 | riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]), | |
2297 | operands[1], operands[2]); | |
2298 | DONE; | |
2299 | }) | |
2300 | ||
2301 | (define_insn_and_split "*branch_on_bit<X:mode>" | |
2302 | [(set (pc) | |
2303 | (if_then_else | |
2304 | (match_operator 0 "equality_operator" | |
2305 | [(zero_extract:X (match_operand:X 2 "register_operand" "r") | |
2306 | (const_int 1) | |
2307 | (match_operand 3 "branch_on_bit_operand")) | |
2308 | (const_int 0)]) | |
2309 | (label_ref (match_operand 1)) | |
2310 | (pc))) | |
2311 | (clobber (match_scratch:X 4 "=&r"))] | |
2312 | "" | |
2313 | "#" | |
2314 | "reload_completed" | |
2315 | [(set (match_dup 4) | |
2316 | (ashift:X (match_dup 2) (match_dup 3))) | |
2317 | (set (pc) | |
2318 | (if_then_else | |
2319 | (match_op_dup 0 [(match_dup 4) (const_int 0)]) | |
2320 | (label_ref (match_operand 1)) | |
2321 | (pc)))] | |
2322 | { | |
2323 | int shift = GET_MODE_BITSIZE (<MODE>mode) - 1 - INTVAL (operands[3]); | |
2324 | operands[3] = GEN_INT (shift); | |
2325 | ||
2326 | if (GET_CODE (operands[0]) == EQ) | |
2327 | operands[0] = gen_rtx_GE (<MODE>mode, operands[4], const0_rtx); | |
2328 | else | |
2329 | operands[0] = gen_rtx_LT (<MODE>mode, operands[4], const0_rtx); | |
2330 | }) | |
2331 | ||
2332 | (define_insn_and_split "*branch_on_bit_range<X:mode>" | |
2333 | [(set (pc) | |
2334 | (if_then_else | |
2335 | (match_operator 0 "equality_operator" | |
2336 | [(zero_extract:X (match_operand:X 2 "register_operand" "r") | |
2337 | (match_operand 3 "branch_on_bit_operand") | |
2338 | (const_int 0)) | |
2339 | (const_int 0)]) | |
2340 | (label_ref (match_operand 1)) | |
2341 | (pc))) | |
2342 | (clobber (match_scratch:X 4 "=&r"))] | |
2343 | "" | |
2344 | "#" | |
2345 | "reload_completed" | |
2346 | [(set (match_dup 4) | |
2347 | (ashift:X (match_dup 2) (match_dup 3))) | |
2348 | (set (pc) | |
2349 | (if_then_else | |
2350 | (match_op_dup 0 [(match_dup 4) (const_int 0)]) | |
2351 | (label_ref (match_operand 1)) | |
2352 | (pc)))] | |
2353 | { | |
2354 | operands[3] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[3])); | |
2355 | }) | |
2356 | ||
2357 | ;; | |
2358 | ;; .................... | |
2359 | ;; | |
2360 | ;; SETTING A REGISTER FROM A COMPARISON | |
2361 | ;; | |
2362 | ;; .................... | |
2363 | ||
2364 | ;; Destination is always set in SI mode. | |
2365 | ||
2366 | (define_expand "cstore<mode>4" | |
2367 | [(set (match_operand:SI 0 "register_operand") | |
2368 | (match_operator:SI 1 "order_operator" | |
2369 | [(match_operand:GPR 2 "register_operand") | |
2370 | (match_operand:GPR 3 "nonmemory_operand")]))] | |
2371 | "" | |
2372 | { | |
2373 | riscv_expand_int_scc (operands[0], GET_CODE (operands[1]), operands[2], | |
2374 | operands[3]); | |
2375 | DONE; | |
2376 | }) | |
2377 | ||
2378 | (define_expand "cstore<mode>4" | |
2379 | [(set (match_operand:SI 0 "register_operand") | |
2380 | (match_operator:SI 1 "fp_scc_comparison" | |
2381 | [(match_operand:ANYF 2 "register_operand") | |
2382 | (match_operand:ANYF 3 "register_operand")]))] | |
2383 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2384 | { | |
2385 | riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2], | |
2386 | operands[3]); | |
2387 | DONE; | |
2388 | }) | |
2389 | ||
2390 | (define_insn "*cstore<ANYF:mode><X:mode>4" | |
2391 | [(set (match_operand:X 0 "register_operand" "=r") | |
2392 | (match_operator:X 1 "fp_native_comparison" | |
2393 | [(match_operand:ANYF 2 "register_operand" " f") | |
2394 | (match_operand:ANYF 3 "register_operand" " f")]))] | |
2395 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2396 | "f%C1.<fmt>\t%0,%2,%3" | |
2397 | [(set_attr "type" "fcmp") | |
2398 | (set_attr "mode" "<UNITMODE>")]) | |
2399 | ||
2400 | (define_expand "f<quiet_pattern>_quiet<ANYF:mode><X:mode>4" | |
2401 | [(set (match_operand:X 0 "register_operand") | |
2402 | (unspec:X [(match_operand:ANYF 1 "register_operand") | |
2403 | (match_operand:ANYF 2 "register_operand")] | |
2404 | QUIET_COMPARISON))] | |
2405 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2406 | { | |
2407 | rtx op0 = operands[0]; | |
2408 | rtx op1 = operands[1]; | |
2409 | rtx op2 = operands[2]; | |
2410 | rtx tmp = gen_reg_rtx (SImode); | |
2411 | rtx cmp = gen_rtx_<QUIET_PATTERN> (<X:MODE>mode, op1, op2); | |
2412 | rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx), | |
2413 | UNSPECV_FRFLAGS); | |
2414 | rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp), | |
2415 | UNSPECV_FSFLAGS); | |
2416 | ||
2417 | emit_insn (gen_rtx_SET (tmp, frflags)); | |
2418 | emit_insn (gen_rtx_SET (op0, cmp)); | |
2419 | emit_insn (fsflags); | |
2420 | if (HONOR_SNANS (<ANYF:MODE>mode)) | |
2421 | emit_insn (gen_rtx_UNSPEC_VOLATILE (<ANYF:MODE>mode, | |
2422 | gen_rtvec (2, op1, op2), | |
2423 | UNSPECV_FSNVSNAN)); | |
2424 | DONE; | |
2425 | }) | |
2426 | ||
2427 | (define_insn "*seq_zero_<X:mode><GPR:mode>" | |
2428 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
2429 | (eq:GPR (match_operand:X 1 "register_operand" " r") | |
2430 | (const_int 0)))] | |
2431 | "" | |
2432 | "seqz\t%0,%1" | |
2433 | [(set_attr "type" "slt") | |
2434 | (set_attr "mode" "<X:MODE>")]) | |
2435 | ||
2436 | (define_insn "*sne_zero_<X:mode><GPR:mode>" | |
2437 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
2438 | (ne:GPR (match_operand:X 1 "register_operand" " r") | |
2439 | (const_int 0)))] | |
2440 | "" | |
2441 | "snez\t%0,%1" | |
2442 | [(set_attr "type" "slt") | |
2443 | (set_attr "mode" "<X:MODE>")]) | |
2444 | ||
2445 | (define_insn "*sgt<u>_<X:mode><GPR:mode>" | |
2446 | [(set (match_operand:GPR 0 "register_operand" "= r") | |
2447 | (any_gt:GPR (match_operand:X 1 "register_operand" " r") | |
2448 | (match_operand:X 2 "reg_or_0_operand" " rJ")))] | |
2449 | "" | |
2450 | "sgt<u>\t%0,%1,%z2" | |
2451 | [(set_attr "type" "slt") | |
2452 | (set_attr "mode" "<X:MODE>")]) | |
2453 | ||
2454 | (define_insn "*sge<u>_<X:mode><GPR:mode>" | |
2455 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
2456 | (any_ge:GPR (match_operand:X 1 "register_operand" " r") | |
2457 | (const_int 1)))] | |
2458 | "" | |
2459 | "slt%i2<u>\t%0,zero,%1" | |
2460 | [(set_attr "type" "slt") | |
2461 | (set_attr "mode" "<X:MODE>")]) | |
2462 | ||
2463 | (define_insn "*slt<u>_<X:mode><GPR:mode>" | |
2464 | [(set (match_operand:GPR 0 "register_operand" "= r") | |
2465 | (any_lt:GPR (match_operand:X 1 "register_operand" " r") | |
2466 | (match_operand:X 2 "arith_operand" " rI")))] | |
2467 | "" | |
2468 | "slt%i2<u>\t%0,%1,%2" | |
2469 | [(set_attr "type" "slt") | |
2470 | (set_attr "mode" "<X:MODE>")]) | |
2471 | ||
2472 | (define_insn "*sle<u>_<X:mode><GPR:mode>" | |
2473 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
2474 | (any_le:GPR (match_operand:X 1 "register_operand" " r") | |
2475 | (match_operand:X 2 "sle_operand" "")))] | |
2476 | "" | |
2477 | { | |
2478 | operands[2] = GEN_INT (INTVAL (operands[2]) + 1); | |
2479 | return "slt%i2<u>\t%0,%1,%2"; | |
2480 | } | |
2481 | [(set_attr "type" "slt") | |
2482 | (set_attr "mode" "<X:MODE>")]) | |
2483 | ||
2484 | ;; | |
2485 | ;; .................... | |
2486 | ;; | |
2487 | ;; UNCONDITIONAL BRANCHES | |
2488 | ;; | |
2489 | ;; .................... | |
2490 | ||
2491 | ;; Unconditional branches. | |
2492 | ||
2493 | (define_insn "jump" | |
2494 | [(set (pc) | |
2495 | (label_ref (match_operand 0 "" "")))] | |
2496 | "" | |
2497 | "j\t%l0" | |
2498 | [(set_attr "type" "jump") | |
2499 | (set_attr "mode" "none")]) | |
2500 | ||
2501 | (define_expand "indirect_jump" | |
2502 | [(set (pc) (match_operand 0 "register_operand"))] | |
2503 | "" | |
2504 | { | |
2505 | operands[0] = force_reg (Pmode, operands[0]); | |
2506 | if (Pmode == SImode) | |
2507 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
2508 | else | |
2509 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
2510 | DONE; | |
2511 | }) | |
2512 | ||
2513 | (define_insn "indirect_jump<mode>" | |
2514 | [(set (pc) (match_operand:P 0 "register_operand" "l"))] | |
2515 | "" | |
2516 | "jr\t%0" | |
2517 | [(set_attr "type" "jump") | |
2518 | (set_attr "mode" "none")]) | |
2519 | ||
2520 | (define_expand "tablejump" | |
2521 | [(set (pc) (match_operand 0 "register_operand" "")) | |
2522 | (use (label_ref (match_operand 1 "" "")))] | |
2523 | "" | |
2524 | { | |
2525 | if (CASE_VECTOR_PC_RELATIVE) | |
2526 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
2527 | gen_rtx_LABEL_REF (Pmode, operands[1]), | |
2528 | NULL_RTX, 0, OPTAB_DIRECT); | |
2529 | ||
2530 | if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode) | |
2531 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
2532 | else | |
2533 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
2534 | DONE; | |
2535 | }) | |
2536 | ||
2537 | (define_insn "tablejump<mode>" | |
2538 | [(set (pc) (match_operand:GPR 0 "register_operand" "l")) | |
2539 | (use (label_ref (match_operand 1 "" "")))] | |
2540 | "" | |
2541 | "jr\t%0" | |
2542 | [(set_attr "type" "jump") | |
2543 | (set_attr "mode" "none")]) | |
2544 | ||
2545 | ;; | |
2546 | ;; .................... | |
2547 | ;; | |
2548 | ;; Function prologue/epilogue | |
2549 | ;; | |
2550 | ;; .................... | |
2551 | ;; | |
2552 | ||
2553 | (define_expand "prologue" | |
2554 | [(const_int 1)] | |
2555 | "" | |
2556 | { | |
2557 | riscv_expand_prologue (); | |
2558 | DONE; | |
2559 | }) | |
2560 | ||
2561 | ;; Block any insns from being moved before this point, since the | |
2562 | ;; profiling call to mcount can use various registers that aren't | |
2563 | ;; saved or used to pass arguments. | |
2564 | ||
2565 | (define_insn "blockage" | |
2566 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] | |
2567 | "" | |
2568 | "" | |
2569 | [(set_attr "type" "ghost") | |
2570 | (set_attr "mode" "none")]) | |
2571 | ||
2572 | (define_expand "epilogue" | |
2573 | [(const_int 2)] | |
2574 | "" | |
2575 | { | |
2576 | riscv_expand_epilogue (NORMAL_RETURN); | |
2577 | DONE; | |
2578 | }) | |
2579 | ||
2580 | (define_expand "sibcall_epilogue" | |
2581 | [(const_int 2)] | |
2582 | "" | |
2583 | { | |
2584 | riscv_expand_epilogue (SIBCALL_RETURN); | |
2585 | DONE; | |
2586 | }) | |
2587 | ||
2588 | ;; Trivial return. Make it look like a normal return insn as that | |
2589 | ;; allows jump optimizations to work better. | |
2590 | ||
2591 | (define_expand "return" | |
2592 | [(simple_return)] | |
2593 | "riscv_can_use_return_insn ()" | |
2594 | "") | |
2595 | ||
2596 | (define_insn "simple_return" | |
2597 | [(simple_return)] | |
2598 | "" | |
2599 | { | |
2600 | return riscv_output_return (); | |
2601 | } | |
2602 | [(set_attr "type" "jump") | |
2603 | (set_attr "mode" "none")]) | |
2604 | ||
2605 | ;; Normal return. | |
2606 | ||
2607 | (define_insn "simple_return_internal" | |
2608 | [(simple_return) | |
2609 | (use (match_operand 0 "pmode_register_operand" ""))] | |
2610 | "" | |
2611 | "jr\t%0" | |
2612 | [(set_attr "type" "jump") | |
2613 | (set_attr "mode" "none")]) | |
2614 | ||
2615 | ;; This is used in compiling the unwind routines. | |
2616 | (define_expand "eh_return" | |
2617 | [(use (match_operand 0 "general_operand"))] | |
2618 | "" | |
2619 | { | |
2620 | if (GET_MODE (operands[0]) != word_mode) | |
2621 | operands[0] = convert_to_mode (word_mode, operands[0], 0); | |
2622 | if (TARGET_64BIT) | |
2623 | emit_insn (gen_eh_set_lr_di (operands[0])); | |
2624 | else | |
2625 | emit_insn (gen_eh_set_lr_si (operands[0])); | |
2626 | ||
2627 | emit_jump_insn (gen_eh_return_internal ()); | |
2628 | emit_barrier (); | |
2629 | DONE; | |
2630 | }) | |
2631 | ||
2632 | ;; Clobber the return address on the stack. We can't expand this | |
2633 | ;; until we know where it will be put in the stack frame. | |
2634 | ||
2635 | (define_insn "eh_set_lr_si" | |
2636 | [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN) | |
2637 | (clobber (match_scratch:SI 1 "=&r"))] | |
2638 | "! TARGET_64BIT" | |
2639 | "#") | |
2640 | ||
2641 | (define_insn "eh_set_lr_di" | |
2642 | [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN) | |
2643 | (clobber (match_scratch:DI 1 "=&r"))] | |
2644 | "TARGET_64BIT" | |
2645 | "#") | |
2646 | ||
2647 | (define_split | |
2648 | [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) | |
2649 | (clobber (match_scratch 1))] | |
2650 | "reload_completed" | |
2651 | [(const_int 0)] | |
2652 | { | |
2653 | riscv_set_return_address (operands[0], operands[1]); | |
2654 | DONE; | |
2655 | }) | |
2656 | ||
2657 | (define_insn_and_split "eh_return_internal" | |
2658 | [(eh_return)] | |
2659 | "" | |
2660 | "#" | |
2661 | "epilogue_completed" | |
2662 | [(const_int 0)] | |
2663 | "riscv_expand_epilogue (EXCEPTION_RETURN); DONE;") | |
2664 | ||
2665 | ;; | |
2666 | ;; .................... | |
2667 | ;; | |
2668 | ;; FUNCTION CALLS | |
2669 | ;; | |
2670 | ;; .................... | |
2671 | ||
2672 | (define_expand "sibcall" | |
2673 | [(parallel [(call (match_operand 0 "") | |
2674 | (match_operand 1 "")) | |
2675 | (use (match_operand 2 "")) ;; next_arg_reg | |
2676 | (use (match_operand 3 ""))])] ;; struct_value_size_rtx | |
2677 | "" | |
2678 | { | |
2679 | rtx target = riscv_legitimize_call_address (XEXP (operands[0], 0)); | |
2680 | emit_call_insn (gen_sibcall_internal (target, operands[1])); | |
2681 | DONE; | |
2682 | }) | |
2683 | ||
2684 | (define_insn "sibcall_internal" | |
2685 | [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S,U")) | |
2686 | (match_operand 1 "" ""))] | |
2687 | "SIBLING_CALL_P (insn)" | |
2688 | "@ | |
2689 | jr\t%0 | |
2690 | tail\t%0 | |
2691 | tail\t%0@plt" | |
2692 | [(set_attr "type" "call")]) | |
2693 | ||
2694 | (define_expand "sibcall_value" | |
2695 | [(parallel [(set (match_operand 0 "") | |
2696 | (call (match_operand 1 "") | |
2697 | (match_operand 2 ""))) | |
2698 | (use (match_operand 3 ""))])] ;; next_arg_reg | |
2699 | "" | |
2700 | { | |
2701 | rtx target = riscv_legitimize_call_address (XEXP (operands[1], 0)); | |
2702 | emit_call_insn (gen_sibcall_value_internal (operands[0], target, operands[2])); | |
2703 | DONE; | |
2704 | }) | |
2705 | ||
2706 | (define_insn "sibcall_value_internal" | |
2707 | [(set (match_operand 0 "" "") | |
2708 | (call (mem:SI (match_operand 1 "call_insn_operand" "j,S,U")) | |
2709 | (match_operand 2 "" "")))] | |
2710 | "SIBLING_CALL_P (insn)" | |
2711 | "@ | |
2712 | jr\t%1 | |
2713 | tail\t%1 | |
2714 | tail\t%1@plt" | |
2715 | [(set_attr "type" "call")]) | |
2716 | ||
2717 | (define_expand "call" | |
2718 | [(parallel [(call (match_operand 0 "") | |
2719 | (match_operand 1 "")) | |
2720 | (use (match_operand 2 "")) ;; next_arg_reg | |
2721 | (use (match_operand 3 ""))])] ;; struct_value_size_rtx | |
2722 | "" | |
2723 | { | |
2724 | rtx target = riscv_legitimize_call_address (XEXP (operands[0], 0)); | |
2725 | emit_call_insn (gen_call_internal (target, operands[1])); | |
2726 | DONE; | |
2727 | }) | |
2728 | ||
2729 | (define_insn "call_internal" | |
2730 | [(call (mem:SI (match_operand 0 "call_insn_operand" "l,S,U")) | |
2731 | (match_operand 1 "" "")) | |
2732 | (clobber (reg:SI RETURN_ADDR_REGNUM))] | |
2733 | "" | |
2734 | "@ | |
2735 | jalr\t%0 | |
2736 | call\t%0 | |
2737 | call\t%0@plt" | |
2738 | [(set_attr "type" "call")]) | |
2739 | ||
2740 | (define_expand "call_value" | |
2741 | [(parallel [(set (match_operand 0 "") | |
2742 | (call (match_operand 1 "") | |
2743 | (match_operand 2 ""))) | |
2744 | (use (match_operand 3 ""))])] ;; next_arg_reg | |
2745 | "" | |
2746 | { | |
2747 | rtx target = riscv_legitimize_call_address (XEXP (operands[1], 0)); | |
2748 | emit_call_insn (gen_call_value_internal (operands[0], target, operands[2])); | |
2749 | DONE; | |
2750 | }) | |
2751 | ||
2752 | (define_insn "call_value_internal" | |
2753 | [(set (match_operand 0 "" "") | |
2754 | (call (mem:SI (match_operand 1 "call_insn_operand" "l,S,U")) | |
2755 | (match_operand 2 "" ""))) | |
2756 | (clobber (reg:SI RETURN_ADDR_REGNUM))] | |
2757 | "" | |
2758 | "@ | |
2759 | jalr\t%1 | |
2760 | call\t%1 | |
2761 | call\t%1@plt" | |
2762 | [(set_attr "type" "call")]) | |
2763 | ||
2764 | ;; Call subroutine returning any type. | |
2765 | ||
2766 | (define_expand "untyped_call" | |
2767 | [(parallel [(call (match_operand 0 "") | |
2768 | (const_int 0)) | |
2769 | (match_operand 1 "") | |
2770 | (match_operand 2 "")])] | |
2771 | "" | |
2772 | { | |
2773 | int i; | |
2774 | ||
2775 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
2776 | ||
2777 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
2778 | { | |
2779 | rtx set = XVECEXP (operands[2], 0, i); | |
2780 | riscv_emit_move (SET_DEST (set), SET_SRC (set)); | |
2781 | } | |
2782 | ||
2783 | emit_insn (gen_blockage ()); | |
2784 | DONE; | |
2785 | }) | |
2786 | ||
2787 | (define_insn "nop" | |
2788 | [(const_int 0)] | |
2789 | "" | |
2790 | "nop" | |
2791 | [(set_attr "type" "nop") | |
2792 | (set_attr "mode" "none")]) | |
2793 | ||
2794 | (define_insn "trap" | |
2795 | [(trap_if (const_int 1) (const_int 0))] | |
2796 | "" | |
2797 | "ebreak") | |
2798 | ||
2799 | ;; Must use the registers that we save to prevent the rename reg optimization | |
2800 | ;; pass from using them before the gpr_save pattern when shrink wrapping | |
2801 | ;; occurs. See bug 95252 for instance. | |
2802 | ||
2803 | (define_insn "gpr_save" | |
2804 | [(match_parallel 1 "gpr_save_operation" | |
2805 | [(unspec_volatile [(match_operand 0 "const_int_operand")] | |
2806 | UNSPECV_GPR_SAVE)])] | |
2807 | "" | |
2808 | "call\tt0,__riscv_save_%0") | |
2809 | ||
2810 | (define_insn "gpr_restore" | |
2811 | [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_RESTORE)] | |
2812 | "" | |
2813 | "tail\t__riscv_restore_%0") | |
2814 | ||
2815 | (define_insn "gpr_restore_return" | |
2816 | [(return) | |
2817 | (use (match_operand 0 "pmode_register_operand" "")) | |
2818 | (const_int 0)] | |
2819 | "" | |
2820 | "") | |
2821 | ||
2822 | (define_insn "riscv_frflags" | |
2823 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2824 | (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] | |
2825 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2826 | "frflags\t%0") | |
2827 | ||
2828 | (define_insn "riscv_fsflags" | |
2829 | [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)] | |
2830 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2831 | "fsflags\t%0") | |
2832 | ||
2833 | (define_insn "*riscv_fsnvsnan<mode>2" | |
2834 | [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f") | |
2835 | (match_operand:ANYF 1 "register_operand" "f")] | |
2836 | UNSPECV_FSNVSNAN)] | |
2837 | "TARGET_HARD_FLOAT || TARGET_ZFINX" | |
2838 | "feq.<fmt>\tzero,%0,%1" | |
2839 | [(set_attr "type" "fcmp") | |
2840 | (set_attr "mode" "<UNITMODE>")]) | |
2841 | ||
2842 | (define_insn "riscv_mret" | |
2843 | [(return) | |
2844 | (unspec_volatile [(const_int 0)] UNSPECV_MRET)] | |
2845 | "" | |
2846 | "mret") | |
2847 | ||
2848 | (define_insn "riscv_sret" | |
2849 | [(return) | |
2850 | (unspec_volatile [(const_int 0)] UNSPECV_SRET)] | |
2851 | "" | |
2852 | "sret") | |
2853 | ||
2854 | (define_insn "riscv_uret" | |
2855 | [(return) | |
2856 | (unspec_volatile [(const_int 0)] UNSPECV_URET)] | |
2857 | "" | |
2858 | "uret") | |
2859 | ||
2860 | (define_insn "stack_tie<mode>" | |
2861 | [(set (mem:BLK (scratch)) | |
2862 | (unspec:BLK [(match_operand:X 0 "register_operand" "r") | |
2863 | (match_operand:X 1 "register_operand" "r")] | |
2864 | UNSPEC_TIE))] | |
2865 | "" | |
2866 | "" | |
2867 | [(set_attr "length" "0")] | |
2868 | ) | |
2869 | ||
2870 | ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a | |
2871 | ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass | |
2872 | ;; runs before register elimination, and we have a non-obvious dependency | |
2873 | ;; between a use of the soft fp and a set of the hard fp. We fix this by | |
2874 | ;; emitting a clobber using the hard fp between the two insns. | |
2875 | (define_expand "restore_stack_nonlocal" | |
2876 | [(match_operand 0 "register_operand") | |
2877 | (match_operand 1 "memory_operand")] | |
2878 | "" | |
2879 | { | |
2880 | emit_move_insn (operands[0], operands[1]); | |
2881 | /* Prevent the following hard fp restore from being moved before the move | |
2882 | insn above which uses a copy of the soft fp reg. */ | |
2883 | emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); | |
2884 | DONE; | |
2885 | }) | |
2886 | ||
2887 | ;; Named pattern for expanding thread pointer reference. | |
2888 | (define_expand "get_thread_pointer<mode>" | |
2889 | [(set (match_operand:P 0 "register_operand" "=r") | |
2890 | (reg:P TP_REGNUM))] | |
2891 | "" | |
2892 | {}) | |
2893 | ||
2894 | ;; Named patterns for stack smashing protection. | |
2895 | ||
2896 | (define_expand "stack_protect_set" | |
2897 | [(match_operand 0 "memory_operand") | |
2898 | (match_operand 1 "memory_operand")] | |
2899 | "" | |
2900 | { | |
2901 | machine_mode mode = GET_MODE (operands[0]); | |
2902 | if (riscv_stack_protector_guard == SSP_TLS) | |
2903 | { | |
2904 | rtx reg = gen_rtx_REG (Pmode, riscv_stack_protector_guard_reg); | |
2905 | rtx offset = GEN_INT (riscv_stack_protector_guard_offset); | |
2906 | rtx addr = gen_rtx_PLUS (Pmode, reg, offset); | |
2907 | operands[1] = gen_rtx_MEM (Pmode, addr); | |
2908 | } | |
2909 | ||
2910 | emit_insn ((mode == DImode | |
2911 | ? gen_stack_protect_set_di | |
2912 | : gen_stack_protect_set_si) (operands[0], operands[1])); | |
2913 | DONE; | |
2914 | }) | |
2915 | ||
2916 | ;; DO NOT SPLIT THIS PATTERN. It is important for security reasons that the | |
2917 | ;; canary value does not live beyond the life of this sequence. | |
2918 | (define_insn "stack_protect_set_<mode>" | |
2919 | [(set (match_operand:GPR 0 "memory_operand" "=m") | |
2920 | (unspec:GPR [(match_operand:GPR 1 "memory_operand" "m")] | |
2921 | UNSPEC_SSP_SET)) | |
2922 | (set (match_scratch:GPR 2 "=&r") (const_int 0))] | |
2923 | "" | |
2924 | "<load>\t%2, %1\;<store>\t%2, %0\;li\t%2, 0" | |
2925 | [(set_attr "length" "12")]) | |
2926 | ||
2927 | (define_expand "stack_protect_test" | |
2928 | [(match_operand 0 "memory_operand") | |
2929 | (match_operand 1 "memory_operand") | |
2930 | (match_operand 2)] | |
2931 | "" | |
2932 | { | |
2933 | rtx result; | |
2934 | machine_mode mode = GET_MODE (operands[0]); | |
2935 | ||
2936 | result = gen_reg_rtx(mode); | |
2937 | if (riscv_stack_protector_guard == SSP_TLS) | |
2938 | { | |
2939 | rtx reg = gen_rtx_REG (Pmode, riscv_stack_protector_guard_reg); | |
2940 | rtx offset = GEN_INT (riscv_stack_protector_guard_offset); | |
2941 | rtx addr = gen_rtx_PLUS (Pmode, reg, offset); | |
2942 | operands[1] = gen_rtx_MEM (Pmode, addr); | |
2943 | } | |
2944 | emit_insn ((mode == DImode | |
2945 | ? gen_stack_protect_test_di | |
2946 | : gen_stack_protect_test_si) (result, | |
2947 | operands[0], | |
2948 | operands[1])); | |
2949 | ||
2950 | rtx cond = gen_rtx_EQ (VOIDmode, result, const0_rtx); | |
2951 | emit_jump_insn (gen_cbranch4 (mode, cond, result, const0_rtx, operands[2])); | |
2952 | ||
2953 | DONE; | |
2954 | }) | |
2955 | ||
2956 | (define_insn "stack_protect_test_<mode>" | |
2957 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
2958 | (unspec:GPR [(match_operand:GPR 1 "memory_operand" "m") | |
2959 | (match_operand:GPR 2 "memory_operand" "m")] | |
2960 | UNSPEC_SSP_TEST)) | |
2961 | (clobber (match_scratch:GPR 3 "=&r"))] | |
2962 | "" | |
2963 | "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" | |
2964 | [(set_attr "length" "12")]) | |
2965 | ||
2966 | (define_insn "riscv_clean_<mode>" | |
2967 | [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] | |
2968 | UNSPECV_CLEAN)] | |
2969 | "TARGET_ZICBOM" | |
2970 | "cbo.clean\t%a0" | |
2971 | ) | |
2972 | ||
2973 | (define_insn "riscv_flush_<mode>" | |
2974 | [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] | |
2975 | UNSPECV_FLUSH)] | |
2976 | "TARGET_ZICBOM" | |
2977 | "cbo.flush\t%a0" | |
2978 | ) | |
2979 | ||
2980 | (define_insn "riscv_inval_<mode>" | |
2981 | [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] | |
2982 | UNSPECV_INVAL)] | |
2983 | "TARGET_ZICBOM" | |
2984 | "cbo.inval\t%a0" | |
2985 | ) | |
2986 | ||
2987 | (define_insn "riscv_zero_<mode>" | |
2988 | [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] | |
2989 | UNSPECV_ZERO)] | |
2990 | "TARGET_ZICBOZ" | |
2991 | "cbo.zero\t%a0" | |
2992 | ) | |
2993 | ||
2994 | (define_insn "prefetch" | |
2995 | [(prefetch (match_operand 0 "address_operand" "p") | |
2996 | (match_operand 1 "imm5_operand" "i") | |
2997 | (match_operand 2 "const_int_operand" "n"))] | |
2998 | "TARGET_ZICBOP" | |
2999 | { | |
3000 | switch (INTVAL (operands[1])) | |
3001 | { | |
3002 | case 0: return "prefetch.r\t%a0"; | |
3003 | case 1: return "prefetch.w\t%a0"; | |
3004 | default: gcc_unreachable (); | |
3005 | } | |
3006 | }) | |
3007 | ||
3008 | (define_insn "riscv_prefetchi_<mode>" | |
3009 | [(unspec_volatile:X [(match_operand:X 0 "address_operand" "p") | |
3010 | (match_operand:X 1 "imm5_operand" "i")] | |
3011 | UNSPECV_PREI)] | |
3012 | "TARGET_ZICBOP" | |
3013 | "prefetch.i\t%a0" | |
3014 | ) | |
3015 | ||
3016 | (include "bitmanip.md") | |
3017 | (include "sync.md") | |
3018 | (include "peephole.md") | |
3019 | (include "pic.md") | |
3020 | (include "generic.md") | |
3021 | (include "sifive-7.md") | |
3022 | (include "vector.md") |