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1 | ;; e500 SPE description | |
2 | ;; Copyright (C) 2002-2017 Free Software Foundation, Inc. | |
3 | ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) | |
4 | ||
5 | ;; This file is part of GCC. | |
6 | ||
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | (define_constants | |
22 | [(CMPDFEQ_GPR 1006) | |
23 | (TSTDFEQ_GPR 1007) | |
24 | (CMPDFGT_GPR 1008) | |
25 | (TSTDFGT_GPR 1009) | |
26 | (CMPDFLT_GPR 1010) | |
27 | (TSTDFLT_GPR 1011) | |
28 | (CMPTFEQ_GPR 1012) | |
29 | (TSTTFEQ_GPR 1013) | |
30 | (CMPTFGT_GPR 1014) | |
31 | (TSTTFGT_GPR 1015) | |
32 | (CMPTFLT_GPR 1016) | |
33 | (TSTTFLT_GPR 1017) | |
34 | (E500_CR_IOR_COMPARE 1018) | |
35 | ]) | |
36 | ||
37 | ;; Modes using a 64-bit register. | |
38 | (define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI]) | |
39 | ||
40 | ;; Likewise, but allow TFmode (two registers) as well. | |
41 | (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF]) | |
42 | ||
43 | ;; DImode and TImode. | |
44 | (define_mode_iterator DITI [DI TI]) | |
45 | ||
46 | (define_insn "*negsf2_gpr" | |
47 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
48 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
49 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
50 | "efsneg %0,%1" | |
51 | [(set_attr "type" "fpsimple")]) | |
52 | ||
53 | (define_insn "*abssf2_gpr" | |
54 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
55 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
56 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
57 | "efsabs %0,%1" | |
58 | [(set_attr "type" "fpsimple")]) | |
59 | ||
60 | (define_insn "*nabssf2_gpr" | |
61 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
62 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] | |
63 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
64 | "efsnabs %0,%1" | |
65 | [(set_attr "type" "fpsimple")]) | |
66 | ||
67 | (define_insn "*addsf3_gpr" | |
68 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
69 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
70 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
71 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
72 | "efsadd %0,%1,%2" | |
73 | [(set_attr "type" "fp")]) | |
74 | ||
75 | (define_insn "*subsf3_gpr" | |
76 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
77 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
78 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
79 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
80 | "efssub %0,%1,%2" | |
81 | [(set_attr "type" "fp")]) | |
82 | ||
83 | (define_insn "*mulsf3_gpr" | |
84 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
85 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
86 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
87 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
88 | "efsmul %0,%1,%2" | |
89 | [(set_attr "type" "fp")]) | |
90 | ||
91 | (define_insn "*divsf3_gpr" | |
92 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
93 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
94 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
95 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
96 | "efsdiv %0,%1,%2" | |
97 | [(set_attr "type" "vecfdiv")]) | |
98 | ||
99 | ;; Floating point conversion instructions. | |
100 | ||
101 | (define_insn "spe_fixuns_truncdfsi2" | |
102 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
103 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
104 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
105 | "efdctuiz %0,%1" | |
106 | [(set_attr "type" "fp")]) | |
107 | ||
108 | (define_insn "spe_extendsfdf2" | |
109 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
110 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
111 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
112 | "efdcfs %0,%1" | |
113 | [(set_attr "type" "fp")]) | |
114 | ||
115 | (define_insn "spe_fixuns_truncsfsi2" | |
116 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
117 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
118 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
119 | "efsctuiz %0,%1" | |
120 | [(set_attr "type" "fp")]) | |
121 | ||
122 | (define_insn "spe_fix_truncsfsi2" | |
123 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
124 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
125 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
126 | "efsctsiz %0,%1" | |
127 | [(set_attr "type" "fp")]) | |
128 | ||
129 | (define_insn "spe_fix_truncdfsi2" | |
130 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
131 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
132 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
133 | "efdctsiz %0,%1" | |
134 | [(set_attr "type" "fp")]) | |
135 | ||
136 | (define_insn "spe_floatunssisf2" | |
137 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
138 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
139 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
140 | "efscfui %0,%1" | |
141 | [(set_attr "type" "fp")]) | |
142 | ||
143 | (define_insn "spe_floatunssidf2" | |
144 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
145 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
146 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
147 | "efdcfui %0,%1" | |
148 | [(set_attr "type" "fp")]) | |
149 | ||
150 | (define_insn "spe_floatsisf2" | |
151 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
152 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
153 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
154 | "efscfsi %0,%1" | |
155 | [(set_attr "type" "fp")]) | |
156 | ||
157 | (define_insn "spe_floatsidf2" | |
158 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
159 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
160 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
161 | "efdcfsi %0,%1" | |
162 | [(set_attr "type" "fp")]) | |
163 | ||
164 | ;; SPE SIMD instructions | |
165 | ||
166 | (define_insn "absv2si2" | |
167 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
168 | (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
169 | "TARGET_SPE" | |
170 | "evabs %0,%1" | |
171 | [(set_attr "type" "vecsimple") | |
172 | (set_attr "length" "4")]) | |
173 | ||
174 | (define_insn "spe_evandc" | |
175 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
176 | (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
177 | (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
178 | "TARGET_SPE" | |
179 | "evandc %0,%1,%2" | |
180 | [(set_attr "type" "vecsimple") | |
181 | (set_attr "length" "4")]) | |
182 | ||
183 | (define_insn "andv2si3" | |
184 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
185 | (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
186 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
187 | "TARGET_SPE" | |
188 | "evand %0,%1,%2" | |
189 | [(set_attr "type" "vecsimple") | |
190 | (set_attr "length" "4")]) | |
191 | ||
192 | ;; Vector compare instructions | |
193 | ||
194 | (define_insn "spe_evcmpeq" | |
195 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
196 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
197 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] | |
198 | "TARGET_SPE" | |
199 | "evcmpeq %0,%1,%2" | |
200 | [(set_attr "type" "veccmp") | |
201 | (set_attr "length" "4")]) | |
202 | ||
203 | (define_insn "spe_evcmpgts" | |
204 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
205 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
206 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] | |
207 | "TARGET_SPE" | |
208 | "evcmpgts %0,%1,%2" | |
209 | [(set_attr "type" "veccmp") | |
210 | (set_attr "length" "4")]) | |
211 | ||
212 | (define_insn "spe_evcmpgtu" | |
213 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
214 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
215 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] | |
216 | "TARGET_SPE" | |
217 | "evcmpgtu %0,%1,%2" | |
218 | [(set_attr "type" "veccmp") | |
219 | (set_attr "length" "4")]) | |
220 | ||
221 | (define_insn "spe_evcmplts" | |
222 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
223 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
224 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] | |
225 | "TARGET_SPE" | |
226 | "evcmplts %0,%1,%2" | |
227 | [(set_attr "type" "veccmp") | |
228 | (set_attr "length" "4")]) | |
229 | ||
230 | (define_insn "spe_evcmpltu" | |
231 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
232 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
233 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] | |
234 | "TARGET_SPE" | |
235 | "evcmpltu %0,%1,%2" | |
236 | [(set_attr "type" "veccmp") | |
237 | (set_attr "length" "4")]) | |
238 | ||
239 | ;; Floating point vector compare instructions | |
240 | ||
241 | (define_insn "spe_evfscmpeq" | |
242 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
243 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
244 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) | |
245 | (clobber (reg:SI SPEFSCR_REGNO))] | |
246 | "TARGET_SPE" | |
247 | "evfscmpeq %0,%1,%2" | |
248 | [(set_attr "type" "veccmp") | |
249 | (set_attr "length" "4")]) | |
250 | ||
251 | (define_insn "spe_evfscmpgt" | |
252 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
253 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
254 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) | |
255 | (clobber (reg:SI SPEFSCR_REGNO))] | |
256 | "TARGET_SPE" | |
257 | "evfscmpgt %0,%1,%2" | |
258 | [(set_attr "type" "veccmp") | |
259 | (set_attr "length" "4")]) | |
260 | ||
261 | (define_insn "spe_evfscmplt" | |
262 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
263 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
264 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) | |
265 | (clobber (reg:SI SPEFSCR_REGNO))] | |
266 | "TARGET_SPE" | |
267 | "evfscmplt %0,%1,%2" | |
268 | [(set_attr "type" "veccmp") | |
269 | (set_attr "length" "4")]) | |
270 | ||
271 | (define_insn "spe_evfststeq" | |
272 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
273 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
274 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] | |
275 | "TARGET_SPE" | |
276 | "evfststeq %0,%1,%2" | |
277 | [(set_attr "type" "veccmp") | |
278 | (set_attr "length" "4")]) | |
279 | ||
280 | (define_insn "spe_evfststgt" | |
281 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
282 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
283 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] | |
284 | "TARGET_SPE" | |
285 | "evfststgt %0,%1,%2" | |
286 | [(set_attr "type" "veccmp") | |
287 | (set_attr "length" "4")]) | |
288 | ||
289 | (define_insn "spe_evfststlt" | |
290 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
291 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
292 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] | |
293 | "TARGET_SPE" | |
294 | "evfststlt %0,%1,%2" | |
295 | [(set_attr "type" "veccmp") | |
296 | (set_attr "length" "4")]) | |
297 | ||
298 | ;; End of vector compare instructions | |
299 | ||
300 | (define_insn "spe_evcntlsw" | |
301 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
302 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] | |
303 | "TARGET_SPE" | |
304 | "evcntlsw %0,%1" | |
305 | [(set_attr "type" "vecsimple") | |
306 | (set_attr "length" "4")]) | |
307 | ||
308 | (define_insn "spe_evcntlzw" | |
309 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
310 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] | |
311 | "TARGET_SPE" | |
312 | "evcntlzw %0,%1" | |
313 | [(set_attr "type" "vecsimple") | |
314 | (set_attr "length" "4")]) | |
315 | ||
316 | (define_insn "spe_eveqv" | |
317 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
318 | (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
319 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
320 | "TARGET_SPE" | |
321 | "eveqv %0,%1,%2" | |
322 | [(set_attr "type" "vecsimple") | |
323 | (set_attr "length" "4")]) | |
324 | ||
325 | (define_insn "spe_evextsb" | |
326 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
327 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] | |
328 | "TARGET_SPE" | |
329 | "evextsb %0,%1" | |
330 | [(set_attr "type" "vecsimple") | |
331 | (set_attr "length" "4")]) | |
332 | ||
333 | (define_insn "spe_evextsh" | |
334 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
335 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] | |
336 | "TARGET_SPE" | |
337 | "evextsh %0,%1" | |
338 | [(set_attr "type" "vecsimple") | |
339 | (set_attr "length" "4")]) | |
340 | ||
341 | (define_insn "spe_evlhhesplat" | |
342 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
343 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
344 | (match_operand:QI 2 "immediate_operand" "i")))) | |
345 | (unspec [(const_int 0)] 509)] | |
346 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
347 | "evlhhesplat %0,%2*2(%1)" | |
348 | [(set_attr "type" "vecload") | |
349 | (set_attr "length" "4")]) | |
350 | ||
351 | (define_insn "spe_evlhhesplatx" | |
352 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
353 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
354 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
355 | (unspec [(const_int 0)] 510)] | |
356 | "TARGET_SPE" | |
357 | "evlhhesplatx %0,%1,%2" | |
358 | [(set_attr "type" "vecload") | |
359 | (set_attr "length" "4")]) | |
360 | ||
361 | (define_insn "spe_evlhhossplat" | |
362 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
363 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
364 | (match_operand:QI 2 "immediate_operand" "i")))) | |
365 | (unspec [(const_int 0)] 511)] | |
366 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
367 | "evlhhossplat %0,%2*2(%1)" | |
368 | [(set_attr "type" "vecload") | |
369 | (set_attr "length" "4")]) | |
370 | ||
371 | (define_insn "spe_evlhhossplatx" | |
372 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
373 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
374 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
375 | (unspec [(const_int 0)] 512)] | |
376 | "TARGET_SPE" | |
377 | "evlhhossplatx %0,%1,%2" | |
378 | [(set_attr "type" "vecload") | |
379 | (set_attr "length" "4")]) | |
380 | ||
381 | (define_insn "spe_evlhhousplat" | |
382 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
383 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
384 | (match_operand:QI 2 "immediate_operand" "i")))) | |
385 | (unspec [(const_int 0)] 513)] | |
386 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
387 | "evlhhousplat %0,%2*2(%1)" | |
388 | [(set_attr "type" "vecload") | |
389 | (set_attr "length" "4")]) | |
390 | ||
391 | (define_insn "spe_evlhhousplatx" | |
392 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
393 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
394 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
395 | (unspec [(const_int 0)] 514)] | |
396 | "TARGET_SPE" | |
397 | "evlhhousplatx %0,%1,%2" | |
398 | [(set_attr "type" "vecload") | |
399 | (set_attr "length" "4")]) | |
400 | ||
401 | (define_insn "spe_evlwhsplat" | |
402 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
403 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
404 | (match_operand:QI 2 "immediate_operand" "i")))) | |
405 | (unspec [(const_int 0)] 515)] | |
406 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
407 | "evlwhsplat %0,%2*4(%1)" | |
408 | [(set_attr "type" "vecload") | |
409 | (set_attr "length" "4")]) | |
410 | ||
411 | (define_insn "spe_evlwhsplatx" | |
412 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
413 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
414 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
415 | (unspec [(const_int 0)] 516)] | |
416 | "TARGET_SPE" | |
417 | "evlwhsplatx %0,%1,%2" | |
418 | [(set_attr "type" "vecload") | |
419 | (set_attr "length" "4")]) | |
420 | ||
421 | (define_insn "spe_evlwwsplat" | |
422 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
423 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
424 | (match_operand:QI 2 "immediate_operand" "i")))) | |
425 | (unspec [(const_int 0)] 517)] | |
426 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
427 | "evlwwsplat %0,%2*4(%1)" | |
428 | [(set_attr "type" "vecload") | |
429 | (set_attr "length" "4")]) | |
430 | ||
431 | (define_insn "spe_evlwwsplatx" | |
432 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
433 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
434 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
435 | (unspec [(const_int 0)] 518)] | |
436 | "TARGET_SPE" | |
437 | "evlwwsplatx %0,%1,%2" | |
438 | [(set_attr "type" "vecload") | |
439 | (set_attr "length" "4")]) | |
440 | ||
441 | ;; Integer vector permutation instructions. The pairs of digits in the | |
442 | ;; names of these instructions indicate the indices, in the memory vector | |
443 | ;; element ordering, of the vector elements permuted to the output vector | |
444 | ;; from the first and the second input vector respectively. | |
445 | ||
446 | (define_insn "vec_perm00_v2si" | |
447 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
448 | (vec_select:V2SI | |
449 | (vec_concat:V4SI | |
450 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
451 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
452 | (parallel [(const_int 0) (const_int 2)])))] | |
453 | "TARGET_SPE" | |
454 | { | |
455 | if (WORDS_BIG_ENDIAN) | |
456 | return "evmergehi %0,%1,%2"; | |
457 | else | |
458 | return "evmergelo %0,%2,%1"; | |
459 | } | |
460 | [(set_attr "type" "vecsimple") | |
461 | (set_attr "length" "4")]) | |
462 | ||
463 | (define_insn "vec_perm01_v2si" | |
464 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
465 | (vec_select:V2SI | |
466 | (vec_concat:V4SI | |
467 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
468 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
469 | (parallel [(const_int 0) (const_int 3)])))] | |
470 | "TARGET_SPE" | |
471 | { | |
472 | if (WORDS_BIG_ENDIAN) | |
473 | return "evmergehilo %0,%1,%2"; | |
474 | else | |
475 | return "evmergehilo %0,%2,%1"; | |
476 | } | |
477 | [(set_attr "type" "vecsimple") | |
478 | (set_attr "length" "4")]) | |
479 | ||
480 | (define_insn "vec_perm11_v2si" | |
481 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
482 | (vec_select:V2SI | |
483 | (vec_concat:V4SI | |
484 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
485 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
486 | (parallel [(const_int 1) (const_int 3)])))] | |
487 | "TARGET_SPE" | |
488 | { | |
489 | if (WORDS_BIG_ENDIAN) | |
490 | return "evmergelo %0,%1,%2"; | |
491 | else | |
492 | return "evmergehi %0,%2,%1"; | |
493 | } | |
494 | [(set_attr "type" "vecsimple") | |
495 | (set_attr "length" "4")]) | |
496 | ||
497 | (define_insn "vec_perm10_v2si" | |
498 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
499 | (vec_select:V2SI | |
500 | (vec_concat:V4SI | |
501 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
502 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
503 | (parallel [(const_int 1) (const_int 2)])))] | |
504 | "TARGET_SPE" | |
505 | { | |
506 | if (WORDS_BIG_ENDIAN) | |
507 | return "evmergelohi %0,%1,%2"; | |
508 | else | |
509 | return "evmergelohi %0,%2,%1"; | |
510 | } | |
511 | [(set_attr "type" "vecsimple") | |
512 | (set_attr "length" "4")]) | |
513 | ||
514 | (define_expand "vec_perm_constv2si" | |
515 | [(match_operand:V2SI 0 "gpc_reg_operand" "") | |
516 | (match_operand:V2SI 1 "gpc_reg_operand" "") | |
517 | (match_operand:V2SI 2 "gpc_reg_operand" "") | |
518 | (match_operand:V2SI 3 "" "")] | |
519 | "TARGET_SPE" | |
520 | { | |
521 | if (rs6000_expand_vec_perm_const (operands)) | |
522 | DONE; | |
523 | else | |
524 | FAIL; | |
525 | }) | |
526 | ||
527 | (define_expand "spe_evmergehi" | |
528 | [(match_operand:V2SI 0 "register_operand" "") | |
529 | (match_operand:V2SI 1 "register_operand" "") | |
530 | (match_operand:V2SI 2 "register_operand" "")] | |
531 | "TARGET_SPE" | |
532 | { | |
533 | if (BYTES_BIG_ENDIAN) | |
534 | emit_insn (gen_vec_perm00_v2si (operands[0], operands[1], operands[2])); | |
535 | else | |
536 | emit_insn (gen_vec_perm11_v2si (operands[0], operands[2], operands[1])); | |
537 | DONE; | |
538 | }) | |
539 | ||
540 | (define_expand "spe_evmergehilo" | |
541 | [(match_operand:V2SI 0 "register_operand" "") | |
542 | (match_operand:V2SI 1 "register_operand" "") | |
543 | (match_operand:V2SI 2 "register_operand" "")] | |
544 | "TARGET_SPE" | |
545 | { | |
546 | if (BYTES_BIG_ENDIAN) | |
547 | emit_insn (gen_vec_perm01_v2si (operands[0], operands[1], operands[2])); | |
548 | else | |
549 | emit_insn (gen_vec_perm01_v2si (operands[0], operands[2], operands[1])); | |
550 | DONE; | |
551 | }) | |
552 | ||
553 | (define_expand "spe_evmergelo" | |
554 | [(match_operand:V2SI 0 "register_operand" "") | |
555 | (match_operand:V2SI 1 "register_operand" "") | |
556 | (match_operand:V2SI 2 "register_operand" "")] | |
557 | "TARGET_SPE" | |
558 | { | |
559 | if (BYTES_BIG_ENDIAN) | |
560 | emit_insn (gen_vec_perm11_v2si (operands[0], operands[1], operands[2])); | |
561 | else | |
562 | emit_insn (gen_vec_perm00_v2si (operands[0], operands[2], operands[1])); | |
563 | DONE; | |
564 | }) | |
565 | ||
566 | (define_expand "spe_evmergelohi" | |
567 | [(match_operand:V2SI 0 "register_operand" "") | |
568 | (match_operand:V2SI 1 "register_operand" "") | |
569 | (match_operand:V2SI 2 "register_operand" "")] | |
570 | "TARGET_SPE" | |
571 | { | |
572 | if (BYTES_BIG_ENDIAN) | |
573 | emit_insn (gen_vec_perm10_v2si (operands[0], operands[1], operands[2])); | |
574 | else | |
575 | emit_insn (gen_vec_perm10_v2si (operands[0], operands[2], operands[1])); | |
576 | DONE; | |
577 | }) | |
578 | ||
579 | ;; End of integer vector permutation instructions. | |
580 | ||
581 | (define_insn "spe_evnand" | |
582 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
583 | (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
584 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
585 | "TARGET_SPE" | |
586 | "evnand %0,%1,%2" | |
587 | [(set_attr "type" "vecsimple") | |
588 | (set_attr "length" "4")]) | |
589 | ||
590 | (define_insn "negv2si2" | |
591 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
592 | (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
593 | "TARGET_SPE" | |
594 | "evneg %0,%1" | |
595 | [(set_attr "type" "vecsimple") | |
596 | (set_attr "length" "4")]) | |
597 | ||
598 | (define_insn "spe_evnor" | |
599 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
600 | (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
601 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
602 | "TARGET_SPE" | |
603 | "evnor %0,%1,%2" | |
604 | [(set_attr "type" "vecsimple") | |
605 | (set_attr "length" "4")]) | |
606 | ||
607 | (define_insn "spe_evorc" | |
608 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
609 | (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
610 | (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
611 | "TARGET_SPE" | |
612 | "evorc %0,%1,%2" | |
613 | [(set_attr "type" "vecsimple") | |
614 | (set_attr "length" "4")]) | |
615 | ||
616 | (define_insn "spe_evor" | |
617 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
618 | (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
619 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
620 | "TARGET_SPE" | |
621 | "evor %0,%1,%2" | |
622 | [(set_attr "type" "vecsimple") | |
623 | (set_attr "length" "4")]) | |
624 | ||
625 | (define_insn "spe_evrlwi" | |
626 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
627 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
628 | (match_operand:QI 2 "immediate_operand" "i")] 519))] | |
629 | "TARGET_SPE" | |
630 | "evrlwi %0,%1,%2" | |
631 | [(set_attr "type" "vecsimple") | |
632 | (set_attr "length" "4")]) | |
633 | ||
634 | (define_insn "spe_evrlw" | |
635 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
636 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
637 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] | |
638 | "TARGET_SPE" | |
639 | "evrlw %0,%1,%2" | |
640 | [(set_attr "type" "veccomplex") | |
641 | (set_attr "length" "4")]) | |
642 | ||
643 | (define_insn "spe_evrndw" | |
644 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
645 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] | |
646 | "TARGET_SPE" | |
647 | "evrndw %0,%1" | |
648 | [(set_attr "type" "vecsimple") | |
649 | (set_attr "length" "4")]) | |
650 | ||
651 | (define_insn "spe_evsel" | |
652 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
653 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
654 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
655 | (match_operand:CC 3 "cc_reg_operand" "y")] 522))] | |
656 | "TARGET_SPE" | |
657 | "evsel %0,%1,%2,%3" | |
658 | [(set_attr "type" "veccmp") | |
659 | (set_attr "length" "4")]) | |
660 | ||
661 | (define_insn "spe_evsel_fs" | |
662 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
663 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
664 | (match_operand:V2SF 2 "gpc_reg_operand" "r") | |
665 | (match_operand:CC 3 "cc_reg_operand" "y")] 725))] | |
666 | "TARGET_SPE" | |
667 | "evsel %0,%1,%2,%3" | |
668 | [(set_attr "type" "veccmp") | |
669 | (set_attr "length" "4")]) | |
670 | ||
671 | (define_insn "spe_evslwi" | |
672 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
673 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
674 | (match_operand:QI 2 "immediate_operand" "i")] | |
675 | 523))] | |
676 | "TARGET_SPE" | |
677 | "evslwi %0,%1,%2" | |
678 | [(set_attr "type" "vecsimple") | |
679 | (set_attr "length" "4")]) | |
680 | ||
681 | (define_insn "spe_evslw" | |
682 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
683 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
684 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] | |
685 | "TARGET_SPE" | |
686 | "evslw %0,%1,%2" | |
687 | [(set_attr "type" "vecsimple") | |
688 | (set_attr "length" "4")]) | |
689 | ||
690 | (define_insn "spe_evsrwis" | |
691 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
692 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
693 | (match_operand:QI 2 "immediate_operand" "i")] | |
694 | 525))] | |
695 | "TARGET_SPE" | |
696 | "evsrwis %0,%1,%2" | |
697 | [(set_attr "type" "vecsimple") | |
698 | (set_attr "length" "4")]) | |
699 | ||
700 | (define_insn "spe_evsrwiu" | |
701 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
702 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
703 | (match_operand:QI 2 "immediate_operand" "i")] | |
704 | 526))] | |
705 | "TARGET_SPE" | |
706 | "evsrwiu %0,%1,%2" | |
707 | [(set_attr "type" "vecsimple") | |
708 | (set_attr "length" "4")]) | |
709 | ||
710 | (define_insn "spe_evsrws" | |
711 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
712 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
713 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] | |
714 | "TARGET_SPE" | |
715 | "evsrws %0,%1,%2" | |
716 | [(set_attr "type" "vecsimple") | |
717 | (set_attr "length" "4")]) | |
718 | ||
719 | (define_insn "spe_evsrwu" | |
720 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
721 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
722 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] | |
723 | "TARGET_SPE" | |
724 | "evsrwu %0,%1,%2" | |
725 | [(set_attr "type" "vecsimple") | |
726 | (set_attr "length" "4")]) | |
727 | ||
728 | ;; vector xors | |
729 | ||
730 | (define_insn "xorv2si3" | |
731 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
732 | (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
733 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
734 | "TARGET_SPE" | |
735 | "evxor %0,%1,%2" | |
736 | [(set_attr "type" "vecsimple") | |
737 | (set_attr "length" "4")]) | |
738 | ||
739 | (define_insn "xorv4hi3" | |
740 | [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") | |
741 | (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r") | |
742 | (match_operand:V4HI 2 "gpc_reg_operand" "r")))] | |
743 | "TARGET_SPE" | |
744 | "evxor %0,%1,%2" | |
745 | [(set_attr "type" "vecsimple") | |
746 | (set_attr "length" "4")]) | |
747 | ||
748 | (define_insn "xorv1di3" | |
749 | [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") | |
750 | (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r") | |
751 | (match_operand:V1DI 2 "gpc_reg_operand" "r")))] | |
752 | "TARGET_SPE" | |
753 | "evxor %0,%1,%2" | |
754 | [(set_attr "type" "vecsimple") | |
755 | (set_attr "length" "4")]) | |
756 | ||
757 | ;; end of vector xors | |
758 | ||
759 | (define_insn "spe_evfsabs" | |
760 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
761 | (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
762 | "TARGET_SPE" | |
763 | "evfsabs %0,%1" | |
764 | [(set_attr "type" "vecsimple") | |
765 | (set_attr "length" "4")]) | |
766 | ||
767 | (define_insn "spe_evfsadd" | |
768 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
769 | (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
770 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
771 | (clobber (reg:SI SPEFSCR_REGNO))] | |
772 | "TARGET_SPE" | |
773 | "evfsadd %0,%1,%2" | |
774 | [(set_attr "type" "vecfloat") | |
775 | (set_attr "length" "4")]) | |
776 | ||
777 | (define_insn "spe_evfscfsf" | |
778 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
779 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] | |
780 | "TARGET_SPE" | |
781 | "evfscfsf %0,%1" | |
782 | [(set_attr "type" "vecfloat") | |
783 | (set_attr "length" "4")]) | |
784 | ||
785 | (define_insn "spe_evfscfsi" | |
786 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
787 | (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
788 | "TARGET_SPE" | |
789 | "evfscfsi %0,%1" | |
790 | [(set_attr "type" "vecfloat") | |
791 | (set_attr "length" "4")]) | |
792 | ||
793 | (define_insn "spe_evfscfuf" | |
794 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
795 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] | |
796 | "TARGET_SPE" | |
797 | "evfscfuf %0,%1" | |
798 | [(set_attr "type" "vecfloat") | |
799 | (set_attr "length" "4")]) | |
800 | ||
801 | (define_insn "spe_evfscfui" | |
802 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
803 | (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] | |
804 | "TARGET_SPE" | |
805 | "evfscfui %0,%1" | |
806 | [(set_attr "type" "vecfloat") | |
807 | (set_attr "length" "4")]) | |
808 | ||
809 | (define_insn "spe_evfsctsf" | |
810 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
811 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] | |
812 | "TARGET_SPE" | |
813 | "evfsctsf %0,%1" | |
814 | [(set_attr "type" "vecfloat") | |
815 | (set_attr "length" "4")]) | |
816 | ||
817 | (define_insn "spe_evfsctsi" | |
818 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
819 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] | |
820 | "TARGET_SPE" | |
821 | "evfsctsi %0,%1" | |
822 | [(set_attr "type" "vecfloat") | |
823 | (set_attr "length" "4")]) | |
824 | ||
825 | (define_insn "spe_evfsctsiz" | |
826 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
827 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] | |
828 | "TARGET_SPE" | |
829 | "evfsctsiz %0,%1" | |
830 | [(set_attr "type" "vecfloat") | |
831 | (set_attr "length" "4")]) | |
832 | ||
833 | (define_insn "spe_evfsctuf" | |
834 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
835 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] | |
836 | "TARGET_SPE" | |
837 | "evfsctuf %0,%1" | |
838 | [(set_attr "type" "vecfloat") | |
839 | (set_attr "length" "4")]) | |
840 | ||
841 | (define_insn "spe_evfsctui" | |
842 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
843 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] | |
844 | "TARGET_SPE" | |
845 | "evfsctui %0,%1" | |
846 | [(set_attr "type" "vecfloat") | |
847 | (set_attr "length" "4")]) | |
848 | ||
849 | (define_insn "spe_evfsctuiz" | |
850 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
851 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] | |
852 | "TARGET_SPE" | |
853 | "evfsctuiz %0,%1" | |
854 | [(set_attr "type" "vecfloat") | |
855 | (set_attr "length" "4")]) | |
856 | ||
857 | (define_insn "spe_evfsdiv" | |
858 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
859 | (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
860 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
861 | (clobber (reg:SI SPEFSCR_REGNO))] | |
862 | "TARGET_SPE" | |
863 | "evfsdiv %0,%1,%2" | |
864 | [(set_attr "type" "vecfdiv") | |
865 | (set_attr "length" "4")]) | |
866 | ||
867 | (define_insn "spe_evfsmul" | |
868 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
869 | (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
870 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
871 | (clobber (reg:SI SPEFSCR_REGNO))] | |
872 | "TARGET_SPE" | |
873 | "evfsmul %0,%1,%2" | |
874 | [(set_attr "type" "vecfloat") | |
875 | (set_attr "length" "4")]) | |
876 | ||
877 | (define_insn "spe_evfsnabs" | |
878 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
879 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] | |
880 | "TARGET_SPE" | |
881 | "evfsnabs %0,%1" | |
882 | [(set_attr "type" "vecsimple") | |
883 | (set_attr "length" "4")]) | |
884 | ||
885 | (define_insn "spe_evfsneg" | |
886 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
887 | (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
888 | "TARGET_SPE" | |
889 | "evfsneg %0,%1" | |
890 | [(set_attr "type" "vecsimple") | |
891 | (set_attr "length" "4")]) | |
892 | ||
893 | (define_insn "spe_evfssub" | |
894 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
895 | (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
896 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
897 | (clobber (reg:SI SPEFSCR_REGNO))] | |
898 | "TARGET_SPE" | |
899 | "evfssub %0,%1,%2" | |
900 | [(set_attr "type" "vecfloat") | |
901 | (set_attr "length" "4")]) | |
902 | ||
903 | ;; SPE SIMD load instructions. | |
904 | ||
905 | ;; Only the hardware engineer who designed the SPE understands the | |
906 | ;; plethora of load and store instructions ;-). We have no way of | |
907 | ;; differentiating between them with RTL so use an unspec of const_int 0 | |
908 | ;; to avoid identical RTL. | |
909 | ||
910 | (define_insn "spe_evldd" | |
911 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
912 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
913 | (match_operand:QI 2 "immediate_operand" "i")))) | |
914 | (unspec [(const_int 0)] 544)] | |
915 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
916 | "evldd %0,%2*8(%1)" | |
917 | [(set_attr "type" "vecload") | |
918 | (set_attr "length" "4")]) | |
919 | ||
920 | (define_insn "spe_evlddx" | |
921 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
922 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
923 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
924 | (unspec [(const_int 0)] 545)] | |
925 | "TARGET_SPE" | |
926 | "evlddx %0,%1,%2" | |
927 | [(set_attr "type" "vecload") | |
928 | (set_attr "length" "4")]) | |
929 | ||
930 | (define_insn "spe_evldh" | |
931 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
932 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
933 | (match_operand:QI 2 "immediate_operand" "i")))) | |
934 | (unspec [(const_int 0)] 546)] | |
935 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
936 | "evldh %0,%2*8(%1)" | |
937 | [(set_attr "type" "vecload") | |
938 | (set_attr "length" "4")]) | |
939 | ||
940 | (define_insn "spe_evldhx" | |
941 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
942 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
943 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
944 | (unspec [(const_int 0)] 547)] | |
945 | "TARGET_SPE" | |
946 | "evldhx %0,%1,%2" | |
947 | [(set_attr "type" "vecload") | |
948 | (set_attr "length" "4")]) | |
949 | ||
950 | (define_insn "spe_evldw" | |
951 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
952 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
953 | (match_operand:QI 2 "immediate_operand" "i")))) | |
954 | (unspec [(const_int 0)] 548)] | |
955 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
956 | "evldw %0,%2*8(%1)" | |
957 | [(set_attr "type" "vecload") | |
958 | (set_attr "length" "4")]) | |
959 | ||
960 | (define_insn "spe_evldwx" | |
961 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
962 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
963 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
964 | (unspec [(const_int 0)] 549)] | |
965 | "TARGET_SPE" | |
966 | "evldwx %0,%1,%2" | |
967 | [(set_attr "type" "vecload") | |
968 | (set_attr "length" "4")]) | |
969 | ||
970 | (define_insn "spe_evlwhe" | |
971 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
972 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
973 | (match_operand:QI 2 "immediate_operand" "i")))) | |
974 | (unspec [(const_int 0)] 550)] | |
975 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
976 | "evlwhe %0,%2*4(%1)" | |
977 | [(set_attr "type" "vecload") | |
978 | (set_attr "length" "4")]) | |
979 | ||
980 | (define_insn "spe_evlwhex" | |
981 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
982 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
983 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
984 | (unspec [(const_int 0)] 551)] | |
985 | "TARGET_SPE" | |
986 | "evlwhex %0,%1,%2" | |
987 | [(set_attr "type" "vecload") | |
988 | (set_attr "length" "4")]) | |
989 | ||
990 | (define_insn "spe_evlwhos" | |
991 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
992 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
993 | (match_operand:QI 2 "immediate_operand" "i")))) | |
994 | (unspec [(const_int 0)] 552)] | |
995 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
996 | "evlwhos %0,%2*4(%1)" | |
997 | [(set_attr "type" "vecload") | |
998 | (set_attr "length" "4")]) | |
999 | ||
1000 | (define_insn "spe_evlwhosx" | |
1001 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1002 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1003 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
1004 | (unspec [(const_int 0)] 553)] | |
1005 | "TARGET_SPE" | |
1006 | "evlwhosx %0,%1,%2" | |
1007 | [(set_attr "type" "vecload") | |
1008 | (set_attr "length" "4")]) | |
1009 | ||
1010 | (define_insn "spe_evlwhou" | |
1011 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1012 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1013 | (match_operand:QI 2 "immediate_operand" "i")))) | |
1014 | (unspec [(const_int 0)] 554)] | |
1015 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
1016 | "evlwhou %0,%2*4(%1)" | |
1017 | [(set_attr "type" "vecload") | |
1018 | (set_attr "length" "4")]) | |
1019 | ||
1020 | (define_insn "spe_evlwhoux" | |
1021 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1022 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1023 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
1024 | (unspec [(const_int 0)] 555)] | |
1025 | "TARGET_SPE" | |
1026 | "evlwhoux %0,%1,%2" | |
1027 | [(set_attr "type" "vecload") | |
1028 | (set_attr "length" "4")]) | |
1029 | ||
1030 | (define_insn "spe_brinc" | |
1031 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1032 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") | |
1033 | (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] | |
1034 | "TARGET_SPE" | |
1035 | "brinc %0,%1,%2" | |
1036 | [(set_attr "type" "brinc") | |
1037 | (set_attr "length" "4")]) | |
1038 | ||
1039 | (define_insn "spe_evmhegsmfaa" | |
1040 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1041 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1042 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1043 | (reg:V2SI SPE_ACC_REGNO)] 557)) | |
1044 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1045 | "TARGET_SPE" | |
1046 | "evmhegsmfaa %0,%1,%2" | |
1047 | [(set_attr "type" "veccomplex") | |
1048 | (set_attr "length" "4")]) | |
1049 | ||
1050 | (define_insn "spe_evmhegsmfan" | |
1051 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1052 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1053 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1054 | (reg:V2SI SPE_ACC_REGNO)] 558)) | |
1055 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1056 | "TARGET_SPE" | |
1057 | "evmhegsmfan %0,%1,%2" | |
1058 | [(set_attr "type" "veccomplex") | |
1059 | (set_attr "length" "4")]) | |
1060 | ||
1061 | (define_insn "spe_evmhegsmiaa" | |
1062 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1063 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1064 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1065 | (reg:V2SI SPE_ACC_REGNO)] 559)) | |
1066 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1067 | "TARGET_SPE" | |
1068 | "evmhegsmiaa %0,%1,%2" | |
1069 | [(set_attr "type" "veccomplex") | |
1070 | (set_attr "length" "4")]) | |
1071 | ||
1072 | (define_insn "spe_evmhegsmian" | |
1073 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1074 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1075 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1076 | (reg:V2SI SPE_ACC_REGNO)] 560)) | |
1077 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1078 | "TARGET_SPE" | |
1079 | "evmhegsmian %0,%1,%2" | |
1080 | [(set_attr "type" "veccomplex") | |
1081 | (set_attr "length" "4")]) | |
1082 | ||
1083 | (define_insn "spe_evmhegumiaa" | |
1084 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1085 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1086 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1087 | (reg:V2SI SPE_ACC_REGNO)] 561)) | |
1088 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1089 | "TARGET_SPE" | |
1090 | "evmhegumiaa %0,%1,%2" | |
1091 | [(set_attr "type" "veccomplex") | |
1092 | (set_attr "length" "4")]) | |
1093 | ||
1094 | (define_insn "spe_evmhegumian" | |
1095 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1096 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1097 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1098 | (reg:V2SI SPE_ACC_REGNO)] 562)) | |
1099 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1100 | "TARGET_SPE" | |
1101 | "evmhegumian %0,%1,%2" | |
1102 | [(set_attr "type" "veccomplex") | |
1103 | (set_attr "length" "4")]) | |
1104 | ||
1105 | (define_insn "spe_evmhesmfaaw" | |
1106 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1107 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1108 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1109 | (reg:V2SI SPE_ACC_REGNO)] 563)) | |
1110 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1111 | "TARGET_SPE" | |
1112 | "evmhesmfaaw %0,%1,%2" | |
1113 | [(set_attr "type" "veccomplex") | |
1114 | (set_attr "length" "4")]) | |
1115 | ||
1116 | (define_insn "spe_evmhesmfanw" | |
1117 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1118 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1119 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1120 | (reg:V2SI SPE_ACC_REGNO)] 564)) | |
1121 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1122 | "TARGET_SPE" | |
1123 | "evmhesmfanw %0,%1,%2" | |
1124 | [(set_attr "type" "veccomplex") | |
1125 | (set_attr "length" "4")]) | |
1126 | ||
1127 | (define_insn "spe_evmhesmfa" | |
1128 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1129 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1130 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) | |
1131 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1132 | "TARGET_SPE" | |
1133 | "evmhesmfa %0,%1,%2" | |
1134 | [(set_attr "type" "veccomplex") | |
1135 | (set_attr "length" "4")]) | |
1136 | ||
1137 | (define_insn "spe_evmhesmf" | |
1138 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1139 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1140 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] | |
1141 | "TARGET_SPE" | |
1142 | "evmhesmf %0,%1,%2" | |
1143 | [(set_attr "type" "veccomplex") | |
1144 | (set_attr "length" "4")]) | |
1145 | ||
1146 | (define_insn "spe_evmhesmiaaw" | |
1147 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1148 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1149 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1150 | (reg:V2SI SPE_ACC_REGNO)] 567)) | |
1151 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1152 | "TARGET_SPE" | |
1153 | "evmhesmiaaw %0,%1,%2" | |
1154 | [(set_attr "type" "veccomplex") | |
1155 | (set_attr "length" "4")]) | |
1156 | ||
1157 | (define_insn "spe_evmhesmianw" | |
1158 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1159 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1160 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1161 | (reg:V2SI SPE_ACC_REGNO)] 568)) | |
1162 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1163 | "TARGET_SPE" | |
1164 | "evmhesmianw %0,%1,%2" | |
1165 | [(set_attr "type" "veccomplex") | |
1166 | (set_attr "length" "4")]) | |
1167 | ||
1168 | (define_insn "spe_evmhesmia" | |
1169 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1170 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1171 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) | |
1172 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1173 | "TARGET_SPE" | |
1174 | "evmhesmia %0,%1,%2" | |
1175 | [(set_attr "type" "veccomplex") | |
1176 | (set_attr "length" "4")]) | |
1177 | ||
1178 | (define_insn "spe_evmhesmi" | |
1179 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1180 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1181 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] | |
1182 | "TARGET_SPE" | |
1183 | "evmhesmi %0,%1,%2" | |
1184 | [(set_attr "type" "veccomplex") | |
1185 | (set_attr "length" "4")]) | |
1186 | ||
1187 | (define_insn "spe_evmhessfaaw" | |
1188 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1189 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1190 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1191 | (reg:V2SI SPE_ACC_REGNO)] 571)) | |
1192 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1193 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1194 | "TARGET_SPE" | |
1195 | "evmhessfaaw %0,%1,%2" | |
1196 | [(set_attr "type" "veccomplex") | |
1197 | (set_attr "length" "4")]) | |
1198 | ||
1199 | (define_insn "spe_evmhessfanw" | |
1200 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1201 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1202 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1203 | (reg:V2SI SPE_ACC_REGNO)] 572)) | |
1204 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1205 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1206 | "TARGET_SPE" | |
1207 | "evmhessfanw %0,%1,%2" | |
1208 | [(set_attr "type" "veccomplex") | |
1209 | (set_attr "length" "4")]) | |
1210 | ||
1211 | (define_insn "spe_evmhessfa" | |
1212 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1213 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1214 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) | |
1215 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1216 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1217 | "TARGET_SPE" | |
1218 | "evmhessfa %0,%1,%2" | |
1219 | [(set_attr "type" "veccomplex") | |
1220 | (set_attr "length" "4")]) | |
1221 | ||
1222 | (define_insn "spe_evmhessf" | |
1223 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1224 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1225 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) | |
1226 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1227 | "TARGET_SPE" | |
1228 | "evmhessf %0,%1,%2" | |
1229 | [(set_attr "type" "veccomplex") | |
1230 | (set_attr "length" "4")]) | |
1231 | ||
1232 | (define_insn "spe_evmhessiaaw" | |
1233 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1234 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1235 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1236 | (reg:V2SI SPE_ACC_REGNO)] 575)) | |
1237 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1238 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1239 | "TARGET_SPE" | |
1240 | "evmhessiaaw %0,%1,%2" | |
1241 | [(set_attr "type" "veccomplex") | |
1242 | (set_attr "length" "4")]) | |
1243 | ||
1244 | (define_insn "spe_evmhessianw" | |
1245 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1246 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1247 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1248 | (reg:V2SI SPE_ACC_REGNO)] 576)) | |
1249 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1250 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1251 | "TARGET_SPE" | |
1252 | "evmhessianw %0,%1,%2" | |
1253 | [(set_attr "type" "veccomplex") | |
1254 | (set_attr "length" "4")]) | |
1255 | ||
1256 | (define_insn "spe_evmheumiaaw" | |
1257 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1258 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1259 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1260 | (reg:V2SI SPE_ACC_REGNO)] 577)) | |
1261 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1262 | "TARGET_SPE" | |
1263 | "evmheumiaaw %0,%1,%2" | |
1264 | [(set_attr "type" "veccomplex") | |
1265 | (set_attr "length" "4")]) | |
1266 | ||
1267 | (define_insn "spe_evmheumianw" | |
1268 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1269 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1270 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1271 | (reg:V2SI SPE_ACC_REGNO)] 578)) | |
1272 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1273 | "TARGET_SPE" | |
1274 | "evmheumianw %0,%1,%2" | |
1275 | [(set_attr "type" "veccomplex") | |
1276 | (set_attr "length" "4")]) | |
1277 | ||
1278 | (define_insn "spe_evmheumia" | |
1279 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1280 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1281 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) | |
1282 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1283 | "TARGET_SPE" | |
1284 | "evmheumia %0,%1,%2" | |
1285 | [(set_attr "type" "veccomplex") | |
1286 | (set_attr "length" "4")]) | |
1287 | ||
1288 | (define_insn "spe_evmheumi" | |
1289 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1290 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1291 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] | |
1292 | "TARGET_SPE" | |
1293 | "evmheumi %0,%1,%2" | |
1294 | [(set_attr "type" "veccomplex") | |
1295 | (set_attr "length" "4")]) | |
1296 | ||
1297 | (define_insn "spe_evmheusiaaw" | |
1298 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1299 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1300 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1301 | (reg:V2SI SPE_ACC_REGNO)] 581)) | |
1302 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1303 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1304 | "TARGET_SPE" | |
1305 | "evmheusiaaw %0,%1,%2" | |
1306 | [(set_attr "type" "veccomplex") | |
1307 | (set_attr "length" "4")]) | |
1308 | ||
1309 | (define_insn "spe_evmheusianw" | |
1310 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1311 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1312 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1313 | (reg:V2SI SPE_ACC_REGNO)] 582)) | |
1314 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1315 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1316 | "TARGET_SPE" | |
1317 | "evmheusianw %0,%1,%2" | |
1318 | [(set_attr "type" "veccomplex") | |
1319 | (set_attr "length" "4")]) | |
1320 | ||
1321 | (define_insn "spe_evmhogsmfaa" | |
1322 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1323 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1324 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1325 | (reg:V2SI SPE_ACC_REGNO)] 583)) | |
1326 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1327 | "TARGET_SPE" | |
1328 | "evmhogsmfaa %0,%1,%2" | |
1329 | [(set_attr "type" "veccomplex") | |
1330 | (set_attr "length" "4")]) | |
1331 | ||
1332 | (define_insn "spe_evmhogsmfan" | |
1333 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1334 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1335 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1336 | (reg:V2SI SPE_ACC_REGNO)] 584)) | |
1337 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1338 | "TARGET_SPE" | |
1339 | "evmhogsmfan %0,%1,%2" | |
1340 | [(set_attr "type" "veccomplex") | |
1341 | (set_attr "length" "4")]) | |
1342 | ||
1343 | (define_insn "spe_evmhogsmiaa" | |
1344 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1345 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1346 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1347 | (reg:V2SI SPE_ACC_REGNO)] 585)) | |
1348 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1349 | "TARGET_SPE" | |
1350 | "evmhogsmiaa %0,%1,%2" | |
1351 | [(set_attr "type" "veccomplex") | |
1352 | (set_attr "length" "4")]) | |
1353 | ||
1354 | (define_insn "spe_evmhogsmian" | |
1355 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1356 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1357 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1358 | (reg:V2SI SPE_ACC_REGNO)] 586)) | |
1359 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1360 | "TARGET_SPE" | |
1361 | "evmhogsmian %0,%1,%2" | |
1362 | [(set_attr "type" "veccomplex") | |
1363 | (set_attr "length" "4")]) | |
1364 | ||
1365 | (define_insn "spe_evmhogumiaa" | |
1366 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1367 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1368 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1369 | (reg:V2SI SPE_ACC_REGNO)] 587)) | |
1370 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1371 | "TARGET_SPE" | |
1372 | "evmhogumiaa %0,%1,%2" | |
1373 | [(set_attr "type" "veccomplex") | |
1374 | (set_attr "length" "4")]) | |
1375 | ||
1376 | (define_insn "spe_evmhogumian" | |
1377 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1378 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1379 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1380 | (reg:V2SI SPE_ACC_REGNO)] 588)) | |
1381 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1382 | "TARGET_SPE" | |
1383 | "evmhogumian %0,%1,%2" | |
1384 | [(set_attr "type" "veccomplex") | |
1385 | (set_attr "length" "4")]) | |
1386 | ||
1387 | (define_insn "spe_evmhosmfaaw" | |
1388 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1389 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1390 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1391 | (reg:V2SI SPE_ACC_REGNO)] 589)) | |
1392 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1393 | "TARGET_SPE" | |
1394 | "evmhosmfaaw %0,%1,%2" | |
1395 | [(set_attr "type" "veccomplex") | |
1396 | (set_attr "length" "4")]) | |
1397 | ||
1398 | (define_insn "spe_evmhosmfanw" | |
1399 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1400 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1401 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1402 | (reg:V2SI SPE_ACC_REGNO)] 590)) | |
1403 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1404 | "TARGET_SPE" | |
1405 | "evmhosmfanw %0,%1,%2" | |
1406 | [(set_attr "type" "veccomplex") | |
1407 | (set_attr "length" "4")]) | |
1408 | ||
1409 | (define_insn "spe_evmhosmfa" | |
1410 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1411 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1412 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] | |
1413 | "TARGET_SPE" | |
1414 | "evmhosmfa %0,%1,%2" | |
1415 | [(set_attr "type" "veccomplex") | |
1416 | (set_attr "length" "4")]) | |
1417 | ||
1418 | (define_insn "spe_evmhosmf" | |
1419 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1420 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1421 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) | |
1422 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1423 | "TARGET_SPE" | |
1424 | "evmhosmf %0,%1,%2" | |
1425 | [(set_attr "type" "veccomplex") | |
1426 | (set_attr "length" "4")]) | |
1427 | ||
1428 | (define_insn "spe_evmhosmiaaw" | |
1429 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1430 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1431 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1432 | (reg:V2SI SPE_ACC_REGNO)] 593)) | |
1433 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1434 | "TARGET_SPE" | |
1435 | "evmhosmiaaw %0,%1,%2" | |
1436 | [(set_attr "type" "veccomplex") | |
1437 | (set_attr "length" "4")]) | |
1438 | ||
1439 | (define_insn "spe_evmhosmianw" | |
1440 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1441 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1442 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1443 | (reg:V2SI SPE_ACC_REGNO)] 594)) | |
1444 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1445 | "TARGET_SPE" | |
1446 | "evmhosmianw %0,%1,%2" | |
1447 | [(set_attr "type" "veccomplex") | |
1448 | (set_attr "length" "4")]) | |
1449 | ||
1450 | (define_insn "spe_evmhosmia" | |
1451 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1452 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1453 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) | |
1454 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1455 | "TARGET_SPE" | |
1456 | "evmhosmia %0,%1,%2" | |
1457 | [(set_attr "type" "veccomplex") | |
1458 | (set_attr "length" "4")]) | |
1459 | ||
1460 | (define_insn "spe_evmhosmi" | |
1461 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1462 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1463 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] | |
1464 | "TARGET_SPE" | |
1465 | "evmhosmi %0,%1,%2" | |
1466 | [(set_attr "type" "veccomplex") | |
1467 | (set_attr "length" "4")]) | |
1468 | ||
1469 | (define_insn "spe_evmhossfaaw" | |
1470 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1471 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1472 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1473 | (reg:V2SI SPE_ACC_REGNO)] 597)) | |
1474 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1475 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1476 | "TARGET_SPE" | |
1477 | "evmhossfaaw %0,%1,%2" | |
1478 | [(set_attr "type" "veccomplex") | |
1479 | (set_attr "length" "4")]) | |
1480 | ||
1481 | (define_insn "spe_evmhossfanw" | |
1482 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1483 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1484 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1485 | (reg:V2SI SPE_ACC_REGNO)] 598)) | |
1486 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1487 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1488 | "TARGET_SPE" | |
1489 | "evmhossfanw %0,%1,%2" | |
1490 | [(set_attr "type" "veccomplex") | |
1491 | (set_attr "length" "4")]) | |
1492 | ||
1493 | (define_insn "spe_evmhossfa" | |
1494 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1495 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1496 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1497 | (reg:V2SI SPE_ACC_REGNO)] 599)) | |
1498 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1499 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1500 | "TARGET_SPE" | |
1501 | "evmhossfa %0,%1,%2" | |
1502 | [(set_attr "type" "veccomplex") | |
1503 | (set_attr "length" "4")]) | |
1504 | ||
1505 | (define_insn "spe_evmhossf" | |
1506 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1507 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1508 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) | |
1509 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1510 | "TARGET_SPE" | |
1511 | "evmhossf %0,%1,%2" | |
1512 | [(set_attr "type" "veccomplex") | |
1513 | (set_attr "length" "4")]) | |
1514 | ||
1515 | (define_insn "spe_evmhossiaaw" | |
1516 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1517 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1518 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1519 | (reg:V2SI SPE_ACC_REGNO)] 601)) | |
1520 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1521 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1522 | "TARGET_SPE" | |
1523 | "evmhossiaaw %0,%1,%2" | |
1524 | [(set_attr "type" "veccomplex") | |
1525 | (set_attr "length" "4")]) | |
1526 | ||
1527 | (define_insn "spe_evmhossianw" | |
1528 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1529 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1530 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1531 | (reg:V2SI SPE_ACC_REGNO)] 602)) | |
1532 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1533 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1534 | "TARGET_SPE" | |
1535 | "evmhossianw %0,%1,%2" | |
1536 | [(set_attr "type" "veccomplex") | |
1537 | (set_attr "length" "4")]) | |
1538 | ||
1539 | (define_insn "spe_evmhoumiaaw" | |
1540 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1541 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1542 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1543 | (reg:V2SI SPE_ACC_REGNO)] 603)) | |
1544 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1545 | "TARGET_SPE" | |
1546 | "evmhoumiaaw %0,%1,%2" | |
1547 | [(set_attr "type" "veccomplex") | |
1548 | (set_attr "length" "4")]) | |
1549 | ||
1550 | (define_insn "spe_evmhoumianw" | |
1551 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1552 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1553 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1554 | (reg:V2SI SPE_ACC_REGNO)] 604)) | |
1555 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1556 | "TARGET_SPE" | |
1557 | "evmhoumianw %0,%1,%2" | |
1558 | [(set_attr "type" "veccomplex") | |
1559 | (set_attr "length" "4")]) | |
1560 | ||
1561 | (define_insn "spe_evmhoumia" | |
1562 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1563 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1564 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) | |
1565 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1566 | "TARGET_SPE" | |
1567 | "evmhoumia %0,%1,%2" | |
1568 | [(set_attr "type" "veccomplex") | |
1569 | (set_attr "length" "4")]) | |
1570 | ||
1571 | (define_insn "spe_evmhoumi" | |
1572 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1573 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1574 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] | |
1575 | "TARGET_SPE" | |
1576 | "evmhoumi %0,%1,%2" | |
1577 | [(set_attr "type" "veccomplex") | |
1578 | (set_attr "length" "4")]) | |
1579 | ||
1580 | (define_insn "spe_evmhousiaaw" | |
1581 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1582 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1583 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1584 | (reg:V2SI SPE_ACC_REGNO)] 607)) | |
1585 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1586 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1587 | "TARGET_SPE" | |
1588 | "evmhousiaaw %0,%1,%2" | |
1589 | [(set_attr "type" "veccomplex") | |
1590 | (set_attr "length" "4")]) | |
1591 | ||
1592 | (define_insn "spe_evmhousianw" | |
1593 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1594 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1595 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1596 | (reg:V2SI SPE_ACC_REGNO)] 608)) | |
1597 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1598 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1599 | "TARGET_SPE" | |
1600 | "evmhousianw %0,%1,%2" | |
1601 | [(set_attr "type" "veccomplex") | |
1602 | (set_attr "length" "4")]) | |
1603 | ||
1604 | (define_insn "spe_evmmlssfa" | |
1605 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1606 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1607 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] | |
1608 | "TARGET_SPE" | |
1609 | "evmmlssfa %0,%1,%2" | |
1610 | [(set_attr "type" "veccomplex") | |
1611 | (set_attr "length" "4")]) | |
1612 | ||
1613 | (define_insn "spe_evmmlssf" | |
1614 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1615 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1616 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] | |
1617 | "TARGET_SPE" | |
1618 | "evmmlssf %0,%1,%2" | |
1619 | [(set_attr "type" "veccomplex") | |
1620 | (set_attr "length" "4")]) | |
1621 | ||
1622 | (define_insn "spe_evmwhsmfa" | |
1623 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1624 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1625 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) | |
1626 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1627 | "TARGET_SPE" | |
1628 | "evmwhsmfa %0,%1,%2" | |
1629 | [(set_attr "type" "veccomplex") | |
1630 | (set_attr "length" "4")]) | |
1631 | ||
1632 | (define_insn "spe_evmwhsmf" | |
1633 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1634 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1635 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] | |
1636 | "TARGET_SPE" | |
1637 | "evmwhsmf %0,%1,%2" | |
1638 | [(set_attr "type" "veccomplex") | |
1639 | (set_attr "length" "4")]) | |
1640 | ||
1641 | (define_insn "spe_evmwhsmia" | |
1642 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1643 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1644 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) | |
1645 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1646 | "TARGET_SPE" | |
1647 | "evmwhsmia %0,%1,%2" | |
1648 | [(set_attr "type" "veccomplex") | |
1649 | (set_attr "length" "4")]) | |
1650 | ||
1651 | (define_insn "spe_evmwhsmi" | |
1652 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1653 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1654 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] | |
1655 | "TARGET_SPE" | |
1656 | "evmwhsmi %0,%1,%2" | |
1657 | [(set_attr "type" "veccomplex") | |
1658 | (set_attr "length" "4")]) | |
1659 | ||
1660 | (define_insn "spe_evmwhssfa" | |
1661 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1662 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1663 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) | |
1664 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1665 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1666 | "TARGET_SPE" | |
1667 | "evmwhssfa %0,%1,%2" | |
1668 | [(set_attr "type" "veccomplex") | |
1669 | (set_attr "length" "4")]) | |
1670 | ||
1671 | (define_insn "spe_evmwhusian" | |
1672 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1673 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1674 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] | |
1675 | "TARGET_SPE" | |
1676 | "evmwhusian %0,%1,%2" | |
1677 | [(set_attr "type" "veccomplex") | |
1678 | (set_attr "length" "4")]) | |
1679 | ||
1680 | (define_insn "spe_evmwhssf" | |
1681 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1682 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1683 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) | |
1684 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1685 | "TARGET_SPE" | |
1686 | "evmwhssf %0,%1,%2" | |
1687 | [(set_attr "type" "veccomplex") | |
1688 | (set_attr "length" "4")]) | |
1689 | ||
1690 | (define_insn "spe_evmwhumia" | |
1691 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1692 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1693 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) | |
1694 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1695 | "TARGET_SPE" | |
1696 | "evmwhumia %0,%1,%2" | |
1697 | [(set_attr "type" "veccomplex") | |
1698 | (set_attr "length" "4")]) | |
1699 | ||
1700 | (define_insn "spe_evmwhumi" | |
1701 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1702 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1703 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] | |
1704 | "TARGET_SPE" | |
1705 | "evmwhumi %0,%1,%2" | |
1706 | [(set_attr "type" "veccomplex") | |
1707 | (set_attr "length" "4")]) | |
1708 | ||
1709 | (define_insn "spe_evmwlsmiaaw" | |
1710 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1711 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1712 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1713 | (reg:V2SI SPE_ACC_REGNO)] 635)) | |
1714 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1715 | "TARGET_SPE" | |
1716 | "evmwlsmiaaw %0,%1,%2" | |
1717 | [(set_attr "type" "veccomplex") | |
1718 | (set_attr "length" "4")]) | |
1719 | ||
1720 | (define_insn "spe_evmwlsmianw" | |
1721 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1722 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1723 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1724 | (reg:V2SI SPE_ACC_REGNO)] 636)) | |
1725 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1726 | "TARGET_SPE" | |
1727 | "evmwlsmianw %0,%1,%2" | |
1728 | [(set_attr "type" "veccomplex") | |
1729 | (set_attr "length" "4")]) | |
1730 | ||
1731 | (define_insn "spe_evmwlssiaaw" | |
1732 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1733 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1734 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1735 | (reg:V2SI SPE_ACC_REGNO)] 641)) | |
1736 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1737 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1738 | "TARGET_SPE" | |
1739 | "evmwlssiaaw %0,%1,%2" | |
1740 | [(set_attr "type" "veccomplex") | |
1741 | (set_attr "length" "4")]) | |
1742 | ||
1743 | (define_insn "spe_evmwlssianw" | |
1744 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1745 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1746 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1747 | (reg:V2SI SPE_ACC_REGNO)] 642)) | |
1748 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1749 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1750 | "TARGET_SPE" | |
1751 | "evmwlssianw %0,%1,%2" | |
1752 | [(set_attr "type" "veccomplex") | |
1753 | (set_attr "length" "4")]) | |
1754 | ||
1755 | (define_insn "spe_evmwlumiaaw" | |
1756 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1757 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1758 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1759 | (reg:V2SI SPE_ACC_REGNO)] 643)) | |
1760 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1761 | "TARGET_SPE" | |
1762 | "evmwlumiaaw %0,%1,%2" | |
1763 | [(set_attr "type" "veccomplex") | |
1764 | (set_attr "length" "4")]) | |
1765 | ||
1766 | (define_insn "spe_evmwlumianw" | |
1767 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1768 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1769 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1770 | (reg:V2SI SPE_ACC_REGNO)] 644)) | |
1771 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1772 | "TARGET_SPE" | |
1773 | "evmwlumianw %0,%1,%2" | |
1774 | [(set_attr "type" "veccomplex") | |
1775 | (set_attr "length" "4")]) | |
1776 | ||
1777 | (define_insn "spe_evmwlumia" | |
1778 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1779 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1780 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) | |
1781 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1782 | "TARGET_SPE" | |
1783 | "evmwlumia %0,%1,%2" | |
1784 | [(set_attr "type" "veccomplex") | |
1785 | (set_attr "length" "4")]) | |
1786 | ||
1787 | (define_insn "spe_evmwlumi" | |
1788 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1789 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1790 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] | |
1791 | "TARGET_SPE" | |
1792 | "evmwlumi %0,%1,%2" | |
1793 | [(set_attr "type" "veccomplex") | |
1794 | (set_attr "length" "4")]) | |
1795 | ||
1796 | (define_insn "spe_evmwlusiaaw" | |
1797 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1798 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1799 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1800 | (reg:V2SI SPE_ACC_REGNO)] 647)) | |
1801 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1802 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1803 | "TARGET_SPE" | |
1804 | "evmwlusiaaw %0,%1,%2" | |
1805 | [(set_attr "type" "veccomplex") | |
1806 | (set_attr "length" "4")]) | |
1807 | ||
1808 | (define_insn "spe_evmwlusianw" | |
1809 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1810 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1811 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1812 | (reg:V2SI SPE_ACC_REGNO)] 648)) | |
1813 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1814 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1815 | "TARGET_SPE" | |
1816 | "evmwlusianw %0,%1,%2" | |
1817 | [(set_attr "type" "veccomplex") | |
1818 | (set_attr "length" "4")]) | |
1819 | ||
1820 | (define_insn "spe_evmwsmfaa" | |
1821 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1822 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1823 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1824 | (reg:V2SI SPE_ACC_REGNO)] 649)) | |
1825 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1826 | "TARGET_SPE" | |
1827 | "evmwsmfaa %0,%1,%2" | |
1828 | [(set_attr "type" "veccomplex") | |
1829 | (set_attr "length" "4")]) | |
1830 | ||
1831 | (define_insn "spe_evmwsmfan" | |
1832 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1833 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1834 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1835 | (reg:V2SI SPE_ACC_REGNO)] 650)) | |
1836 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1837 | "TARGET_SPE" | |
1838 | "evmwsmfan %0,%1,%2" | |
1839 | [(set_attr "type" "veccomplex") | |
1840 | (set_attr "length" "4")]) | |
1841 | ||
1842 | (define_insn "spe_evmwsmfa" | |
1843 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1844 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1845 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) | |
1846 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1847 | "TARGET_SPE" | |
1848 | "evmwsmfa %0,%1,%2" | |
1849 | [(set_attr "type" "veccomplex") | |
1850 | (set_attr "length" "4")]) | |
1851 | ||
1852 | (define_insn "spe_evmwsmf" | |
1853 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1854 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1855 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] | |
1856 | "TARGET_SPE" | |
1857 | "evmwsmf %0,%1,%2" | |
1858 | [(set_attr "type" "veccomplex") | |
1859 | (set_attr "length" "4")]) | |
1860 | ||
1861 | (define_insn "spe_evmwsmiaa" | |
1862 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1863 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1864 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1865 | (reg:V2SI SPE_ACC_REGNO)] 653)) | |
1866 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1867 | "TARGET_SPE" | |
1868 | "evmwsmiaa %0,%1,%2" | |
1869 | [(set_attr "type" "veccomplex") | |
1870 | (set_attr "length" "4")]) | |
1871 | ||
1872 | (define_insn "spe_evmwsmian" | |
1873 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1874 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1875 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1876 | (reg:V2SI SPE_ACC_REGNO)] 654)) | |
1877 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1878 | "TARGET_SPE" | |
1879 | "evmwsmian %0,%1,%2" | |
1880 | [(set_attr "type" "veccomplex") | |
1881 | (set_attr "length" "4")]) | |
1882 | ||
1883 | (define_insn "spe_evmwsmia" | |
1884 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1885 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1886 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) | |
1887 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1888 | "TARGET_SPE" | |
1889 | "evmwsmia %0,%1,%2" | |
1890 | [(set_attr "type" "veccomplex") | |
1891 | (set_attr "length" "4")]) | |
1892 | ||
1893 | (define_insn "spe_evmwsmi" | |
1894 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1895 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1896 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] | |
1897 | "TARGET_SPE" | |
1898 | "evmwsmi %0,%1,%2" | |
1899 | [(set_attr "type" "veccomplex") | |
1900 | (set_attr "length" "4")]) | |
1901 | ||
1902 | (define_insn "spe_evmwssfaa" | |
1903 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1904 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1905 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1906 | (reg:V2SI SPE_ACC_REGNO)] 657)) | |
1907 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1908 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1909 | "TARGET_SPE" | |
1910 | "evmwssfaa %0,%1,%2" | |
1911 | [(set_attr "type" "veccomplex") | |
1912 | (set_attr "length" "4")]) | |
1913 | ||
1914 | (define_insn "spe_evmwssfan" | |
1915 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1916 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1917 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1918 | (reg:V2SI SPE_ACC_REGNO)] 658)) | |
1919 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1920 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1921 | "TARGET_SPE" | |
1922 | "evmwssfan %0,%1,%2" | |
1923 | [(set_attr "type" "veccomplex") | |
1924 | (set_attr "length" "4")]) | |
1925 | ||
1926 | (define_insn "spe_evmwssfa" | |
1927 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1928 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1929 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) | |
1930 | (clobber (reg:SI SPEFSCR_REGNO)) | |
1931 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1932 | "TARGET_SPE" | |
1933 | "evmwssfa %0,%1,%2" | |
1934 | [(set_attr "type" "veccomplex") | |
1935 | (set_attr "length" "4")]) | |
1936 | ||
1937 | (define_insn "spe_evmwssf" | |
1938 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1939 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1940 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) | |
1941 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1942 | "TARGET_SPE" | |
1943 | "evmwssf %0,%1,%2" | |
1944 | [(set_attr "type" "veccomplex") | |
1945 | (set_attr "length" "4")]) | |
1946 | ||
1947 | (define_insn "spe_evmwumiaa" | |
1948 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1949 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1950 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1951 | (reg:V2SI SPE_ACC_REGNO)] 661)) | |
1952 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1953 | "TARGET_SPE" | |
1954 | "evmwumiaa %0,%1,%2" | |
1955 | [(set_attr "type" "veccomplex") | |
1956 | (set_attr "length" "4")]) | |
1957 | ||
1958 | (define_insn "spe_evmwumian" | |
1959 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1960 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1961 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1962 | (reg:V2SI SPE_ACC_REGNO)] 662)) | |
1963 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1964 | "TARGET_SPE" | |
1965 | "evmwumian %0,%1,%2" | |
1966 | [(set_attr "type" "veccomplex") | |
1967 | (set_attr "length" "4")]) | |
1968 | ||
1969 | (define_insn "spe_evmwumia" | |
1970 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1971 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1972 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) | |
1973 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
1974 | "TARGET_SPE" | |
1975 | "evmwumia %0,%1,%2" | |
1976 | [(set_attr "type" "veccomplex") | |
1977 | (set_attr "length" "4")]) | |
1978 | ||
1979 | (define_insn "spe_evmwumi" | |
1980 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1981 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1982 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] | |
1983 | "TARGET_SPE" | |
1984 | "evmwumi %0,%1,%2" | |
1985 | [(set_attr "type" "veccomplex") | |
1986 | (set_attr "length" "4")]) | |
1987 | ||
1988 | (define_insn "addv2si3" | |
1989 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1990 | (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1991 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
1992 | "TARGET_SPE" | |
1993 | "evaddw %0,%1,%2" | |
1994 | [(set_attr "type" "vecsimple") | |
1995 | (set_attr "length" "4")]) | |
1996 | ||
1997 | (define_insn "spe_evaddusiaaw" | |
1998 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1999 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2000 | (reg:V2SI SPE_ACC_REGNO)] 673)) | |
2001 | (clobber (reg:SI SPEFSCR_REGNO)) | |
2002 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2003 | "TARGET_SPE" | |
2004 | "evaddusiaaw %0,%1" | |
2005 | [(set_attr "type" "veccomplex") | |
2006 | (set_attr "length" "4")]) | |
2007 | ||
2008 | (define_insn "spe_evaddumiaaw" | |
2009 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2010 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2011 | (reg:V2SI SPE_ACC_REGNO)] 674)) | |
2012 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2013 | "TARGET_SPE" | |
2014 | "evaddumiaaw %0,%1" | |
2015 | [(set_attr "type" "veccomplex") | |
2016 | (set_attr "length" "4")]) | |
2017 | ||
2018 | (define_insn "spe_evaddssiaaw" | |
2019 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2020 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2021 | (reg:V2SI SPE_ACC_REGNO)] 675)) | |
2022 | (clobber (reg:SI SPEFSCR_REGNO)) | |
2023 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2024 | "TARGET_SPE" | |
2025 | "evaddssiaaw %0,%1" | |
2026 | [(set_attr "type" "veccomplex") | |
2027 | (set_attr "length" "4")]) | |
2028 | ||
2029 | (define_insn "spe_evaddsmiaaw" | |
2030 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2031 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2032 | (reg:V2SI SPE_ACC_REGNO)] 676)) | |
2033 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2034 | "TARGET_SPE" | |
2035 | "evaddsmiaaw %0,%1" | |
2036 | [(set_attr "type" "veccomplex") | |
2037 | (set_attr "length" "4")]) | |
2038 | ||
2039 | (define_insn "spe_evaddiw" | |
2040 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2041 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2042 | (match_operand:QI 2 "immediate_operand" "i")] 677))] | |
2043 | "TARGET_SPE" | |
2044 | "evaddiw %0,%1,%2" | |
2045 | [(set_attr "type" "vecsimple") | |
2046 | (set_attr "length" "4")]) | |
2047 | ||
2048 | (define_insn "spe_evsubifw" | |
2049 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2050 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2051 | (match_operand:QI 2 "immediate_operand" "i")] 678))] | |
2052 | "TARGET_SPE" | |
2053 | "evsubifw %0,%2,%1" | |
2054 | [(set_attr "type" "veccomplex") | |
2055 | (set_attr "length" "4")]) | |
2056 | ||
2057 | (define_insn "subv2si3" | |
2058 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2059 | (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2060 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
2061 | "TARGET_SPE" | |
2062 | "evsubfw %0,%2,%1" | |
2063 | [(set_attr "type" "veccomplex") | |
2064 | (set_attr "length" "4")]) | |
2065 | ||
2066 | (define_insn "spe_evsubfusiaaw" | |
2067 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2068 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2069 | (reg:V2SI SPE_ACC_REGNO)] 679)) | |
2070 | (clobber (reg:SI SPEFSCR_REGNO)) | |
2071 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2072 | "TARGET_SPE" | |
2073 | "evsubfusiaaw %0,%1" | |
2074 | [(set_attr "type" "veccomplex") | |
2075 | (set_attr "length" "4")]) | |
2076 | ||
2077 | (define_insn "spe_evsubfumiaaw" | |
2078 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2079 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2080 | (reg:V2SI SPE_ACC_REGNO)] 680)) | |
2081 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2082 | "TARGET_SPE" | |
2083 | "evsubfumiaaw %0,%1" | |
2084 | [(set_attr "type" "veccomplex") | |
2085 | (set_attr "length" "4")]) | |
2086 | ||
2087 | (define_insn "spe_evsubfssiaaw" | |
2088 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2089 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2090 | (reg:V2SI SPE_ACC_REGNO)] 681)) | |
2091 | (clobber (reg:SI SPEFSCR_REGNO)) | |
2092 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2093 | "TARGET_SPE" | |
2094 | "evsubfssiaaw %0,%1" | |
2095 | [(set_attr "type" "veccomplex") | |
2096 | (set_attr "length" "4")]) | |
2097 | ||
2098 | (define_insn "spe_evsubfsmiaaw" | |
2099 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2100 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2101 | (reg:V2SI SPE_ACC_REGNO)] 682)) | |
2102 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
2103 | "TARGET_SPE" | |
2104 | "evsubfsmiaaw %0,%1" | |
2105 | [(set_attr "type" "veccomplex") | |
2106 | (set_attr "length" "4")]) | |
2107 | ||
2108 | (define_insn "spe_evmra" | |
2109 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2110 | (match_operand:V2SI 1 "gpc_reg_operand" "r")) | |
2111 | (set (reg:V2SI SPE_ACC_REGNO) | |
2112 | (unspec:V2SI [(match_dup 1)] 726))] | |
2113 | "TARGET_SPE" | |
2114 | "evmra %0,%1" | |
2115 | [(set_attr "type" "veccomplex") | |
2116 | (set_attr "length" "4")]) | |
2117 | ||
2118 | (define_insn "divv2si3" | |
2119 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2120 | (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2121 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
2122 | (clobber (reg:SI SPEFSCR_REGNO))] | |
2123 | "TARGET_SPE" | |
2124 | "evdivws %0,%1,%2" | |
2125 | [(set_attr "type" "vecdiv") | |
2126 | (set_attr "length" "4")]) | |
2127 | ||
2128 | (define_insn "spe_evdivwu" | |
2129 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2130 | (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2131 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
2132 | (clobber (reg:SI SPEFSCR_REGNO))] | |
2133 | "TARGET_SPE" | |
2134 | "evdivwu %0,%1,%2" | |
2135 | [(set_attr "type" "vecdiv") | |
2136 | (set_attr "length" "4")]) | |
2137 | ||
2138 | (define_insn "spe_evsplatfi" | |
2139 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2140 | (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] | |
2141 | "TARGET_SPE" | |
2142 | "evsplatfi %0,%1" | |
2143 | [(set_attr "type" "vecperm") | |
2144 | (set_attr "length" "4")]) | |
2145 | ||
2146 | (define_insn "spe_evsplati" | |
2147 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2148 | (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] | |
2149 | "TARGET_SPE" | |
2150 | "evsplati %0,%1" | |
2151 | [(set_attr "type" "vecperm") | |
2152 | (set_attr "length" "4")]) | |
2153 | ||
2154 | (define_insn "spe_evstdd" | |
2155 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2156 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2157 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2158 | (unspec [(const_int 0)] 686)] | |
2159 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2160 | "evstdd %2,%1*8(%0)" | |
2161 | [(set_attr "type" "vecstore") | |
2162 | (set_attr "length" "4")]) | |
2163 | ||
2164 | (define_insn "spe_evstddx" | |
2165 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2166 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2167 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2168 | (unspec [(const_int 0)] 687)] | |
2169 | "TARGET_SPE" | |
2170 | "evstddx %2,%0,%1" | |
2171 | [(set_attr "type" "vecstore") | |
2172 | (set_attr "length" "4")]) | |
2173 | ||
2174 | (define_insn "spe_evstdh" | |
2175 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2176 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2177 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2178 | (unspec [(const_int 0)] 688)] | |
2179 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2180 | "evstdh %2,%1*8(%0)" | |
2181 | [(set_attr "type" "vecstore") | |
2182 | (set_attr "length" "4")]) | |
2183 | ||
2184 | (define_insn "spe_evstdhx" | |
2185 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2186 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2187 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2188 | (unspec [(const_int 0)] 689)] | |
2189 | "TARGET_SPE" | |
2190 | "evstdhx %2,%0,%1" | |
2191 | [(set_attr "type" "vecstore") | |
2192 | (set_attr "length" "4")]) | |
2193 | ||
2194 | (define_insn "spe_evstdw" | |
2195 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2196 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2197 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2198 | (unspec [(const_int 0)] 690)] | |
2199 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2200 | "evstdw %2,%1*8(%0)" | |
2201 | [(set_attr "type" "vecstore") | |
2202 | (set_attr "length" "4")]) | |
2203 | ||
2204 | (define_insn "spe_evstdwx" | |
2205 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2206 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2207 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2208 | (unspec [(const_int 0)] 691)] | |
2209 | "TARGET_SPE" | |
2210 | "evstdwx %2,%0,%1" | |
2211 | [(set_attr "type" "vecstore") | |
2212 | (set_attr "length" "4")]) | |
2213 | ||
2214 | (define_insn "spe_evstwhe" | |
2215 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2216 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2217 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2218 | (unspec [(const_int 0)] 692)] | |
2219 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2220 | "evstwhe %2,%1*4(%0)" | |
2221 | [(set_attr "type" "vecstore") | |
2222 | (set_attr "length" "4")]) | |
2223 | ||
2224 | (define_insn "spe_evstwhex" | |
2225 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2226 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2227 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2228 | (unspec [(const_int 0)] 693)] | |
2229 | "TARGET_SPE" | |
2230 | "evstwhex %2,%0,%1" | |
2231 | [(set_attr "type" "vecstore") | |
2232 | (set_attr "length" "4")]) | |
2233 | ||
2234 | (define_insn "spe_evstwho" | |
2235 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2236 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2237 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2238 | (unspec [(const_int 0)] 694)] | |
2239 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2240 | "evstwho %2,%1*4(%0)" | |
2241 | [(set_attr "type" "vecstore") | |
2242 | (set_attr "length" "4")]) | |
2243 | ||
2244 | (define_insn "spe_evstwhox" | |
2245 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2246 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2247 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2248 | (unspec [(const_int 0)] 695)] | |
2249 | "TARGET_SPE" | |
2250 | "evstwhox %2,%0,%1" | |
2251 | [(set_attr "type" "vecstore") | |
2252 | (set_attr "length" "4")]) | |
2253 | ||
2254 | (define_insn "spe_evstwwe" | |
2255 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2256 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2257 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2258 | (unspec [(const_int 0)] 696)] | |
2259 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2260 | "evstwwe %2,%1*4(%0)" | |
2261 | [(set_attr "type" "vecstore") | |
2262 | (set_attr "length" "4")]) | |
2263 | ||
2264 | (define_insn "spe_evstwwex" | |
2265 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2266 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2267 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2268 | (unspec [(const_int 0)] 697)] | |
2269 | "TARGET_SPE" | |
2270 | "evstwwex %2,%0,%1" | |
2271 | [(set_attr "type" "vecstore") | |
2272 | (set_attr "length" "4")]) | |
2273 | ||
2274 | (define_insn "spe_evstwwo" | |
2275 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2276 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2277 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2278 | (unspec [(const_int 0)] 698)] | |
2279 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
2280 | "evstwwo %2,%1*4(%0)" | |
2281 | [(set_attr "type" "vecstore") | |
2282 | (set_attr "length" "4")]) | |
2283 | ||
2284 | (define_insn "spe_evstwwox" | |
2285 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2286 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2287 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2288 | (unspec [(const_int 0)] 699)] | |
2289 | "TARGET_SPE" | |
2290 | "evstwwox %2,%0,%1" | |
2291 | [(set_attr "type" "vecstore") | |
2292 | (set_attr "length" "4")]) | |
2293 | ||
2294 | ;; Double-precision floating point instructions. | |
2295 | ||
2296 | ;; FIXME: Add o=r option. | |
2297 | (define_insn "*frob_<SPE64:mode>_<DITI:mode>" | |
2298 | [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r") | |
2299 | (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))] | |
2300 | "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode) | |
2301 | || (TARGET_SPE && <SPE64:MODE>mode != DFmode)" | |
2302 | { | |
2303 | switch (which_alternative) | |
2304 | { | |
2305 | default: | |
2306 | gcc_unreachable (); | |
2307 | case 0: | |
2308 | if (WORDS_BIG_ENDIAN) | |
2309 | return "evmergelo %0,%1,%L1"; | |
2310 | else | |
2311 | return "evmergelo %0,%L1,%1"; | |
2312 | case 1: | |
2313 | return "evldd%X1 %0,%y1"; | |
2314 | } | |
2315 | }) | |
2316 | ||
2317 | (define_insn "*frob_<SPE64:mode>_ti_8" | |
2318 | [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r") | |
2319 | (subreg:SPE64 (match_operand:TI 1 "input_operand" "r") 8))] | |
2320 | "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode) | |
2321 | || (TARGET_SPE && <SPE64:MODE>mode != DFmode)" | |
2322 | { | |
2323 | if (WORDS_BIG_ENDIAN) | |
2324 | return "evmergelo %0,%Y1,%Z1"; | |
2325 | else | |
2326 | return "evmergelo %0,%Z1,%Y1"; | |
2327 | }) | |
2328 | ||
2329 | (define_insn "*frob_tf_ti" | |
2330 | [(set (match_operand:TF 0 "gpc_reg_operand" "=r") | |
2331 | (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))] | |
2332 | "TARGET_E500_DOUBLE" | |
2333 | { | |
2334 | if (WORDS_BIG_ENDIAN) | |
2335 | return "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1"; | |
2336 | else | |
2337 | return "evmergelo %L0,%Z1,%Y1\;evmergelo %0,%L1,%1"; | |
2338 | } | |
2339 | [(set_attr "length" "8")]) | |
2340 | ||
2341 | (define_insn "*frob_<mode>_di_2" | |
2342 | [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0) | |
2343 | (match_operand:DI 1 "input_operand" "r,m"))] | |
2344 | "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2345 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
2346 | { | |
2347 | switch (which_alternative) | |
2348 | { | |
2349 | default: | |
2350 | gcc_unreachable (); | |
2351 | case 0: | |
2352 | if (WORDS_BIG_ENDIAN) | |
2353 | return "evmergelo %0,%1,%L1"; | |
2354 | else | |
2355 | return "evmergelo %0,%L1,%1"; | |
2356 | case 1: | |
2357 | return "evldd%X1 %0,%y1"; | |
2358 | } | |
2359 | }) | |
2360 | ||
2361 | (define_insn "*frob_tf_di_8_2" | |
2362 | [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8) | |
2363 | (match_operand:DI 1 "input_operand" "r,m"))] | |
2364 | "TARGET_E500_DOUBLE" | |
2365 | { | |
2366 | switch (which_alternative) | |
2367 | { | |
2368 | default: | |
2369 | gcc_unreachable (); | |
2370 | case 0: | |
2371 | if (WORDS_BIG_ENDIAN) | |
2372 | return "evmergelo %L0,%1,%L1"; | |
2373 | else | |
2374 | return "evmergelo %L0,%L1,%1"; | |
2375 | case 1: | |
2376 | return "evldd%X1 %L0,%y1"; | |
2377 | } | |
2378 | }) | |
2379 | ||
2380 | (define_insn "*frob_di_<mode>" | |
2381 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&r") | |
2382 | (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))] | |
2383 | "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2384 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
2385 | { | |
2386 | if (WORDS_BIG_ENDIAN) | |
2387 | return "evmergehi %0,%1,%1\;mr %L0,%1"; | |
2388 | else | |
2389 | return "evmergehi %L0,%1,%1\;mr %0,%1"; | |
2390 | } | |
2391 | [(set_attr "length" "8")]) | |
2392 | ||
2393 | (define_insn "*frob_ti_tf" | |
2394 | [(set (match_operand:TI 0 "nonimmediate_operand" "=&r") | |
2395 | (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))] | |
2396 | "TARGET_E500_DOUBLE" | |
2397 | { | |
2398 | if (WORDS_BIG_ENDIAN) | |
2399 | return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"; | |
2400 | else | |
2401 | return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1"; | |
2402 | } | |
2403 | [(set_attr "length" "16")]) | |
2404 | ||
2405 | (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2" | |
2406 | [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0) | |
2407 | (match_operand:SPE64 1 "input_operand" "r,m"))] | |
2408 | "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode) | |
2409 | || (TARGET_SPE && <SPE64:MODE>mode != DFmode)" | |
2410 | "* | |
2411 | { | |
2412 | switch (which_alternative) | |
2413 | { | |
2414 | default: | |
2415 | gcc_unreachable (); | |
2416 | case 0: | |
2417 | if (WORDS_BIG_ENDIAN) | |
2418 | return \"evmergehi %0,%1,%1\;mr %L0,%1\"; | |
2419 | else | |
2420 | return \"evmergehi %L0,%1,%1\;mr %0,%1\"; | |
2421 | case 1: | |
2422 | /* If the address is not offsettable we need to load the whole | |
2423 | doubleword into a 64-bit register and then copy the high word | |
2424 | to form the correct output layout. */ | |
2425 | if (!offsettable_nonstrict_memref_p (operands[1])) | |
2426 | { | |
2427 | if (WORDS_BIG_ENDIAN) | |
2428 | return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\"; | |
2429 | else | |
2430 | return \"evldd%X1 %0,%y1\;evmergehi %L0,%0,%0\"; | |
2431 | } | |
2432 | /* If the low-address word is used in the address, we must load | |
2433 | it last. Otherwise, load it first. Note that we cannot have | |
2434 | auto-increment in that case since the address register is | |
2435 | known to be dead. */ | |
2436 | if (refers_to_regno_p (REGNO (operands[0]), operands[1])) | |
2437 | { | |
2438 | if (WORDS_BIG_ENDIAN) | |
2439 | return \"lwz %L0,%L1\;lwz %0,%1\"; | |
2440 | else | |
2441 | return \"lwz %0,%1\;lwz %L0,%L1\"; | |
2442 | } | |
2443 | else | |
2444 | { | |
2445 | if (WORDS_BIG_ENDIAN) | |
2446 | return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\"; | |
2447 | else | |
2448 | return \"lwz%U1%X1 %L0,%L1\;lwz %0,%1\"; | |
2449 | } | |
2450 | } | |
2451 | }" | |
2452 | [(set_attr "length" "8,8")]) | |
2453 | ||
2454 | ; As the above, but TImode at offset 8. | |
2455 | (define_insn "*frob_ti_<mode>_8_2" | |
2456 | [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8) | |
2457 | (match_operand:SPE64 1 "input_operand" "r,m"))] | |
2458 | "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) | |
2459 | || (TARGET_SPE && <MODE>mode != DFmode)" | |
2460 | "* | |
2461 | { | |
2462 | switch (which_alternative) | |
2463 | { | |
2464 | default: | |
2465 | gcc_unreachable (); | |
2466 | case 0: | |
2467 | if (WORDS_BIG_ENDIAN) | |
2468 | return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\"; | |
2469 | else | |
2470 | return \"evmergehi %Z0,%1,%1\;mr %Y0,%1\"; | |
2471 | case 1: | |
2472 | if (!offsettable_nonstrict_memref_p (operands[1])) | |
2473 | { | |
2474 | if (WORDS_BIG_ENDIAN) | |
2475 | return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\"; | |
2476 | else | |
2477 | return \"evldd%X1 %Y0,%y1\;evmergehi %Z0,%Y0,%Y0\"; | |
2478 | } | |
2479 | if (refers_to_regno_p (REGNO (operands[0]), operands[1])) | |
2480 | { | |
2481 | if (WORDS_BIG_ENDIAN) | |
2482 | return \"lwz %Z0,%L1\;lwz %Y0,%1\"; | |
2483 | else | |
2484 | return \"lwz %Y0,%1\;lwz %Z0,%L1\"; | |
2485 | } | |
2486 | else | |
2487 | { | |
2488 | if (WORDS_BIG_ENDIAN) | |
2489 | return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\"; | |
2490 | else | |
2491 | return \"lwz%U1%X1 %Z0,%L1\;lwz %Y0,%1\"; | |
2492 | } | |
2493 | } | |
2494 | }" | |
2495 | [(set_attr "length" "8,8")]) | |
2496 | ||
2497 | (define_insn "*frob_ti_tf_2" | |
2498 | [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0) | |
2499 | (match_operand:TF 1 "input_operand" "r"))] | |
2500 | "TARGET_E500_DOUBLE" | |
2501 | { | |
2502 | if (WORDS_BIG_ENDIAN) | |
2503 | return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"; | |
2504 | else | |
2505 | return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1"; | |
2506 | } | |
2507 | [(set_attr "length" "16")]) | |
2508 | ||
2509 | (define_insn "mov_si<mode>_e500_subreg0_be" | |
2510 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0) | |
2511 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2512 | "WORDS_BIG_ENDIAN | |
2513 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2514 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2515 | "@ | |
2516 | evmergelo %0,%1,%0 | |
2517 | evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0" | |
2518 | [(set_attr "length" "4,12")]) | |
2519 | ||
2520 | (define_insn "*mov_si<mode>_e500_subreg0_le" | |
2521 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 0) | |
2522 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2523 | "!WORDS_BIG_ENDIAN | |
2524 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2525 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2526 | "@ | |
2527 | mr %0,%1 | |
2528 | lwz%U1%X1 %0,%1") | |
2529 | ||
2530 | (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be" | |
2531 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) | |
2532 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
2533 | (match_operand 2 "" "")))] | |
2534 | "WORDS_BIG_ENDIAN | |
2535 | && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2536 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) | |
2537 | && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())" | |
2538 | "#" | |
2539 | "&& 1" | |
2540 | [(pc)] | |
2541 | { | |
2542 | rtx tmp = gen_reg_rtx (SImode); | |
2543 | emit_insn (gen_elf_low (tmp, operands[1], operands[2])); | |
2544 | emit_insn (gen_mov_si<mode>_e500_subreg0_be (operands[0], tmp)); | |
2545 | DONE; | |
2546 | } | |
2547 | [(set_attr "length" "8")]) | |
2548 | ||
2549 | (define_insn "*mov_si<mode>_e500_subreg0_elf_low_le" | |
2550 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) | |
2551 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
2552 | (match_operand 2 "" "")))] | |
2553 | "!WORDS_BIG_ENDIAN | |
2554 | && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2555 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) | |
2556 | && TARGET_ELF && !TARGET_64BIT)" | |
2557 | "addi %0,%1,%K2") | |
2558 | ||
2559 | ;; ??? Could use evstwwe for memory stores in some cases, depending on | |
2560 | ;; the offset. | |
2561 | (define_insn "*mov_si<mode>_e500_subreg0_2_be" | |
2562 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2563 | (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))] | |
2564 | "WORDS_BIG_ENDIAN | |
2565 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2566 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2567 | "@ | |
2568 | evmergehi %0,%0,%1 | |
2569 | evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" | |
2570 | [(set_attr "length" "4,8")]) | |
2571 | ||
2572 | (define_insn "*mov_si<mode>_e500_subreg0_2_le" | |
2573 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2574 | (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,r") 0))] | |
2575 | "!WORDS_BIG_ENDIAN | |
2576 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2577 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2578 | "@ | |
2579 | mr %0,%1 | |
2580 | stw%U0%X0 %1,%0") | |
2581 | ||
2582 | (define_insn "*mov_si<mode>_e500_subreg4_be" | |
2583 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4) | |
2584 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2585 | "WORDS_BIG_ENDIAN | |
2586 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2587 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2588 | "@ | |
2589 | mr %0,%1 | |
2590 | lwz%U1%X1 %0,%1") | |
2591 | ||
2592 | (define_insn "mov_si<mode>_e500_subreg4_le" | |
2593 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 4) | |
2594 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2595 | "!WORDS_BIG_ENDIAN | |
2596 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2597 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2598 | "@ | |
2599 | evmergelo %0,%1,%0 | |
2600 | evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0" | |
2601 | [(set_attr "length" "4,12")]) | |
2602 | ||
2603 | (define_insn "*mov_si<mode>_e500_subreg4_elf_low_be" | |
2604 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) | |
2605 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
2606 | (match_operand 2 "" "")))] | |
2607 | "WORDS_BIG_ENDIAN | |
2608 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2609 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) | |
2610 | && TARGET_ELF && !TARGET_64BIT" | |
2611 | "addi %0,%1,%K2") | |
2612 | ||
2613 | (define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le" | |
2614 | [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) | |
2615 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
2616 | (match_operand 2 "" "")))] | |
2617 | "!WORDS_BIG_ENDIAN | |
2618 | && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2619 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)) | |
2620 | && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())" | |
2621 | "#" | |
2622 | "&& 1" | |
2623 | [(pc)] | |
2624 | { | |
2625 | rtx tmp = gen_reg_rtx (SImode); | |
2626 | emit_insn (gen_elf_low (tmp, operands[1], operands[2])); | |
2627 | emit_insn (gen_mov_si<mode>_e500_subreg4_le (operands[0], tmp)); | |
2628 | DONE; | |
2629 | } | |
2630 | [(set_attr "length" "8")]) | |
2631 | ||
2632 | (define_insn "*mov_si<mode>_e500_subreg4_2_be" | |
2633 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2634 | (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))] | |
2635 | "WORDS_BIG_ENDIAN | |
2636 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2637 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2638 | "@ | |
2639 | mr %0,%1 | |
2640 | stw%U0%X0 %1,%0") | |
2641 | ||
2642 | (define_insn "*mov_si<mode>_e500_subreg4_2_le" | |
2643 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2644 | (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))] | |
2645 | "!WORDS_BIG_ENDIAN | |
2646 | && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
2647 | || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))" | |
2648 | "@ | |
2649 | evmergehi %0,%0,%1 | |
2650 | evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" | |
2651 | [(set_attr "length" "4,8")]) | |
2652 | ||
2653 | (define_insn "*mov_sitf_e500_subreg8_be" | |
2654 | [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8) | |
2655 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2656 | "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2657 | "@ | |
2658 | evmergelo %L0,%1,%L0 | |
2659 | evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0" | |
2660 | [(set_attr "length" "4,12")]) | |
2661 | ||
2662 | (define_insn "*mov_sitf_e500_subreg8_le" | |
2663 | [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 8) | |
2664 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2665 | "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2666 | "@ | |
2667 | mr %L0,%1 | |
2668 | lwz%U1%X1 %L0,%1") | |
2669 | ||
2670 | (define_insn "*mov_sitf_e500_subreg8_2_be" | |
2671 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2672 | (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))] | |
2673 | "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2674 | "@ | |
2675 | evmergehi %0,%0,%L1 | |
2676 | evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0" | |
2677 | [(set_attr "length" "4,8")]) | |
2678 | ||
2679 | (define_insn "*mov_sitf_e500_subreg8_2_le" | |
2680 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2681 | (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))] | |
2682 | "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2683 | "@ | |
2684 | mr %0,%L1 | |
2685 | stw%U0%X0 %L1,%0") | |
2686 | ||
2687 | (define_insn "*mov_sitf_e500_subreg12_be" | |
2688 | [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12) | |
2689 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2690 | "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2691 | "@ | |
2692 | mr %L0,%1 | |
2693 | lwz%U1%X1 %L0,%1") | |
2694 | ||
2695 | (define_insn "*mov_sitf_e500_subreg12_le" | |
2696 | [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 12) | |
2697 | (match_operand:SI 1 "input_operand" "r,m"))] | |
2698 | "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2699 | "@ | |
2700 | evmergelo %L0,%1,%L0 | |
2701 | evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0" | |
2702 | [(set_attr "length" "4,12")]) | |
2703 | ||
2704 | (define_insn "*mov_sitf_e500_subreg12_2_be" | |
2705 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2706 | (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))] | |
2707 | "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2708 | "@ | |
2709 | mr %0,%L1 | |
2710 | stw%U0%X0 %L1,%0") | |
2711 | ||
2712 | (define_insn "*mov_sitf_e500_subreg12_2_le" | |
2713 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
2714 | (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))] | |
2715 | "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" | |
2716 | "@ | |
2717 | evmergehi %0,%0,%L1 | |
2718 | evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0" | |
2719 | [(set_attr "length" "4,8")]) | |
2720 | ||
2721 | ;; FIXME: Allow r=CONST0. | |
2722 | (define_insn "*movdf_e500_double" | |
2723 | [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m") | |
2724 | (match_operand:DF 1 "input_operand" "r,m,r"))] | |
2725 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
2726 | && (gpc_reg_operand (operands[0], DFmode) | |
2727 | || gpc_reg_operand (operands[1], DFmode))" | |
2728 | "* | |
2729 | { | |
2730 | switch (which_alternative) | |
2731 | { | |
2732 | case 0: | |
2733 | return \"evor %0,%1,%1\"; | |
2734 | case 1: | |
2735 | return \"evldd%X1 %0,%y1\"; | |
2736 | case 2: | |
2737 | return \"evstdd%X0 %1,%y0\"; | |
2738 | default: | |
2739 | gcc_unreachable (); | |
2740 | } | |
2741 | }" | |
2742 | [(set_attr "type" "*,vecload,vecstore") | |
2743 | (set_attr "length" "*,*,*")]) | |
2744 | ||
2745 | (define_insn "spe_truncdfsf2" | |
2746 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
2747 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2748 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2749 | "efscfd %0,%1") | |
2750 | ||
2751 | (define_insn "spe_absdf2" | |
2752 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2753 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2754 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2755 | "efdabs %0,%1") | |
2756 | ||
2757 | (define_insn "spe_nabsdf2" | |
2758 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2759 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))] | |
2760 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2761 | "efdnabs %0,%1") | |
2762 | ||
2763 | (define_insn "spe_negdf2" | |
2764 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2765 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2766 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2767 | "efdneg %0,%1") | |
2768 | ||
2769 | (define_insn "spe_adddf3" | |
2770 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2771 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2772 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2773 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2774 | "efdadd %0,%1,%2") | |
2775 | ||
2776 | (define_insn "spe_subdf3" | |
2777 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2778 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2779 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2780 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2781 | "efdsub %0,%1,%2") | |
2782 | ||
2783 | (define_insn "spe_muldf3" | |
2784 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2785 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2786 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2787 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2788 | "efdmul %0,%1,%2") | |
2789 | ||
2790 | (define_insn "spe_divdf3" | |
2791 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2792 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2793 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2794 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2795 | "efddiv %0,%1,%2") | |
2796 | ||
2797 | ;; Double-precision floating point instructions for IBM long double. | |
2798 | ||
2799 | (define_insn_and_split "spe_trunctfdf2_internal1" | |
2800 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r") | |
2801 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))] | |
2802 | "!TARGET_IEEEQUAD | |
2803 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2804 | "@ | |
2805 | # | |
2806 | evor %0,%1,%1" | |
2807 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
2808 | [(const_int 0)] | |
2809 | { | |
2810 | emit_note (NOTE_INSN_DELETED); | |
2811 | DONE; | |
2812 | }) | |
2813 | ||
2814 | (define_insn_and_split "spe_trunctfsf2" | |
2815 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
2816 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r"))) | |
2817 | (clobber (match_scratch:DF 2 "=r"))] | |
2818 | "!TARGET_IEEEQUAD | |
2819 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2820 | "#" | |
2821 | "&& reload_completed" | |
2822 | [(set (match_dup 2) | |
2823 | (float_truncate:DF (match_dup 1))) | |
2824 | (set (match_dup 0) | |
2825 | (float_truncate:SF (match_dup 2)))] | |
2826 | "") | |
2827 | ||
2828 | (define_insn "spe_extenddftf2" | |
2829 | [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o") | |
2830 | (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r"))) | |
2831 | (clobber (match_scratch:DF 2 "=X,X,X,&r"))] | |
2832 | "!TARGET_IEEEQUAD | |
2833 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2834 | "@ | |
2835 | evxor %L0,%L0,%L0 | |
2836 | evor %0,%1,%1\;evxor %L0,%L0,%L0 | |
2837 | evldd%X1 %0,%y1\;evxor %L0,%L0,%L0 | |
2838 | evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0" | |
2839 | [(set_attr "length" "4,8,8,12")]) | |
2840 | ||
2841 | (define_expand "spe_fix_trunctfsi2" | |
2842 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2843 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
2844 | (clobber (match_dup 2)) | |
2845 | (clobber (match_dup 3)) | |
2846 | (clobber (match_dup 4))])] | |
2847 | "!TARGET_IEEEQUAD | |
2848 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2849 | { | |
2850 | operands[2] = gen_reg_rtx (DFmode); | |
2851 | operands[3] = gen_reg_rtx (SImode); | |
2852 | operands[4] = gen_reg_rtx (SImode); | |
2853 | }) | |
2854 | ||
2855 | ; Like fix_trunc_helper, add with rounding towards 0. | |
2856 | (define_insn "spe_fix_trunctfsi2_internal" | |
2857 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2858 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r"))) | |
2859 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=r")) | |
2860 | (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r")) | |
2861 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))] | |
2862 | "!TARGET_IEEEQUAD | |
2863 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2864 | "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2" | |
2865 | [(set_attr "length" "24")]) | |
2866 | ||
2867 | (define_insn "spe_negtf2_internal" | |
2868 | [(set (match_operand:TF 0 "gpc_reg_operand" "=r") | |
2869 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))] | |
2870 | "!TARGET_IEEEQUAD | |
2871 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2872 | "* | |
2873 | { | |
2874 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2875 | return \"efdneg %L0,%L1\;efdneg %0,%1\"; | |
2876 | else | |
2877 | return \"efdneg %0,%1\;efdneg %L0,%L1\"; | |
2878 | }" | |
2879 | [(set_attr "length" "8")]) | |
2880 | ||
2881 | (define_expand "spe_abstf2_cmp" | |
2882 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
2883 | (match_operand:TF 1 "gpc_reg_operand" "f")) | |
2884 | (set (match_dup 3) (match_dup 5)) | |
2885 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
2886 | (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3) | |
2887 | (match_dup 5))] CMPDFEQ_GPR)) | |
2888 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
2889 | (label_ref (match_operand 2 "" "")) | |
2890 | (pc))) | |
2891 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
2892 | "!TARGET_IEEEQUAD | |
2893 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2894 | " | |
2895 | { | |
2896 | const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); | |
2897 | const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; | |
2898 | operands[3] = gen_reg_rtx (DFmode); | |
2899 | operands[4] = gen_reg_rtx (CCFPmode); | |
2900 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
2901 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
2902 | }") | |
2903 | ||
2904 | (define_expand "spe_abstf2_tst" | |
2905 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
2906 | (match_operand:TF 1 "gpc_reg_operand" "f")) | |
2907 | (set (match_dup 3) (match_dup 5)) | |
2908 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
2909 | (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3) | |
2910 | (match_dup 5))] TSTDFEQ_GPR)) | |
2911 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
2912 | (label_ref (match_operand 2 "" "")) | |
2913 | (pc))) | |
2914 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
2915 | "!TARGET_IEEEQUAD | |
2916 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
2917 | " | |
2918 | { | |
2919 | const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); | |
2920 | const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; | |
2921 | operands[3] = gen_reg_rtx (DFmode); | |
2922 | operands[4] = gen_reg_rtx (CCFPmode); | |
2923 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
2924 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
2925 | }") | |
2926 | ||
2927 | ;; Vector move instructions. | |
2928 | ||
2929 | (define_expand "movv2si" | |
2930 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "") | |
2931 | (match_operand:V2SI 1 "any_operand" ""))] | |
2932 | "TARGET_SPE" | |
2933 | "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") | |
2934 | ||
2935 | (define_insn "*movv2si_internal" | |
2936 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r") | |
2937 | (match_operand:V2SI 1 "input_operand" "r,m,r,W"))] | |
2938 | "TARGET_SPE | |
2939 | && (gpc_reg_operand (operands[0], V2SImode) | |
2940 | || gpc_reg_operand (operands[1], V2SImode))" | |
2941 | "* | |
2942 | { | |
2943 | switch (which_alternative) | |
2944 | { | |
2945 | case 0: return \"evstdd%X0 %1,%y0\"; | |
2946 | case 1: return \"evldd%X1 %0,%y1\"; | |
2947 | case 2: return \"evor %0,%1,%1\"; | |
2948 | case 3: return output_vec_const_move (operands); | |
2949 | default: gcc_unreachable (); | |
2950 | } | |
2951 | }" | |
2952 | [(set_attr "type" "vecload,vecstore,*,*") | |
2953 | (set_attr "length" "*,*,*,12")]) | |
2954 | ||
2955 | (define_split | |
2956 | [(set (match_operand:V2SI 0 "register_operand" "") | |
2957 | (match_operand:V2SI 1 "zero_constant" ""))] | |
2958 | "TARGET_SPE && reload_completed" | |
2959 | [(set (match_dup 0) | |
2960 | (xor:V2SI (match_dup 0) (match_dup 0)))] | |
2961 | "") | |
2962 | ||
2963 | (define_expand "movv1di" | |
2964 | [(set (match_operand:V1DI 0 "nonimmediate_operand" "") | |
2965 | (match_operand:V1DI 1 "any_operand" ""))] | |
2966 | "TARGET_SPE" | |
2967 | "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") | |
2968 | ||
2969 | (define_insn "*movv1di_internal" | |
2970 | [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r") | |
2971 | (match_operand:V1DI 1 "input_operand" "r,m,r,W"))] | |
2972 | "TARGET_SPE | |
2973 | && (gpc_reg_operand (operands[0], V1DImode) | |
2974 | || gpc_reg_operand (operands[1], V1DImode))" | |
2975 | "@ | |
2976 | evstdd%X0 %1,%y0 | |
2977 | evldd%X1 %0,%y1 | |
2978 | evor %0,%1,%1 | |
2979 | evxor %0,%0,%0" | |
2980 | [(set_attr "type" "vecload,vecstore,*,*") | |
2981 | (set_attr "length" "*,*,*,*")]) | |
2982 | ||
2983 | (define_expand "movv4hi" | |
2984 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "") | |
2985 | (match_operand:V4HI 1 "any_operand" ""))] | |
2986 | "TARGET_SPE" | |
2987 | "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") | |
2988 | ||
2989 | (define_insn "*movv4hi_internal" | |
2990 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r") | |
2991 | (match_operand:V4HI 1 "input_operand" "r,m,r,W"))] | |
2992 | "TARGET_SPE | |
2993 | && (gpc_reg_operand (operands[0], V4HImode) | |
2994 | || gpc_reg_operand (operands[1], V4HImode))" | |
2995 | "@ | |
2996 | evstdd%X0 %1,%y0 | |
2997 | evldd%X1 %0,%y1 | |
2998 | evor %0,%1,%1 | |
2999 | evxor %0,%0,%0" | |
3000 | [(set_attr "type" "vecload")]) | |
3001 | ||
3002 | (define_expand "movv2sf" | |
3003 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "") | |
3004 | (match_operand:V2SF 1 "any_operand" ""))] | |
3005 | "TARGET_SPE || TARGET_PAIRED_FLOAT" | |
3006 | "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") | |
3007 | ||
3008 | (define_insn "*movv2sf_internal" | |
3009 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r") | |
3010 | (match_operand:V2SF 1 "input_operand" "r,m,r,W"))] | |
3011 | "TARGET_SPE | |
3012 | && (gpc_reg_operand (operands[0], V2SFmode) | |
3013 | || gpc_reg_operand (operands[1], V2SFmode))" | |
3014 | "@ | |
3015 | evstdd%X0 %1,%y0 | |
3016 | evldd%X1 %0,%y1 | |
3017 | evor %0,%1,%1 | |
3018 | evxor %0,%0,%0" | |
3019 | [(set_attr "type" "vecload,vecstore,*,*") | |
3020 | (set_attr "length" "*,*,*,*")]) | |
3021 | ||
3022 | ;; End of vector move instructions. | |
3023 | ||
3024 | (define_insn "spe_evmwhssfaa" | |
3025 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3026 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3027 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) | |
3028 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3029 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3030 | "TARGET_SPE" | |
3031 | "evmwhssfaa %0,%1,%2" | |
3032 | [(set_attr "type" "veccomplex") | |
3033 | (set_attr "length" "4")]) | |
3034 | ||
3035 | (define_insn "spe_evmwhssmaa" | |
3036 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3037 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3038 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) | |
3039 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3040 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3041 | "TARGET_SPE" | |
3042 | "evmwhssmaa %0,%1,%2" | |
3043 | [(set_attr "type" "veccomplex") | |
3044 | (set_attr "length" "4")]) | |
3045 | ||
3046 | (define_insn "spe_evmwhsmfaa" | |
3047 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3048 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3049 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) | |
3050 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3051 | "TARGET_SPE" | |
3052 | "evmwhsmfaa %0,%1,%2" | |
3053 | [(set_attr "type" "veccomplex") | |
3054 | (set_attr "length" "4")]) | |
3055 | ||
3056 | (define_insn "spe_evmwhsmiaa" | |
3057 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3058 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3059 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) | |
3060 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3061 | "TARGET_SPE" | |
3062 | "evmwhsmiaa %0,%1,%2" | |
3063 | [(set_attr "type" "veccomplex") | |
3064 | (set_attr "length" "4")]) | |
3065 | ||
3066 | (define_insn "spe_evmwhusiaa" | |
3067 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3068 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3069 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) | |
3070 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3071 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3072 | "TARGET_SPE" | |
3073 | "evmwhusiaa %0,%1,%2" | |
3074 | [(set_attr "type" "veccomplex") | |
3075 | (set_attr "length" "4")]) | |
3076 | ||
3077 | (define_insn "spe_evmwhumiaa" | |
3078 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3079 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3080 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) | |
3081 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3082 | "TARGET_SPE" | |
3083 | "evmwhumiaa %0,%1,%2" | |
3084 | [(set_attr "type" "veccomplex") | |
3085 | (set_attr "length" "4")]) | |
3086 | ||
3087 | (define_insn "spe_evmwhssfan" | |
3088 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3089 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3090 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) | |
3091 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3092 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3093 | "TARGET_SPE" | |
3094 | "evmwhssfan %0,%1,%2" | |
3095 | [(set_attr "type" "veccomplex") | |
3096 | (set_attr "length" "4")]) | |
3097 | ||
3098 | (define_insn "spe_evmwhssian" | |
3099 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3100 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3101 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) | |
3102 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3103 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3104 | "TARGET_SPE" | |
3105 | "evmwhssian %0,%1,%2" | |
3106 | [(set_attr "type" "veccomplex") | |
3107 | (set_attr "length" "4")]) | |
3108 | ||
3109 | (define_insn "spe_evmwhsmfan" | |
3110 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3111 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3112 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) | |
3113 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3114 | "TARGET_SPE" | |
3115 | "evmwhsmfan %0,%1,%2" | |
3116 | [(set_attr "type" "veccomplex") | |
3117 | (set_attr "length" "4")]) | |
3118 | ||
3119 | (define_insn "spe_evmwhsmian" | |
3120 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3121 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3122 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) | |
3123 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3124 | "TARGET_SPE" | |
3125 | "evmwhsmian %0,%1,%2" | |
3126 | [(set_attr "type" "veccomplex") | |
3127 | (set_attr "length" "4")]) | |
3128 | ||
3129 | (define_insn "spe_evmwhumian" | |
3130 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3131 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3132 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) | |
3133 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3134 | "TARGET_SPE" | |
3135 | "evmwhumian %0,%1,%2" | |
3136 | [(set_attr "type" "veccomplex") | |
3137 | (set_attr "length" "4")]) | |
3138 | ||
3139 | (define_insn "spe_evmwhgssfaa" | |
3140 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3141 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3142 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) | |
3143 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3144 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3145 | "TARGET_SPE" | |
3146 | "evmwhgssfaa %0,%1,%2" | |
3147 | [(set_attr "type" "veccomplex") | |
3148 | (set_attr "length" "4")]) | |
3149 | ||
3150 | (define_insn "spe_evmwhgsmfaa" | |
3151 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3152 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3153 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) | |
3154 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3155 | "TARGET_SPE" | |
3156 | "evmwhgsmfaa %0,%1,%2" | |
3157 | [(set_attr "type" "veccomplex") | |
3158 | (set_attr "length" "4")]) | |
3159 | ||
3160 | (define_insn "spe_evmwhgsmiaa" | |
3161 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3162 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3163 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) | |
3164 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3165 | "TARGET_SPE" | |
3166 | "evmwhgsmiaa %0,%1,%2" | |
3167 | [(set_attr "type" "veccomplex") | |
3168 | (set_attr "length" "4")]) | |
3169 | ||
3170 | (define_insn "spe_evmwhgumiaa" | |
3171 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3172 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3173 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) | |
3174 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3175 | "TARGET_SPE" | |
3176 | "evmwhgumiaa %0,%1,%2" | |
3177 | [(set_attr "type" "veccomplex") | |
3178 | (set_attr "length" "4")]) | |
3179 | ||
3180 | (define_insn "spe_evmwhgssfan" | |
3181 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3182 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3183 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) | |
3184 | (clobber (reg:SI SPEFSCR_REGNO)) | |
3185 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3186 | "TARGET_SPE" | |
3187 | "evmwhgssfan %0,%1,%2" | |
3188 | [(set_attr "type" "veccomplex") | |
3189 | (set_attr "length" "4")]) | |
3190 | ||
3191 | (define_insn "spe_evmwhgsmfan" | |
3192 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3193 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3194 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) | |
3195 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3196 | "TARGET_SPE" | |
3197 | "evmwhgsmfan %0,%1,%2" | |
3198 | [(set_attr "type" "veccomplex") | |
3199 | (set_attr "length" "4")]) | |
3200 | ||
3201 | (define_insn "spe_evmwhgsmian" | |
3202 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3203 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3204 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) | |
3205 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3206 | "TARGET_SPE" | |
3207 | "evmwhgsmian %0,%1,%2" | |
3208 | [(set_attr "type" "veccomplex") | |
3209 | (set_attr "length" "4")]) | |
3210 | ||
3211 | (define_insn "spe_evmwhgumian" | |
3212 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
3213 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
3214 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) | |
3215 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
3216 | "TARGET_SPE" | |
3217 | "evmwhgumian %0,%1,%2" | |
3218 | [(set_attr "type" "veccomplex") | |
3219 | (set_attr "length" "4")]) | |
3220 | ||
3221 | (define_insn "spe_mtspefscr" | |
3222 | [(set (reg:SI SPEFSCR_REGNO) | |
3223 | (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
3224 | 722))] | |
3225 | "TARGET_SPE" | |
3226 | "mtspefscr %0" | |
3227 | [(set_attr "type" "vecsimple")]) | |
3228 | ||
3229 | (define_insn "spe_mfspefscr" | |
3230 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3231 | (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] | |
3232 | "TARGET_SPE" | |
3233 | "mfspefscr %0" | |
3234 | [(set_attr "type" "vecsimple")]) | |
3235 | ||
3236 | ;; Flip the GT bit. | |
3237 | (define_insn "e500_flip_gt_bit" | |
3238 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3239 | (unspec:CCFP | |
3240 | [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))] | |
3241 | "!TARGET_FPRS && TARGET_HARD_FLOAT" | |
3242 | "* | |
3243 | { | |
3244 | return output_e500_flip_gt_bit (operands[0], operands[1]); | |
3245 | }" | |
3246 | [(set_attr "type" "cr_logical")]) | |
3247 | ||
3248 | ;; MPC8540 single-precision FP instructions on GPRs. | |
3249 | ;; We have 2 variants for each. One for IEEE compliant math and one | |
3250 | ;; for non IEEE compliant math. | |
3251 | ||
3252 | (define_insn "cmpsfeq_gpr" | |
3253 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3254 | (unspec:CCFP | |
3255 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3256 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3257 | 1000))] | |
3258 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3259 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3260 | "efscmpeq %0,%1,%2" | |
3261 | [(set_attr "type" "veccmp")]) | |
3262 | ||
3263 | (define_insn "tstsfeq_gpr" | |
3264 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3265 | (unspec:CCFP | |
3266 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3267 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3268 | 1001))] | |
3269 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3270 | && flag_finite_math_only && !flag_trapping_math" | |
3271 | "efststeq %0,%1,%2" | |
3272 | [(set_attr "type" "veccmpsimple")]) | |
3273 | ||
3274 | (define_insn "cmpsfgt_gpr" | |
3275 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3276 | (unspec:CCFP | |
3277 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3278 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3279 | 1002))] | |
3280 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3281 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3282 | "efscmpgt %0,%1,%2" | |
3283 | [(set_attr "type" "veccmp")]) | |
3284 | ||
3285 | (define_insn "tstsfgt_gpr" | |
3286 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3287 | (unspec:CCFP | |
3288 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3289 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3290 | 1003))] | |
3291 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3292 | && flag_finite_math_only && !flag_trapping_math" | |
3293 | "efststgt %0,%1,%2" | |
3294 | [(set_attr "type" "veccmpsimple")]) | |
3295 | ||
3296 | (define_insn "cmpsflt_gpr" | |
3297 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3298 | (unspec:CCFP | |
3299 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3300 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3301 | 1004))] | |
3302 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3303 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3304 | "efscmplt %0,%1,%2" | |
3305 | [(set_attr "type" "veccmp")]) | |
3306 | ||
3307 | (define_insn "tstsflt_gpr" | |
3308 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3309 | (unspec:CCFP | |
3310 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
3311 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
3312 | 1005))] | |
3313 | "TARGET_HARD_FLOAT && !TARGET_FPRS | |
3314 | && flag_finite_math_only && !flag_trapping_math" | |
3315 | "efststlt %0,%1,%2" | |
3316 | [(set_attr "type" "veccmpsimple")]) | |
3317 | ||
3318 | ;; Same thing, but for double-precision. | |
3319 | ||
3320 | (define_insn "cmpdfeq_gpr" | |
3321 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3322 | (unspec:CCFP | |
3323 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3324 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3325 | CMPDFEQ_GPR))] | |
3326 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3327 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3328 | "efdcmpeq %0,%1,%2" | |
3329 | [(set_attr "type" "veccmp")]) | |
3330 | ||
3331 | (define_insn "tstdfeq_gpr" | |
3332 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3333 | (unspec:CCFP | |
3334 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3335 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3336 | TSTDFEQ_GPR))] | |
3337 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3338 | && flag_finite_math_only && !flag_trapping_math" | |
3339 | "efdtsteq %0,%1,%2" | |
3340 | [(set_attr "type" "veccmpsimple")]) | |
3341 | ||
3342 | (define_insn "cmpdfgt_gpr" | |
3343 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3344 | (unspec:CCFP | |
3345 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3346 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3347 | CMPDFGT_GPR))] | |
3348 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3349 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3350 | "efdcmpgt %0,%1,%2" | |
3351 | [(set_attr "type" "veccmp")]) | |
3352 | ||
3353 | (define_insn "tstdfgt_gpr" | |
3354 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3355 | (unspec:CCFP | |
3356 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3357 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3358 | TSTDFGT_GPR))] | |
3359 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3360 | && flag_finite_math_only && !flag_trapping_math" | |
3361 | "efdtstgt %0,%1,%2" | |
3362 | [(set_attr "type" "veccmpsimple")]) | |
3363 | ||
3364 | (define_insn "cmpdflt_gpr" | |
3365 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3366 | (unspec:CCFP | |
3367 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3368 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3369 | CMPDFLT_GPR))] | |
3370 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3371 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3372 | "efdcmplt %0,%1,%2" | |
3373 | [(set_attr "type" "veccmp")]) | |
3374 | ||
3375 | (define_insn "tstdflt_gpr" | |
3376 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3377 | (unspec:CCFP | |
3378 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
3379 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
3380 | TSTDFLT_GPR))] | |
3381 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
3382 | && flag_finite_math_only && !flag_trapping_math" | |
3383 | "efdtstlt %0,%1,%2" | |
3384 | [(set_attr "type" "veccmpsimple")]) | |
3385 | ||
3386 | ;; Same thing, but for IBM long double. | |
3387 | ||
3388 | (define_insn "cmptfeq_gpr" | |
3389 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3390 | (unspec:CCFP | |
3391 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3392 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3393 | CMPTFEQ_GPR))] | |
3394 | "!TARGET_IEEEQUAD | |
3395 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3396 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3397 | "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2" | |
3398 | [(set_attr "type" "veccmp") | |
3399 | (set_attr "length" "12")]) | |
3400 | ||
3401 | (define_insn "tsttfeq_gpr" | |
3402 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3403 | (unspec:CCFP | |
3404 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3405 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3406 | TSTTFEQ_GPR))] | |
3407 | "!TARGET_IEEEQUAD | |
3408 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3409 | && flag_finite_math_only && !flag_trapping_math" | |
3410 | "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2" | |
3411 | [(set_attr "type" "veccmpsimple") | |
3412 | (set_attr "length" "12")]) | |
3413 | ||
3414 | (define_insn "cmptfgt_gpr" | |
3415 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3416 | (unspec:CCFP | |
3417 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3418 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3419 | CMPTFGT_GPR))] | |
3420 | "!TARGET_IEEEQUAD | |
3421 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3422 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3423 | "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2" | |
3424 | [(set_attr "type" "veccmp") | |
3425 | (set_attr "length" "20")]) | |
3426 | ||
3427 | (define_insn "tsttfgt_gpr" | |
3428 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3429 | (unspec:CCFP | |
3430 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3431 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3432 | TSTTFGT_GPR))] | |
3433 | "!TARGET_IEEEQUAD | |
3434 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3435 | && flag_finite_math_only && !flag_trapping_math" | |
3436 | "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2" | |
3437 | [(set_attr "type" "veccmpsimple") | |
3438 | (set_attr "length" "20")]) | |
3439 | ||
3440 | (define_insn "cmptflt_gpr" | |
3441 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3442 | (unspec:CCFP | |
3443 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3444 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3445 | CMPTFLT_GPR))] | |
3446 | "!TARGET_IEEEQUAD | |
3447 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3448 | && !(flag_finite_math_only && !flag_trapping_math)" | |
3449 | "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2" | |
3450 | [(set_attr "type" "veccmp") | |
3451 | (set_attr "length" "20")]) | |
3452 | ||
3453 | (define_insn "tsttflt_gpr" | |
3454 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3455 | (unspec:CCFP | |
3456 | [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
3457 | (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
3458 | TSTTFLT_GPR))] | |
3459 | "!TARGET_IEEEQUAD | |
3460 | && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
3461 | && flag_finite_math_only && !flag_trapping_math" | |
3462 | "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2" | |
3463 | [(set_attr "type" "veccmpsimple") | |
3464 | (set_attr "length" "20")]) | |
3465 | ||
3466 | ;; Like cceq_ior_compare, but compare the GT bits. | |
3467 | (define_insn "e500_cr_ior_compare" | |
3468 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
3469 | (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y") | |
3470 | (match_operand 2 "cc_reg_operand" "y")] | |
3471 | E500_CR_IOR_COMPARE))] | |
3472 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
3473 | "cror 4*%0+gt,4*%1+gt,4*%2+gt" | |
3474 | [(set_attr "type" "cr_logical")]) | |
3475 | ||
3476 | ;; Out-of-line prologues and epilogues. | |
3477 | (define_insn "*save_gpregs_spe" | |
3478 | [(match_parallel 0 "any_parallel_operand" | |
3479 | [(clobber (reg:P LR_REGNO)) | |
3480 | (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
3481 | (use (reg:P 11)) | |
3482 | (set (match_operand:V2SI 2 "memory_operand" "=m") | |
3483 | (match_operand:V2SI 3 "gpc_reg_operand" "r"))])] | |
3484 | "TARGET_SPE_ABI" | |
3485 | "bl %z1" | |
3486 | [(set_attr "type" "branch") | |
3487 | (set_attr "length" "4")]) | |
3488 | ||
3489 | (define_insn "*restore_gpregs_spe" | |
3490 | [(match_parallel 0 "any_parallel_operand" | |
3491 | [(clobber (reg:P LR_REGNO)) | |
3492 | (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
3493 | (use (reg:P 11)) | |
3494 | (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") | |
3495 | (match_operand:V2SI 3 "memory_operand" "m"))])] | |
3496 | "TARGET_SPE_ABI" | |
3497 | "bl %z1" | |
3498 | [(set_attr "type" "branch") | |
3499 | (set_attr "length" "4")]) | |
3500 | ||
3501 | (define_insn "*return_and_restore_gpregs_spe" | |
3502 | [(match_parallel 0 "any_parallel_operand" | |
3503 | [(return) | |
3504 | (clobber (reg:P LR_REGNO)) | |
3505 | (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
3506 | (use (reg:P 11)) | |
3507 | (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") | |
3508 | (match_operand:V2SI 3 "memory_operand" "m"))])] | |
3509 | "TARGET_SPE_ABI" | |
3510 | "b %z1" | |
3511 | [(set_attr "type" "branch") | |
3512 | (set_attr "length" "4")]) |