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1 | ;; Predicate definitions for Renesas / SuperH SH. | |
2 | ;; Copyright (C) 2005-2024 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | ||
21 | ;; Returns 1 if OP is a normal arithmetic register. | |
22 | (define_predicate "arith_reg_operand" | |
23 | (match_code "subreg,reg,sign_extend") | |
24 | { | |
25 | if (register_operand (op, mode)) | |
26 | { | |
27 | int regno; | |
28 | ||
29 | if (REG_P (op)) | |
30 | regno = REGNO (op); | |
31 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) | |
32 | regno = REGNO (SUBREG_REG (op)); | |
33 | else | |
34 | return 1; | |
35 | ||
36 | return (regno != T_REG && regno != PR_REG | |
37 | && regno != FPUL_REG && regno != FPSCR_REG | |
38 | && regno != MACH_REG && regno != MACL_REG); | |
39 | } | |
40 | /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. | |
41 | We allow SImode here, as not using an FP register is just a matter of | |
42 | proper register allocation. */ | |
43 | ||
44 | #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ | |
45 | if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND | |
46 | && GET_MODE (XEXP (op, 0)) == HImode | |
47 | && REG_P (XEXP (op, 0)) | |
48 | && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG) | |
49 | return register_operand (XEXP (op, 0), VOIDmode); | |
50 | #endif | |
51 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT | |
52 | && GET_CODE (op) == SUBREG | |
53 | && GET_MODE (SUBREG_REG (op)) == DImode | |
54 | && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND | |
55 | && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode | |
56 | && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG) | |
57 | return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode); | |
58 | return 0; | |
59 | }) | |
60 | ||
61 | ;; Like above, but for DImode destinations: forbid paradoxical DImode | |
62 | ;; subregs, because this would lead to missing sign extensions when | |
63 | ;; truncating from DImode to SImode. | |
64 | (define_predicate "arith_reg_dest" | |
65 | (and (match_code "subreg,reg") | |
66 | (match_operand 0 "arith_reg_operand"))) | |
67 | ||
68 | ;; Returns true if OP is a valid source operand for an arithmetic insn. | |
69 | (define_predicate "arith_operand" | |
70 | (and (match_code "subreg,reg,const_int,truncate") | |
71 | (ior (match_operand 0 "arith_reg_operand") | |
72 | (match_test "satisfies_constraint_I08 (op)")))) | |
73 | ||
74 | ;; Likewise arith_operand but always permits const_int. | |
75 | (define_predicate "arith_or_int_operand" | |
76 | (and (match_code "subreg,reg,const_int,const_vector") | |
77 | (ior (match_operand 0 "arith_operand") | |
78 | (match_operand 0 "const_int_operand")))) | |
79 | ||
80 | ;; Returns true if OP is a valid source operand for a compare insn. | |
81 | (define_predicate "arith_reg_or_0_operand" | |
82 | (and (match_code "subreg,reg,const_int,const_vector") | |
83 | (ior (match_operand 0 "arith_reg_operand") | |
84 | (match_test "satisfies_constraint_Z (op)")))) | |
85 | ||
86 | ;; Returns true if OP is either a register or constant 0 or constant 1. | |
87 | (define_predicate "arith_reg_or_0_or_1_operand" | |
88 | (and (match_code "subreg,reg,const_int,const_vector") | |
89 | (ior (match_operand 0 "arith_reg_or_0_operand") | |
90 | (match_test "satisfies_constraint_M (op)")))) | |
91 | ||
92 | ;; Returns true if OP is a suitable constant for the minimum value of a | |
93 | ;; clips.b or clips.w insn. | |
94 | (define_predicate "clips_min_const_int" | |
95 | (and (match_code "const_int") | |
96 | (ior (match_test "INTVAL (op) == -128") | |
97 | (match_test "INTVAL (op) == -32768")))) | |
98 | ||
99 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
100 | ;; clips.b or clips.w insn. | |
101 | (define_predicate "clips_max_const_int" | |
102 | (and (match_code "const_int") | |
103 | (ior (match_test "INTVAL (op) == 127") | |
104 | (match_test "INTVAL (op) == 32767")))) | |
105 | ||
106 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
107 | ;; clipu.b or clipu.w insn. | |
108 | (define_predicate "clipu_max_const_int" | |
109 | (and (match_code "const_int") | |
110 | (ior (match_test "INTVAL (op) == 255") | |
111 | (match_test "INTVAL (op) == 65535")))) | |
112 | ||
113 | ;; Returns true if OP is a floating point register that can be used in floating | |
114 | ;; point arithmetic operations. | |
115 | (define_predicate "fp_arith_reg_operand" | |
116 | (match_code "subreg,reg") | |
117 | { | |
118 | if (register_operand (op, mode)) | |
119 | { | |
120 | int regno; | |
121 | ||
122 | if (REG_P (op)) | |
123 | regno = REGNO (op); | |
124 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) | |
125 | regno = REGNO (SUBREG_REG (op)); | |
126 | else | |
127 | return 1; | |
128 | ||
129 | return (regno >= FIRST_PSEUDO_REGISTER | |
130 | || FP_REGISTER_P (regno)); | |
131 | } | |
132 | return 0; | |
133 | }) | |
134 | ||
135 | ;; Returns true if OP is the FPSCR. | |
136 | (define_predicate "fpscr_operand" | |
137 | (and (match_code "reg") | |
138 | (match_test "REGNO (op) == FPSCR_REG"))) | |
139 | ||
140 | ;; Returns true if OP is a valid source operand for a FPSCR move insn. | |
141 | (define_predicate "fpscr_movsrc_operand" | |
142 | (match_code "reg,subreg,mem") | |
143 | { | |
144 | if (arith_reg_operand (op, mode)) | |
145 | return true; | |
146 | ||
147 | return MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC; | |
148 | }) | |
149 | ||
150 | ;; Returns true if OP is a valid destination operand for a FPSCR move insn. | |
151 | (define_predicate "fpscr_movdst_operand" | |
152 | (match_code "reg,subreg,mem") | |
153 | { | |
154 | if (arith_reg_dest (op, mode)) | |
155 | return true; | |
156 | ||
157 | return MEM_P (op) && GET_CODE (XEXP (op, 0)) == PRE_DEC; | |
158 | }) | |
159 | ||
160 | ;; Returns true if OP is an operand that is either the fpul hard reg or | |
161 | ;; a pseudo. This prevents combine from propagating function arguments | |
162 | ;; in hard regs into insns that need the operand in fpul. If it's a pseudo | |
163 | ;; reload can fix it up. | |
164 | (define_predicate "fpul_operand" | |
165 | (match_code "reg") | |
166 | { | |
167 | return REG_P (op) | |
168 | && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
169 | && GET_MODE (op) == mode; | |
170 | }) | |
171 | ||
172 | ;; Returns true if OP is a valid fpul input operand for the fsca insn. | |
173 | ;; The value in fpul is a fixed-point value and its scaling is described | |
174 | ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs | |
175 | ;; in fpul we have to permit things like | |
176 | ;; (reg:SI) | |
177 | ;; (fix:SF (float:SF (reg:SI))) | |
178 | (define_predicate "fpul_fsca_operand" | |
179 | (match_code "fix,reg") | |
180 | { | |
181 | if (fpul_operand (op, SImode)) | |
182 | return true; | |
183 | if (GET_CODE (op) == FIX && GET_MODE (op) == SImode | |
184 | && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode) | |
185 | return fpul_fsca_operand (XEXP (XEXP (op, 0), 0), | |
186 | GET_MODE (XEXP (XEXP (op, 0), 0))); | |
187 | return false; | |
188 | }) | |
189 | ||
190 | ;; Returns true if OP is a valid constant scale factor for the fsca insn. | |
191 | (define_predicate "fsca_scale_factor" | |
192 | (and (match_code "const_double") | |
193 | (match_test "op == sh_fsca_int2sf ()"))) | |
194 | ||
195 | ;; Returns true if OP is an operand that is zero extended during an operation. | |
196 | (define_predicate "general_extend_operand" | |
197 | (match_code "subreg,reg,mem,truncate") | |
198 | { | |
199 | if (reload_completed && GET_CODE (op) == TRUNCATE) | |
200 | return arith_operand (op, mode); | |
201 | ||
202 | if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))) | |
203 | return general_movsrc_operand (op, mode); | |
204 | ||
205 | return nonimmediate_operand (op, mode); | |
206 | }) | |
207 | ||
208 | ;; Returns 1 if OP is a simple register address. | |
209 | (define_predicate "simple_mem_operand" | |
210 | (and (match_code "mem") | |
211 | (match_code "reg" "0") | |
212 | (match_test "arith_reg_operand (XEXP (op, 0), SImode)"))) | |
213 | ||
214 | ;; Returns 1 if OP is a valid displacement address. | |
215 | (define_predicate "displacement_mem_operand" | |
216 | (and (match_code "mem") | |
217 | (match_code "plus" "0") | |
218 | (match_code "reg" "00") | |
219 | (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)") | |
220 | (match_test "sh_legitimate_index_p (GET_MODE (op), | |
221 | XEXP (XEXP (op, 0), 1), | |
222 | TARGET_SH2A, true)"))) | |
223 | ||
224 | ;; Returns true if OP is a displacement address that can fit into a | |
225 | ;; 16 bit (non-SH2A) memory load / store insn. | |
226 | (define_predicate "short_displacement_mem_operand" | |
227 | (and (match_code "mem") | |
228 | (match_operand 0 "displacement_mem_operand") | |
229 | (match_test "sh_disp_addr_displacement (op) | |
230 | <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))) | |
231 | ||
232 | ;; Returns true if OP is a displacement address that does not fit into | |
233 | ;; a 16 bit (non-SH2A) memory load / store insn. | |
234 | (define_predicate "long_displacement_mem_operand" | |
235 | (and (match_operand 0 "displacement_mem_operand") | |
236 | (not (match_operand 0 "short_displacement_mem_operand")))) | |
237 | ||
238 | ;; Returns true if OP is a post-increment addressing mode memory reference. | |
239 | (define_predicate "post_inc_mem" | |
240 | (and (match_code "mem") | |
241 | (match_code "post_inc" "0") | |
242 | (match_code "reg" "00"))) | |
243 | ||
244 | ;; Returns true if OP is a pre-decrement addressing mode memory reference. | |
245 | (define_predicate "pre_dec_mem" | |
246 | (and (match_code "mem") | |
247 | (match_code "pre_dec" "0") | |
248 | (match_code "reg" "00"))) | |
249 | ||
250 | ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. | |
251 | (define_predicate "zero_extend_movu_operand" | |
252 | (and (ior (match_operand 0 "displacement_mem_operand") | |
253 | (match_operand 0 "simple_mem_operand")) | |
254 | (ior (match_test "GET_MODE (op) == QImode") | |
255 | (match_test "GET_MODE (op) == HImode")))) | |
256 | ||
257 | ;; Returns 1 if OP can be source of a simple move operation. Same as | |
258 | ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as | |
259 | ;; are subregs of system registers. | |
260 | (define_predicate "general_movsrc_operand" | |
261 | (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref, | |
262 | const,const_vector") | |
263 | { | |
264 | if (t_reg_operand (op, mode)) | |
265 | return 0; | |
266 | ||
267 | if (fpscr_operand (op, mode)) | |
268 | return false; | |
269 | ||
270 | /* Disallow PC relative QImode loads, since these is no insn to do that | |
271 | and an imm8 load should be used instead. */ | |
272 | if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode) | |
273 | return false; | |
274 | ||
275 | if (MEM_P (op)) | |
276 | { | |
277 | rtx inside = XEXP (op, 0); | |
278 | ||
279 | /* Disallow mems with GBR address here. They have to go through | |
280 | separate special patterns. */ | |
281 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
282 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
283 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
284 | return 0; | |
285 | ||
286 | if (GET_CODE (inside) == CONST) | |
287 | inside = XEXP (inside, 0); | |
288 | ||
289 | if (GET_CODE (inside) == LABEL_REF) | |
290 | return 1; | |
291 | ||
292 | if (GET_CODE (inside) == PLUS | |
293 | && GET_CODE (XEXP (inside, 0)) == LABEL_REF | |
294 | && CONST_INT_P (XEXP (inside, 1))) | |
295 | return 1; | |
296 | ||
297 | /* Only post inc allowed. */ | |
298 | if (GET_CODE (inside) == PRE_DEC) | |
299 | return 0; | |
300 | } | |
301 | ||
302 | if (mode == GET_MODE (op) | |
303 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
304 | { | |
305 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); | |
306 | rtx x = XEXP (mem_rtx, 0); | |
307 | ||
308 | if (GET_CODE (x) == PLUS) | |
309 | { | |
310 | rtx y = XEXP (x, 0); | |
311 | ||
312 | if (! REG_P (y) | |
313 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))) | |
314 | return false; | |
315 | y = XEXP (x, 1); | |
316 | if (! REG_P (y) | |
317 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))) | |
318 | && ! CONST_INT_P (y)) | |
319 | return false; | |
320 | } | |
321 | ||
322 | /* LRA will try to satisfy the constraints for the memory displacements | |
323 | and thus we must not reject invalid displacements in the predicate, | |
324 | or else LRA will bail out. | |
325 | FIXME: maybe remove this check completely? */ | |
326 | if (!lra_in_progress && (mode == QImode || mode == HImode) | |
327 | && GET_CODE (x) == PLUS | |
328 | && REG_P (XEXP (x, 0)) | |
329 | && CONST_INT_P (XEXP (x, 1))) | |
330 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); | |
331 | ||
332 | /* Allow reg+reg addressing here without validating the register | |
333 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
334 | In some cases it can happen that arguments from hard regs are | |
335 | propagated directly into address expressions. In this cases reload | |
336 | will have to fix it up later. However, allow this only for native | |
337 | 1, 2 or 4 byte addresses. */ | |
338 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
339 | && GET_MODE_SIZE (mode) <= 4 | |
340 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
341 | return true; | |
342 | ||
343 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
344 | avoid matching arithmetic that operates on mems, it seems. | |
345 | On SH this leads to redundant sign extensions for QImode or HImode | |
346 | loads. Thus we mimic the behavior but allow volatile mems. */ | |
347 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
348 | MEM_ADDR_SPACE (mem_rtx))) | |
349 | return true; | |
350 | } | |
351 | ||
352 | return general_operand (op, mode); | |
353 | }) | |
354 | ||
355 | ;; Returns true if OP is a MEM that does not use displacement addressing. | |
356 | (define_predicate "movsrc_no_disp_mem_operand" | |
357 | (and (match_code "mem") | |
358 | (match_operand 0 "general_movsrc_operand") | |
359 | (match_test "satisfies_constraint_Snd (op)"))) | |
360 | ||
361 | ;; Returns 1 if OP can be a destination of a move. Same as | |
362 | ;; general_operand, but no preinc allowed. | |
363 | (define_predicate "general_movdst_operand" | |
364 | (match_code "subreg,reg,mem") | |
365 | { | |
366 | if (t_reg_operand (op, mode)) | |
367 | return 0; | |
368 | ||
369 | if (fpscr_operand (op, mode)) | |
370 | return false; | |
371 | ||
372 | if (MEM_P (op)) | |
373 | { | |
374 | rtx inside = XEXP (op, 0); | |
375 | /* Disallow mems with GBR address here. They have to go through | |
376 | separate special patterns. */ | |
377 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
378 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
379 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
380 | return 0; | |
381 | } | |
382 | ||
383 | /* Only pre dec allowed. */ | |
384 | if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC) | |
385 | return 0; | |
386 | ||
387 | if (mode == GET_MODE (op) | |
388 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
389 | { | |
390 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); | |
391 | rtx x = XEXP (mem_rtx, 0); | |
392 | ||
393 | if (GET_CODE (x) == PLUS) | |
394 | { | |
395 | rtx y = XEXP (x, 0); | |
396 | ||
397 | if (! REG_P (y) | |
398 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))) | |
399 | return false; | |
400 | y = XEXP (x, 1); | |
401 | if (! REG_P (y) | |
402 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))) | |
403 | && ! CONST_INT_P (y)) | |
404 | return false; | |
405 | } | |
406 | ||
407 | /* LRA will try to satisfy the constraints for the memory displacements | |
408 | and thus we must not reject invalid displacements in the predicate, | |
409 | or else LRA will bail out. | |
410 | FIXME: maybe remove this check completely? */ | |
411 | if (!lra_in_progress && (mode == QImode || mode == HImode) | |
412 | && GET_CODE (x) == PLUS | |
413 | && REG_P (XEXP (x, 0)) | |
414 | && CONST_INT_P (XEXP (x, 1))) | |
415 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); | |
416 | ||
417 | /* Allow reg+reg addressing here without validating the register | |
418 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
419 | In some cases it can happen that arguments from hard regs are | |
420 | propagated directly into address expressions. In this cases reload | |
421 | will have to fix it up later. However, allow this only for native | |
422 | 1, 2 or 4 byte addresses. */ | |
423 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
424 | && GET_MODE_SIZE (mode) <= 4 | |
425 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
426 | return true; | |
427 | ||
428 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
429 | avoid matching arithmetic that operates on mems, it seems. | |
430 | On SH this leads to redundant sign extensions for QImode or HImode | |
431 | stores. Thus we mimic the behavior but allow volatile mems. */ | |
432 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
433 | MEM_ADDR_SPACE (mem_rtx))) | |
434 | return true; | |
435 | } | |
436 | ||
437 | return general_operand (op, mode); | |
438 | }) | |
439 | ||
440 | ;; Returns 1 if OP is a MEM that can be source of a simple move operation. | |
441 | (define_predicate "unaligned_load_operand" | |
442 | (match_code "mem") | |
443 | { | |
444 | rtx inside; | |
445 | ||
446 | if (!MEM_P (op) || GET_MODE (op) != mode) | |
447 | return 0; | |
448 | ||
449 | inside = XEXP (op, 0); | |
450 | ||
451 | if (GET_CODE (inside) == POST_INC) | |
452 | inside = XEXP (inside, 0); | |
453 | ||
454 | if (REG_P (inside)) | |
455 | return 1; | |
456 | ||
457 | return 0; | |
458 | }) | |
459 | ||
460 | ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner | |
461 | ;; patterns. | |
462 | (define_predicate "mem_index_disp_operand" | |
463 | (match_code "mem") | |
464 | { | |
465 | rtx plus0_rtx, plus1_rtx, mult_rtx; | |
466 | ||
467 | plus0_rtx = XEXP (op, 0); | |
468 | if (GET_CODE (plus0_rtx) != PLUS) | |
469 | return 0; | |
470 | ||
471 | plus1_rtx = XEXP (plus0_rtx, 0); | |
472 | if (GET_CODE (plus1_rtx) != PLUS) | |
473 | return 0; | |
474 | if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1)))) | |
475 | return 0; | |
476 | ||
477 | mult_rtx = XEXP (plus1_rtx, 0); | |
478 | if (GET_CODE (mult_rtx) != MULT) | |
479 | return 0; | |
480 | if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0))) | |
481 | || ! CONST_INT_P (XEXP (mult_rtx, 1))) | |
482 | return 0; | |
483 | ||
484 | return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0 | |
485 | && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); | |
486 | }) | |
487 | ||
488 | ;; Returns true if OP is a valid source operand for a logical operation. | |
489 | (define_predicate "logical_operand" | |
490 | (and (match_code "subreg,reg,const_int") | |
491 | (ior (match_operand 0 "arith_reg_operand") | |
492 | (match_test "satisfies_constraint_K08 (op)")))) | |
493 | ||
494 | ;; Returns true if OP is a valid constant source operand for a logical | |
495 | ;; operations tst/and/or/xor #imm,r0. | |
496 | (define_predicate "const_logical_operand" | |
497 | (and (match_code "const_int") | |
498 | (match_test "satisfies_constraint_K08 (op)"))) | |
499 | ||
500 | ;; Like logical_operand but allows additional constant values which can be | |
501 | ;; done with zero extensions. Used for the second operand of and insns. | |
502 | (define_predicate "logical_and_operand" | |
503 | (and (match_code "subreg,reg,const_int") | |
504 | (ior (match_operand 0 "logical_operand") | |
505 | (match_test "satisfies_constraint_Jmb (op)") | |
506 | (match_test "satisfies_constraint_Jmw (op)")))) | |
507 | ||
508 | ;; Returns true if OP is a logical operator. | |
509 | (define_predicate "logical_operator" | |
510 | (match_code "and,ior,xor")) | |
511 | ||
512 | ;; Returns true if OP is a constant vector. | |
513 | (define_predicate "sh_const_vec" | |
514 | (match_code "const_vector") | |
515 | { | |
516 | for (int i = XVECLEN (op, 0) - 1; i >= 0; i--) | |
517 | if (!CONST_INT_P (XVECEXP (op, 0, i))) | |
518 | return false; | |
519 | return true; | |
520 | }) | |
521 | ||
522 | ;; Determine if OP is a constant vector matching MODE with only one | |
523 | ;; element that is not a sign extension. Two byte-sized elements | |
524 | ;; count as one. | |
525 | (define_predicate "sh_1el_vec" | |
526 | (match_code "const_vector") | |
527 | { | |
528 | /* Determine numbers of last and of least significant elements. */ | |
529 | int last = XVECLEN (op, 0) - 1; | |
530 | int least = TARGET_LITTLE_ENDIAN ? 0 : last; | |
531 | if (!CONST_INT_P (XVECEXP (op, 0, least))) | |
532 | return false; | |
533 | int sign_ix = least; | |
534 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
535 | sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1; | |
536 | if (!CONST_INT_P (XVECEXP (op, 0, sign_ix))) | |
537 | return false; | |
538 | int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
539 | rtx sign = INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1) | |
540 | ? constm1_rtx : const0_rtx; | |
541 | int i = XVECLEN (op, 0) - 1; | |
542 | do | |
543 | if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign) | |
544 | return 0; | |
545 | while (--i); | |
546 | return true; | |
547 | }) | |
548 | ||
549 | ;; Returns true if OP is a vector which is composed of one element that is | |
550 | ;; repeated. | |
551 | (define_predicate "sh_rep_vec" | |
552 | (match_code "const_vector,parallel") | |
553 | { | |
554 | int i = XVECLEN (op, 0) - 2; | |
555 | rtx x = XVECEXP (op, 0, i + 1); | |
556 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
557 | { | |
558 | rtx y = XVECEXP (op, 0, i); | |
559 | for (i -= 2; i >= 0; i -= 2) | |
560 | if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x) | |
561 | || ! rtx_equal_p (XVECEXP (op, 0, i), y)) | |
562 | return false; | |
563 | } | |
564 | else | |
565 | for (; i >= 0; i--) | |
566 | if (XVECEXP (op, 0, i) != x) | |
567 | return false; | |
568 | return true; | |
569 | }) | |
570 | ||
571 | ;; Returns true if OP is a valid shift count operand for shift operations. | |
572 | (define_predicate "shift_count_operand" | |
573 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg, | |
574 | zero_extend,sign_extend") | |
575 | { | |
576 | /* Allow T_REG as shift count for dynamic shifts, although it is not | |
577 | really possible. It will then be copied to a general purpose reg. */ | |
578 | return const_int_operand (op, mode) || arith_reg_operand (op, mode) | |
579 | || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); | |
580 | }) | |
581 | ||
582 | ;; Predicates for matching operands that are constant shift | |
583 | ;; amounts 1, 2, 8, 16. | |
584 | (define_predicate "p27_shift_count_operand" | |
585 | (and (match_code "const_int") | |
586 | (match_test "satisfies_constraint_P27 (op)"))) | |
587 | ||
588 | (define_predicate "not_p27_shift_count_operand" | |
589 | (and (match_code "const_int") | |
590 | (match_test "! satisfies_constraint_P27 (op)"))) | |
591 | ||
592 | ;; For right shifts the constant 1 is a special case because the shlr insn | |
593 | ;; clobbers the T_REG and is handled by the T_REG clobbering version of the | |
594 | ;; insn, which is also used for non-P27 shift sequences. | |
595 | (define_predicate "p27_rshift_count_operand" | |
596 | (and (match_code "const_int") | |
597 | (match_test "satisfies_constraint_P27 (op)") | |
598 | (match_test "! satisfies_constraint_M (op)"))) | |
599 | ||
600 | (define_predicate "not_p27_rshift_count_operand" | |
601 | (and (match_code "const_int") | |
602 | (ior (match_test "! satisfies_constraint_P27 (op)") | |
603 | (match_test "satisfies_constraint_M (op)")))) | |
604 | ||
605 | ;; Returns true if OP is a symbol reference. | |
606 | (define_predicate "symbol_ref_operand" | |
607 | (match_code "symbol_ref")) | |
608 | ||
609 | (define_predicate "bitwise_memory_operand" | |
610 | (match_code "mem") | |
611 | { | |
612 | if (MEM_P (op)) | |
613 | { | |
614 | if (REG_P (XEXP (op, 0))) | |
615 | return 1; | |
616 | ||
617 | if (GET_CODE (XEXP (op, 0)) == PLUS | |
618 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
619 | && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))) | |
620 | return 1; | |
621 | } | |
622 | return 0; | |
623 | }) | |
624 | ||
625 | ;; A predicate that matches any expression for which there is an | |
626 | ;; insn pattern that sets the T bit. | |
627 | (define_predicate "treg_set_expr" | |
628 | (match_test "sh_recog_treg_set_expr (op, mode)")) | |
629 | ||
630 | ;; Same as treg_set_expr but disallow constants 0 and 1 which can be loaded | |
631 | ;; into the T bit. | |
632 | (define_predicate "treg_set_expr_not_const01" | |
633 | (and (match_test "op != const0_rtx") | |
634 | (match_test "op != const1_rtx") | |
635 | (match_operand 0 "treg_set_expr"))) | |
636 | ||
637 | ;; A predicate describing the T bit register in any form. | |
638 | (define_predicate "t_reg_operand" | |
639 | (match_code "reg,subreg,sign_extend,zero_extend,ne,eq") | |
640 | { | |
641 | switch (GET_CODE (op)) | |
642 | { | |
643 | case EQ: | |
644 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
645 | && XEXP (op, 1) == const1_rtx; | |
646 | ||
647 | case NE: | |
648 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
649 | && XEXP (op, 1) == const0_rtx; | |
650 | ||
651 | case REG: | |
652 | return REGNO (op) == T_REG; | |
653 | ||
654 | case SUBREG: | |
655 | return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG; | |
656 | ||
657 | case ZERO_EXTEND: | |
658 | case SIGN_EXTEND: | |
659 | if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG) | |
660 | return true; | |
661 | return GET_CODE (XEXP (op, 0)) == SUBREG | |
662 | && REG_P (SUBREG_REG (XEXP (op, 0))) | |
663 | && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG; | |
664 | ||
665 | default: | |
666 | return 0; | |
667 | } | |
668 | }) | |
669 | ||
670 | ;; A predicate describing a negated T bit register. | |
671 | (define_predicate "negt_reg_operand" | |
672 | (match_code "subreg,xor,ne,eq") | |
673 | { | |
674 | switch (GET_CODE (op)) | |
675 | { | |
676 | case EQ: | |
677 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
678 | && XEXP (op, 1) == const0_rtx; | |
679 | ||
680 | case NE: | |
681 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
682 | && XEXP (op, 1) == const1_rtx; | |
683 | ||
684 | case XOR: | |
685 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
686 | && XEXP (op, 1) == const1_rtx; | |
687 | ||
688 | case SUBREG: | |
689 | return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))); | |
690 | ||
691 | default: | |
692 | return 0; | |
693 | } | |
694 | }) | |
695 | ||
696 | ;; Returns true if OP is an operand that can be used as the first operand in | |
697 | ;; the cstoresi4 expander pattern. | |
698 | (define_predicate "cmpsi_operand" | |
699 | (and (match_code "subreg,reg,const_int") | |
700 | (ior (match_operand:SI 0 "t_reg_operand") | |
701 | (match_operand 0 "arith_operand")))) | |
702 | ||
703 | ;; A predicate that returns true if OP is a valid construct around the T bit | |
704 | ;; that can be used as an operand for conditional branches. | |
705 | (define_predicate "cbranch_treg_value" | |
706 | (and (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend") | |
707 | (match_test "sh_eval_treg_value (op) >= 0"))) | |
708 | ||
709 | ;; Returns true if OP is arith_reg_operand or t_reg_operand. | |
710 | (define_predicate "arith_reg_or_t_reg_operand" | |
711 | (ior (match_operand 0 "arith_reg_operand") | |
712 | (match_operand 0 "t_reg_operand"))) | |
713 | ||
714 | (define_predicate "arith_reg_or_treg_set_expr" | |
715 | (ior (match_operand 0 "arith_reg_operand") | |
716 | (match_operand 0 "treg_set_expr"))) | |
717 | ||
718 | ;; A predicate describing the negated value of the T bit register shifted | |
719 | ;; left by 31. | |
720 | (define_predicate "negt_reg_shl31_operand" | |
721 | (match_code "plus,minus,if_then_else") | |
722 | { | |
723 | /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000 | |
724 | (ashift:SI (match_operand:SI 1 "t_reg_operand") | |
725 | (const_int 31))) | |
726 | */ | |
727 | if (GET_CODE (op) == MINUS && satisfies_constraint_Jhb (XEXP (op, 0)) | |
728 | && GET_CODE (XEXP (op, 1)) == ASHIFT | |
729 | && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode) | |
730 | && CONST_INT_P (XEXP (XEXP (op, 1), 1)) | |
731 | && INTVAL (XEXP (XEXP (op, 1), 1)) == 31) | |
732 | return true; | |
733 | ||
734 | /* (plus:SI (ashift:SI (match_operand:SI 1 "t_reg_operand") | |
735 | (const_int 31)) | |
736 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
737 | */ | |
738 | if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1)) | |
739 | && GET_CODE (XEXP (op, 0)) == ASHIFT | |
740 | && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode) | |
741 | && CONST_INT_P (XEXP (XEXP (op, 0), 1)) | |
742 | && INTVAL (XEXP (XEXP (op, 0), 1)) == 31) | |
743 | return true; | |
744 | ||
745 | /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand") | |
746 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
747 | (const_int -2147483648)) | |
748 | */ | |
749 | if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1)) | |
750 | && GET_CODE (XEXP (op, 0)) == MULT | |
751 | && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode) | |
752 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1))) | |
753 | return true; | |
754 | ||
755 | /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000 | |
756 | (mult:SI (match_operand:SI 1 "t_reg_operand") | |
757 | (const_int -2147483648))) | |
758 | */ | |
759 | if (GET_CODE (op) == MINUS | |
760 | && satisfies_constraint_Jhb (XEXP (op, 0)) | |
761 | && GET_CODE (XEXP (op, 1)) == MULT | |
762 | && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode) | |
763 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1))) | |
764 | return true; | |
765 | ||
766 | /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand") | |
767 | (const_int 0) | |
768 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
769 | */ | |
770 | if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode) | |
771 | && satisfies_constraint_Z (XEXP (op, 1)) | |
772 | && satisfies_constraint_Jhb (XEXP (op, 2))) | |
773 | return true; | |
774 | ||
775 | return false; | |
776 | }) | |
777 | ||
778 | ;; A predicate that determines whether a given constant is a valid | |
779 | ;; displacement for a GBR load/store of the specified mode. | |
780 | (define_predicate "gbr_displacement" | |
781 | (match_code "const_int") | |
782 | { | |
783 | const int mode_sz = GET_MODE_SIZE (mode); | |
784 | const int move_sz = mode_sz > GET_MODE_SIZE (SImode) | |
785 | ? GET_MODE_SIZE (SImode) | |
786 | : mode_sz; | |
787 | int max_disp = 255 * move_sz; | |
788 | if (mode_sz > move_sz) | |
789 | max_disp -= mode_sz - move_sz; | |
790 | ||
791 | return INTVAL (op) >= 0 && INTVAL (op) <= max_disp; | |
792 | }) | |
793 | ||
794 | ;; A predicate that determines whether OP is a valid GBR addressing mode | |
795 | ;; memory reference. | |
796 | (define_predicate "gbr_address_mem" | |
797 | (match_code "mem") | |
798 | { | |
799 | rtx addr = XEXP (op, 0); | |
800 | ||
801 | if (REG_P (addr) && REGNO (addr) == GBR_REG) | |
802 | return true; | |
803 | if (GET_CODE (addr) == PLUS | |
804 | && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG | |
805 | && gbr_displacement (XEXP (addr, 1), mode)) | |
806 | return true; | |
807 | ||
808 | return false; | |
809 | }) |