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1 | /* Target instruction definitions. | |
2 | Copyright (C) 2015 Free Software Foundation, Inc. | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify it | |
5 | under the terms of the GNU General Public License as published by the | |
6 | Free Software Foundation; either version 3, or (at your option) any | |
7 | later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; see the file COPYING3. If not see | |
16 | <http://www.gnu.org/licenses/>. */ | |
17 | ||
18 | /* This file has one entry for each public pattern name that the target | |
19 | can provide. It is only used if no distinction between operand modes | |
20 | is necessary. If separate patterns are needed for different modes | |
21 | (so as to distinguish addition of QImode values from addition of | |
22 | HImode values, for example) then an optab should be used instead. | |
23 | ||
24 | Each entry has the form: | |
25 | ||
26 | DEF_TARGET_INSN (name, prototype) | |
27 | ||
28 | where NAME is the name of the pattern and PROTOTYPE is its C prototype. | |
29 | The prototype should use parameter names of the form "x0", "x1", etc. | |
30 | Patterns that take no operands should have a prototype "(void)". | |
31 | ||
32 | Instructions should be documented in md.texi rather than here. */ | |
33 | DEF_TARGET_INSN (builtin_longjmp, (rtx x0)) | |
34 | DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0)) | |
35 | DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0)) | |
36 | DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1)) | |
37 | DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)) | |
38 | DEF_TARGET_INSN (epilogue, (void)) | |
39 | DEF_TARGET_INSN (exception_receiver, (void)) | |
40 | DEF_TARGET_INSN (jump, (rtx x0)) | |
41 | DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2)) | |
42 | DEF_TARGET_INSN (mem_signal_fence, (rtx x0)) | |
43 | DEF_TARGET_INSN (mem_thread_fence, (rtx x0)) | |
44 | DEF_TARGET_INSN (memory_barrier, (void)) | |
45 | DEF_TARGET_INSN (nonlocal_goto, (rtx x0, rtx x1, rtx x2, rtx x3)) | |
46 | DEF_TARGET_INSN (nonlocal_goto_receiver, (void)) | |
47 | DEF_TARGET_INSN (prefetch, (rtx x0, rtx x1, rtx x2)) | |
48 | DEF_TARGET_INSN (prologue, (void)) | |
49 | DEF_TARGET_INSN (return, (void)) | |
50 | DEF_TARGET_INSN (sibcall_epilogue, (void)) | |
51 | DEF_TARGET_INSN (simple_return, (void)) | |
52 | DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2)) | |
53 | DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1)) | |
54 | DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2)) | |
55 | DEF_TARGET_INSN (untyped_return, (rtx x0, rtx x1)) |