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1 | /* | |
2 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * config for XPedite1000 from XES Inc. | |
9 | * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> | |
10 | * (C) Copyright 2003 Sandburst Corporation | |
11 | * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
17 | /* High Level Configuration Options */ | |
18 | #define CONFIG_XPEDITE1000 1 | |
19 | #define CONFIG_SYS_BOARD_NAME "XPedite1000" | |
20 | #define CONFIG_SYS_FORM_PMC 1 | |
21 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
22 | #define CONFIG_440 1 | |
23 | #define CONFIG_440GX 1 /* 440 GX */ | |
24 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
25 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
26 | ||
27 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
28 | ||
29 | /* | |
30 | * DDR config | |
31 | */ | |
32 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
33 | #define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ | |
34 | #define CONFIG_VERY_BIG_RAM 1 | |
35 | ||
36 | /* | |
37 | * Base addresses -- Note these are effective addresses where the | |
38 | * actual resources get mapped (not physical addresses) | |
39 | */ | |
40 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
41 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ | |
42 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
43 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
44 | #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ | |
45 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
46 | #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) | |
47 | #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) | |
48 | ||
49 | /* | |
50 | * Diagnostics | |
51 | */ | |
52 | #define CONFIG_SYS_ALT_MEMTEST | |
53 | #define CONFIG_SYS_MEMTEST_START 0x0400000 | |
54 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 | |
55 | ||
56 | /* POST support */ | |
57 | #define CONFIG_POST (CONFIG_SYS_POST_RTC | \ | |
58 | CONFIG_SYS_POST_I2C) | |
59 | ||
60 | /* | |
61 | * LED support | |
62 | */ | |
63 | #define USR_LED0 0x00000080 | |
64 | #define USR_LED1 0x00000100 | |
65 | #define USR_LED2 0x00000200 | |
66 | #define USR_LED3 0x00000400 | |
67 | ||
68 | #ifndef __ASSEMBLY__ | |
69 | extern unsigned long in32(unsigned int); | |
70 | extern void out32(unsigned int, unsigned long); | |
71 | ||
72 | #define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0)) | |
73 | #define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1)) | |
74 | #define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2)) | |
75 | #define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3)) | |
76 | ||
77 | #define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0)) | |
78 | #define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1)) | |
79 | #define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2)) | |
80 | #define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) | |
81 | #endif | |
82 | ||
83 | /* | |
84 | * Use internal SRAM for initial stack | |
85 | */ | |
86 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
87 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
88 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
89 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ | |
90 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
91 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
92 | ||
93 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
94 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
95 | ||
96 | /* | |
97 | * Serial Port | |
98 | */ | |
99 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
100 | #define CONFIG_SYS_NS16550 | |
101 | #define CONFIG_SYS_NS16550_SERIAL | |
102 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
103 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
104 | ||
105 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
106 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} | |
107 | #define CONFIG_BAUDRATE 115200 | |
108 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
109 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
110 | ||
111 | /* | |
112 | * Use the HUSH parser | |
113 | */ | |
114 | #define CONFIG_SYS_HUSH_PARSER | |
115 | ||
116 | /* | |
117 | * NOR flash configuration | |
118 | */ | |
119 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 | |
120 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } | |
121 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
122 | #define CONFIG_FLASH_CFI_DRIVER | |
123 | #define CONFIG_SYS_FLASH_CFI | |
124 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
125 | #define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ | |
126 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
127 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
128 | ||
129 | /* | |
130 | * I2C | |
131 | */ | |
132 | #define CONFIG_SYS_I2C | |
133 | #define CONFIG_SYS_I2C_PPC4XX | |
134 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
135 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
136 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7f | |
137 | ||
138 | /* I2C EEPROM */ | |
139 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
140 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
141 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
142 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
143 | ||
144 | /* I2C RTC: STMicro M41T00 */ | |
145 | #define CONFIG_RTC_M41T11 1 | |
146 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
147 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
148 | ||
149 | /* | |
150 | * PCI | |
151 | */ | |
152 | /* General PCI */ | |
153 | #define CONFIG_PCI /* include pci support */ | |
154 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ | |
155 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
156 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
157 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ | |
158 | ||
159 | /* Board-specific PCI */ | |
160 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ | |
161 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
162 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
163 | #define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ | |
164 | ||
165 | /* | |
166 | * Networking options | |
167 | */ | |
168 | #define CONFIG_PPC4xx_EMAC | |
169 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
170 | #define CONFIG_MII 1 /* MII PHY management */ | |
171 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
172 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
173 | #define CONFIG_ETHPRIME "ppc_4xx_eth2" | |
174 | #define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ | |
175 | #define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ | |
176 | #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ | |
177 | #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ | |
178 | #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ | |
179 | ||
180 | /* BOOTP options */ | |
181 | #define CONFIG_BOOTP_BOOTFILESIZE | |
182 | #define CONFIG_BOOTP_BOOTPATH | |
183 | #define CONFIG_BOOTP_GATEWAY | |
184 | #define CONFIG_BOOTP_HOSTNAME | |
185 | ||
186 | /* | |
187 | * Command configuration | |
188 | */ | |
189 | #include <config_cmd_default.h> | |
190 | ||
191 | #define CONFIG_CMD_ASKENV | |
192 | #define CONFIG_CMD_DATE | |
193 | #define CONFIG_CMD_DHCP | |
194 | #define CONFIG_CMD_EEPROM | |
195 | #define CONFIG_CMD_ELF | |
196 | #define CONFIG_CMD_FLASH | |
197 | #define CONFIG_CMD_I2C | |
198 | #define CONFIG_CMD_IRQ | |
199 | #define CONFIG_CMD_JFFS2 | |
200 | #define CONFIG_CMD_MII | |
201 | #define CONFIG_CMD_NET | |
202 | #define CONFIG_CMD_PCI | |
203 | #define CONFIG_CMD_PING | |
204 | #define CONFIG_CMD_SAVEENV | |
205 | #define CONFIG_CMD_SNTP | |
206 | ||
207 | /* | |
208 | * Miscellaneous configurable options | |
209 | */ | |
210 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
211 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
212 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
213 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
214 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
215 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
216 | #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ | |
217 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
218 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
219 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
220 | #define CONFIG_FIT 1 | |
221 | #define CONFIG_FIT_VERBOSE 1 | |
222 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
223 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
224 | ||
225 | /* | |
226 | * For booting Linux, the board info and command line data | |
227 | * have to be in the first 8 MB of memory, since this is | |
228 | * the maximum mapped by the Linux kernel during initialization. | |
229 | */ | |
230 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
231 | ||
232 | /* | |
233 | * Environment Configuration | |
234 | */ | |
235 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
236 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
237 | #define CONFIG_ENV_SIZE 0x8000 | |
238 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
239 | ||
240 | /* | |
241 | * Flash memory map: | |
242 | * fff80000 - ffffffff U-Boot (512 KB) | |
243 | * fff40000 - fff7ffff U-Boot Environment (256 KB) | |
244 | * fff00000 - fff3ffff FDT (256KB) | |
245 | * ffc00000 - ffefffff OS image (3MB) | |
246 | * ff000000 - ffbfffff OS Use/Filesystem (12MB) | |
247 | */ | |
248 | ||
249 | #define CONFIG_UBOOT_ENV_ADDR __stringify(CONFIG_SYS_TEXT_BASE) | |
250 | #define CONFIG_FDT_ENV_ADDR __stringify(0xfff00000) | |
251 | #define CONFIG_OS_ENV_ADDR __stringify(0xffc00000) | |
252 | ||
253 | #define CONFIG_PROG_UBOOT \ | |
254 | "$download_cmd $loadaddr $ubootfile; " \ | |
255 | "if test $? -eq 0; then " \ | |
256 | "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \ | |
257 | "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \ | |
258 | "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \ | |
259 | "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \ | |
260 | "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \ | |
261 | "if test $? -ne 0; then " \ | |
262 | "echo PROGRAM FAILED; " \ | |
263 | "else; " \ | |
264 | "echo PROGRAM SUCCEEDED; " \ | |
265 | "fi; " \ | |
266 | "else; " \ | |
267 | "echo DOWNLOAD FAILED; " \ | |
268 | "fi;" | |
269 | ||
270 | #define CONFIG_BOOT_OS_NET \ | |
271 | "$download_cmd $osaddr $osfile; " \ | |
272 | "if test $? -eq 0; then " \ | |
273 | "if test -n $fdtaddr; then " \ | |
274 | "$download_cmd $fdtaddr $fdtfile; " \ | |
275 | "if test $? -eq 0; then " \ | |
276 | "bootm $osaddr - $fdtaddr; " \ | |
277 | "else; " \ | |
278 | "echo FDT DOWNLOAD FAILED; " \ | |
279 | "fi; " \ | |
280 | "else; " \ | |
281 | "bootm $osaddr; " \ | |
282 | "fi; " \ | |
283 | "else; " \ | |
284 | "echo OS DOWNLOAD FAILED; " \ | |
285 | "fi;" | |
286 | ||
287 | #define CONFIG_PROG_OS \ | |
288 | "$download_cmd $osaddr $osfile; " \ | |
289 | "if test $? -eq 0; then " \ | |
290 | "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \ | |
291 | "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ | |
292 | "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ | |
293 | "if test $? -ne 0; then " \ | |
294 | "echo OS PROGRAM FAILED; " \ | |
295 | "else; " \ | |
296 | "echo OS PROGRAM SUCCEEDED; " \ | |
297 | "fi; " \ | |
298 | "else; " \ | |
299 | "echo OS DOWNLOAD FAILED; " \ | |
300 | "fi;" | |
301 | ||
302 | #define CONFIG_PROG_FDT \ | |
303 | "$download_cmd $fdtaddr $fdtfile; " \ | |
304 | "if test $? -eq 0; then " \ | |
305 | "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \ | |
306 | "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ | |
307 | "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ | |
308 | "if test $? -ne 0; then " \ | |
309 | "echo FDT PROGRAM FAILED; " \ | |
310 | "else; " \ | |
311 | "echo FDT PROGRAM SUCCEEDED; " \ | |
312 | "fi; " \ | |
313 | "else; " \ | |
314 | "echo FDT DOWNLOAD FAILED; " \ | |
315 | "fi;" | |
316 | ||
317 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
318 | "autoload=yes\0" \ | |
319 | "download_cmd=tftp\0" \ | |
320 | "console_args=console=ttyS0,115200\0" \ | |
321 | "root_args=root=/dev/nfs rw\0" \ | |
322 | "misc_args=ip=on\0" \ | |
323 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
324 | "bootfile=/home/user/file\0" \ | |
325 | "osfile=/home/user/board.uImage\0" \ | |
326 | "fdtfile=/home/user/board.dtb\0" \ | |
327 | "ubootfile=/home/user/u-boot.bin\0" \ | |
328 | "fdtaddr=c00000\0" \ | |
329 | "osaddr=0x1000000\0" \ | |
330 | "loadaddr=0x1000000\0" \ | |
331 | "prog_uboot="CONFIG_PROG_UBOOT"\0" \ | |
332 | "prog_os="CONFIG_PROG_OS"\0" \ | |
333 | "prog_fdt="CONFIG_PROG_FDT"\0" \ | |
334 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
335 | "bootcmd_flash=run set_bootargs; " \ | |
336 | "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \ | |
337 | "bootcmd=run bootcmd_flash\0" | |
338 | #endif /* __CONFIG_H */ |