3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
31 #include <asm/processor.h>
34 #if defined(CONFIG_CMD_NET)
41 * Breath some life into the CPU...
43 * Set up the memory map,
44 * initialize a bunch of registers,
45 * initialize the UPM's
49 volatile scm1_t
*scm1
= (scm1_t
*) MMAP_SCM1
;
50 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
51 volatile fbcs_t
*fbcs
= (fbcs_t
*) MMAP_FBCS
;
53 scm1
->mpr
= 0x77777777;
64 GPIO_PAR_BE_BE3_BE3
| GPIO_PAR_BE_BE2_BE2
| GPIO_PAR_BE_BE1_BE1
|
67 GPIO_PAR_FBCTL_OE
| GPIO_PAR_FBCTL_TA_TA
| GPIO_PAR_FBCTL_RW_RW
|
70 #if !defined(CONFIG_CF_SBF)
71 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
72 fbcs
->csar0
= CONFIG_SYS_CS0_BASE
;
73 fbcs
->cscr0
= CONFIG_SYS_CS0_CTRL
;
74 fbcs
->csmr0
= CONFIG_SYS_CS0_MASK
;
78 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
79 /* Latch chipselect */
80 fbcs
->csar1
= CONFIG_SYS_CS1_BASE
;
81 fbcs
->cscr1
= CONFIG_SYS_CS1_CTRL
;
82 fbcs
->csmr1
= CONFIG_SYS_CS1_MASK
;
85 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
86 fbcs
->csar2
= CONFIG_SYS_CS2_BASE
;
87 fbcs
->cscr2
= CONFIG_SYS_CS2_CTRL
;
88 fbcs
->csmr2
= CONFIG_SYS_CS2_MASK
;
91 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
92 fbcs
->csar3
= CONFIG_SYS_CS3_BASE
;
93 fbcs
->cscr3
= CONFIG_SYS_CS3_CTRL
;
94 fbcs
->csmr3
= CONFIG_SYS_CS3_MASK
;
97 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
98 fbcs
->csar4
= CONFIG_SYS_CS4_BASE
;
99 fbcs
->cscr4
= CONFIG_SYS_CS4_CTRL
;
100 fbcs
->csmr4
= CONFIG_SYS_CS4_MASK
;
103 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
104 fbcs
->csar5
= CONFIG_SYS_CS5_BASE
;
105 fbcs
->cscr5
= CONFIG_SYS_CS5_CTRL
;
106 fbcs
->csmr5
= CONFIG_SYS_CS5_MASK
;
110 * now the flash base address is no longer at 0 (Newer ColdFire family
111 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
112 * also move to the new location.
114 if (CONFIG_SYS_CS0_BASE
!= 0)
115 setvbr(CONFIG_SYS_CS0_BASE
);
117 #ifdef CONFIG_FSL_I2C
118 gpio
->par_feci2c
= GPIO_PAR_FECI2C_SCL_SCL
| GPIO_PAR_FECI2C_SDA_SDA
;
125 * initialize higher level parts of CPU like timers
130 volatile rtc_t
*rtc
= (volatile rtc_t
*)(CONFIG_SYS_MCFRTC_BASE
);
131 volatile rtcex_t
*rtcex
= (volatile rtcex_t
*)&rtc
->extended
;
133 rtcex
->gocu
= (CONFIG_SYS_RTC_OSCILLATOR
>> 16) & 0xFFFF;
134 rtcex
->gocl
= CONFIG_SYS_RTC_OSCILLATOR
& 0xFFFF;
140 void uart_port_conf(int port
)
142 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
148 ~(GPIO_PAR_UART_U0TXD_U0TXD
| GPIO_PAR_UART_U0RXD_U0RXD
);
150 (GPIO_PAR_UART_U0TXD_U0TXD
| GPIO_PAR_UART_U0RXD_U0RXD
);
153 #ifdef CONFIG_SYS_UART1_PRI_GPIO
155 ~(GPIO_PAR_UART_U1TXD_U1TXD
| GPIO_PAR_UART_U1RXD_U1RXD
);
157 (GPIO_PAR_UART_U1TXD_U1TXD
| GPIO_PAR_UART_U1RXD_U1RXD
);
158 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
160 (GPIO_PAR_SSI_SRXD_UNMASK
| GPIO_PAR_SSI_STXD_UNMASK
);
162 (GPIO_PAR_SSI_SRXD_U1RXD
| GPIO_PAR_SSI_STXD_U1TXD
);
166 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
168 (GPIO_PAR_TIMER_T3IN_UNMASK
| GPIO_PAR_TIMER_T2IN_UNMASK
);
170 (GPIO_PAR_TIMER_T3IN_U2RXD
| GPIO_PAR_TIMER_T2IN_U2TXD
);
171 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
173 (GPIO_PAR_FECI2C_SCL_UNMASK
| GPIO_PAR_FECI2C_SDA_UNMASK
);
175 (GPIO_PAR_FECI2C_SCL_U2TXD
| GPIO_PAR_FECI2C_SDA_U2RXD
);
181 #if defined(CONFIG_CMD_NET)
182 int fecpin_setclear(struct eth_device
*dev
, int setclear
)
184 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
185 struct fec_info_s
*info
= (struct fec_info_s
*)dev
->priv
;
188 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
189 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
191 (GPIO_PAR_FECI2C_MDC0_MDC0
|
192 GPIO_PAR_FECI2C_MDIO0_MDIO0
);
195 (GPIO_PAR_FECI2C_MDC1_MDC1
|
196 GPIO_PAR_FECI2C_MDIO1_MDIO1
);
199 (GPIO_PAR_FECI2C_MDC0_MDC0
| GPIO_PAR_FECI2C_MDIO0_MDIO0
);
202 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
203 gpio
->par_fec
|= GPIO_PAR_FEC_FEC0_RMII_GPIO
;
205 gpio
->par_fec
|= GPIO_PAR_FEC_FEC1_RMII_ATA
;
208 ~(GPIO_PAR_FECI2C_MDC0_MDC0
| GPIO_PAR_FECI2C_MDIO0_MDIO0
);
210 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
211 gpio
->par_fec
&= GPIO_PAR_FEC_FEC0_UNMASK
;
213 gpio
->par_fec
&= GPIO_PAR_FEC_FEC1_UNMASK
;
219 #ifdef CONFIG_CF_DSPI
220 void cfspi_port_conf(void)
222 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
224 gpio
->par_dspi
= GPIO_PAR_DSPI_SIN_SIN
| GPIO_PAR_DSPI_SOUT_SOUT
|
225 GPIO_PAR_DSPI_SCK_SCK
;
228 int cfspi_claim_bus(uint bus
, uint cs
)
230 volatile dspi_t
*dspi
= (dspi_t
*) MMAP_DSPI
;
231 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
233 if ((dspi
->sr
& DSPI_SR_TXRXS
) != DSPI_SR_TXRXS
)
236 /* Clear FIFO and resume transfer */
237 dspi
->mcr
&= ~(DSPI_MCR_CTXF
| DSPI_MCR_CRXF
);
241 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS0_PCS0
;
242 gpio
->par_dspi
|= GPIO_PAR_DSPI_PCS0_PCS0
;
245 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS1_PCS1
;
246 gpio
->par_dspi
|= GPIO_PAR_DSPI_PCS1_PCS1
;
249 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS2_PCS2
;
250 gpio
->par_dspi
|= GPIO_PAR_DSPI_PCS2_PCS2
;
253 gpio
->par_dma
&= GPIO_PAR_DMA_DACK0_UNMASK
;
254 gpio
->par_dma
|= GPIO_PAR_DMA_DACK0_PCS3
;
257 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS5_PCS5
;
258 gpio
->par_dspi
|= GPIO_PAR_DSPI_PCS5_PCS5
;
265 void cfspi_release_bus(uint bus
, uint cs
)
267 volatile dspi_t
*dspi
= (dspi_t
*) MMAP_DSPI
;
268 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
270 dspi
->mcr
&= ~(DSPI_MCR_CTXF
| DSPI_MCR_CRXF
); /* Clear FIFO */
274 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS0_PCS0
;
277 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS1_PCS1
;
280 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS2_PCS2
;
283 gpio
->par_dma
&= GPIO_PAR_DMA_DACK0_UNMASK
;
286 gpio
->par_dspi
&= ~GPIO_PAR_DSPI_PCS5_PCS5
;