3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/ppc440.h>
24 #include <fdt_support.h>
26 #include <asm/processor.h>
29 #include <asm/4xx_pcie.h>
30 #include <asm/ppc4xx-gpio.h>
31 #include <asm/errno.h>
33 extern flash_info_t flash_info
[CONFIG_SYS_MAX_FLASH_BANKS
]; /* info for FLASH chips */
35 DECLARE_GLOBAL_DATA_PTR
;
49 #define BOARD_CANYONLANDS_PCIE 1
50 #define BOARD_CANYONLANDS_SATA 2
51 #define BOARD_GLACIER 3
52 #define BOARD_ARCHES 4
55 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
56 * board specific values.
58 #if defined(CONFIG_ARCHES)
59 u32
ddr_wrdtr(u32 default_val
) {
60 return (SDRAM_WRDTR_LLWP_1_CYC
| SDRAM_WRDTR_WTR_0_DEG
| 0x823);
63 u32
ddr_wrdtr(u32 default_val
) {
64 return (SDRAM_WRDTR_LLWP_1_CYC
| SDRAM_WRDTR_WTR_180_DEG_ADV
| 0x823);
67 u32
ddr_clktr(u32 default_val
) {
68 return (SDRAM_CLKTR_CLKP_90_DEG_ADV
);
72 #if defined(CONFIG_ARCHES)
74 * FPGA read/write helper macros
76 static inline int board_fpga_read(int offset
)
80 data
= in_8((void *)(CONFIG_SYS_FPGA_BASE
+ offset
));
85 static inline void board_fpga_write(int offset
, int data
)
87 out_8((void *)(CONFIG_SYS_FPGA_BASE
+ offset
), data
);
91 * CPLD read/write helper macros
93 static inline int board_cpld_read(int offset
)
97 out_8((void *)(CONFIG_SYS_CPLD_ADDR
), offset
);
98 data
= in_8((void *)(CONFIG_SYS_CPLD_DATA
));
103 static inline void board_cpld_write(int offset
, int data
)
105 out_8((void *)(CONFIG_SYS_CPLD_ADDR
), offset
);
106 out_8((void *)(CONFIG_SYS_CPLD_DATA
), data
);
109 static int pvr_460ex(void)
113 if ((pvr
== PVR_460EX_RA
) || (pvr
== PVR_460EX_SE_RA
) ||
114 (pvr
== PVR_460EX_RB
))
119 #endif /* defined(CONFIG_ARCHES) */
121 int board_early_init_f(void)
123 #if !defined(CONFIG_ARCHES)
125 struct board_bcsr
*bcsr_data
=
126 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
131 * Setup the interrupt controller polarities, triggers, etc.
133 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
134 mtdcr(UIC0ER
, 0x00000000); /* disable all */
135 mtdcr(UIC0CR
, 0x00000005); /* ATI & UIC1 crit are critical */
136 mtdcr(UIC0PR
, 0xffffffff); /* per ref-board manual */
137 mtdcr(UIC0TR
, 0x00000000); /* per ref-board manual */
138 mtdcr(UIC0VR
, 0x00000000); /* int31 highest, base=0x000 */
139 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
141 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
142 mtdcr(UIC1ER
, 0x00000000); /* disable all */
143 mtdcr(UIC1CR
, 0x00000000); /* all non-critical */
144 mtdcr(UIC1PR
, 0xffffffff); /* per ref-board manual */
145 mtdcr(UIC1TR
, 0x00000000); /* per ref-board manual */
146 mtdcr(UIC1VR
, 0x00000000); /* int31 highest, base=0x000 */
147 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
149 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
150 mtdcr(UIC2ER
, 0x00000000); /* disable all */
151 mtdcr(UIC2CR
, 0x00000000); /* all non-critical */
152 mtdcr(UIC2PR
, 0xffffffff); /* per ref-board manual */
153 mtdcr(UIC2TR
, 0x00000000); /* per ref-board manual */
154 mtdcr(UIC2VR
, 0x00000000); /* int31 highest, base=0x000 */
155 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
157 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
158 mtdcr(UIC3ER
, 0x00000000); /* disable all */
159 mtdcr(UIC3CR
, 0x00000000); /* all non-critical */
160 mtdcr(UIC3PR
, 0xffffffff); /* per ref-board manual */
161 mtdcr(UIC3TR
, 0x00000000); /* per ref-board manual */
162 mtdcr(UIC3VR
, 0x00000000); /* int31 highest, base=0x000 */
163 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
165 #if !defined(CONFIG_ARCHES)
166 /* SDR Setting - enable NDFC */
167 mfsdr(SDR0_CUST0
, sdr0_cust0
);
168 sdr0_cust0
= SDR0_CUST0_MUX_NDFC_SEL
|
169 SDR0_CUST0_NDFC_ENABLE
|
170 SDR0_CUST0_NDFC_BW_8_BIT
|
171 SDR0_CUST0_NDFC_ARE_MASK
|
172 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
173 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS
));
174 mtsdr(SDR0_CUST0
, sdr0_cust0
);
178 * Configure PFC (Pin Function Control) registers
181 mtsdr(SDR0_PFC1
, 0x00040000);
183 /* Enable PCI host functionality in SDR0_PCI0 */
184 mtsdr(SDR0_PCI0
, 0xe0000000);
186 #if !defined(CONFIG_ARCHES)
187 /* Enable ethernet and take out of reset */
188 out_8(&bcsr_data
->eth_ctrl
, 0) ;
190 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
191 out_8(&bcsr_data
->flash_ctrl
, 0) ;
192 mtsdr(SDR0_SRST1
, 0); /* Pull AHB out of reset default=1 */
194 /* Setup PLB4-AHB bridge based on the system address map */
195 mtdcr(AHB_TOP
, 0x8000004B);
196 mtdcr(AHB_BOT
, 0x8000004B);
200 * Configure USB-STP pins as alternate and not GPIO
201 * It seems to be neccessary to configure the STP pins as GPIO
202 * input at powerup (perhaps while USB reset is asserted). So
203 * we configure those pins to their "real" function now.
205 gpio_config(16, GPIO_OUT
, GPIO_ALT1
, GPIO_OUT_1
);
206 gpio_config(19, GPIO_OUT
, GPIO_ALT1
, GPIO_OUT_1
);
213 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
214 int usb_board_init(void)
216 struct board_bcsr
*bcsr_data
=
217 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
220 /* Enable USB host & USB-OTG */
221 val
= in_8(&bcsr_data
->usb_ctrl
);
222 val
&= ~(BCSR_USBCTRL_OTG_RST
| BCSR_USBCTRL_HOST_RST
);
223 out_8(&bcsr_data
->usb_ctrl
, val
);
228 int usb_board_stop(void)
230 struct board_bcsr
*bcsr_data
=
231 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
234 /* Disable USB host & USB-OTG */
235 val
= in_8(&bcsr_data
->usb_ctrl
);
236 val
|= (BCSR_USBCTRL_OTG_RST
| BCSR_USBCTRL_HOST_RST
);
237 out_8(&bcsr_data
->usb_ctrl
, val
);
242 int usb_board_init_fail(void)
244 return usb_board_stop();
246 #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
248 #if !defined(CONFIG_ARCHES)
249 static void canyonlands_sata_init(int board_type
)
253 if (board_type
== BOARD_CANYONLANDS_SATA
) {
254 /* Put SATA in reset */
255 SDR_WRITE(SDR0_SRST1
, 0x00020001);
257 /* Set the phy for SATA, not PCI-E port 0 */
258 reg
= SDR_READ(PESDR0_PHY_CTL_RST
);
259 SDR_WRITE(PESDR0_PHY_CTL_RST
, (reg
& 0xeffffffc) | 0x00000001);
260 reg
= SDR_READ(PESDR0_L0CLK
);
261 SDR_WRITE(PESDR0_L0CLK
, (reg
& 0xfffffff8) | 0x00000007);
262 SDR_WRITE(PESDR0_L0CDRCTL
, 0x00003111);
263 SDR_WRITE(PESDR0_L0DRV
, 0x00000104);
265 /* Bring SATA out of reset */
266 SDR_WRITE(SDR0_SRST1
, 0x00000000);
269 #endif /* !defined(CONFIG_ARCHES) */
271 int get_cpu_num(void)
273 int cpu
= NA_OR_UNKNOWN_CPU
;
275 #if defined(CONFIG_ARCHES)
278 cpu_num
= board_fpga_read(0x3);
280 /* sanity check; assume cpu numbering starts and increments from 0 */
281 if ((cpu_num
>= 0) && (cpu_num
< CONFIG_BD_NUM_CPUS
))
288 #if !defined(CONFIG_ARCHES)
291 struct board_bcsr
*bcsr_data
=
292 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
293 char *s
= getenv("serial#");
296 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
297 if (in_8(&bcsr_data
->board_status
) & BCSR_SELECT_PCIE
)
298 gd
->board_type
= BOARD_CANYONLANDS_PCIE
;
300 gd
->board_type
= BOARD_CANYONLANDS_SATA
;
302 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
303 gd
->board_type
= BOARD_GLACIER
;
306 switch (gd
->board_type
) {
307 case BOARD_CANYONLANDS_PCIE
:
312 case BOARD_CANYONLANDS_SATA
:
313 puts(", 1*PCIe/1*SATA");
317 printf(", Rev. %X", in_8(&bcsr_data
->cpld_rev
));
325 canyonlands_sata_init(gd
->board_type
);
330 #else /* defined(CONFIG_ARCHES) */
334 char *s
= getenv("serial#");
336 printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
337 printf(" Revision %02x.%02x ",
338 board_fpga_read(0x0), board_fpga_read(0x1));
340 gd
->board_type
= BOARD_ARCHES
;
342 /* Only CPU0 has access to CPLD registers */
343 if (get_cpu_num() == 0) {
344 u8 cfg_sw
= board_cpld_read(0x1);
345 printf("(FPGA=%02x, CPLD=%02x)\n",
346 board_fpga_read(0x2), board_cpld_read(0x0));
347 printf(" Configuration Switch %d%d%d%d\n",
348 ((cfg_sw
>> 3) & 0x01),
349 ((cfg_sw
>> 2) & 0x01),
350 ((cfg_sw
>> 1) & 0x01),
351 ((cfg_sw
>> 0) & 0x01));
353 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
357 printf(" Serial# %s\n", s
);
361 #endif /* !defined(CONFIG_ARCHES) */
363 #if defined(CONFIG_NAND_U_BOOT)
365 * NAND booting U-Boot version uses a fixed initialization, since the whole
366 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
369 phys_size_t
initdram(int board_type
)
371 return CONFIG_SYS_MBYTES_SDRAM
<< 20;
375 #if defined(CONFIG_PCI)
376 int board_pcie_first(void)
379 * Canyonlands with SATA enabled has only one PCIe slot
382 if (gd
->board_type
== BOARD_CANYONLANDS_SATA
)
387 #endif /* CONFIG_PCI */
389 int board_early_init_r (void)
392 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
393 * boot EBC mapping only supports a maximum of 16MBytes
394 * (4.ff00.0000 - 4.ffff.ffff).
395 * To solve this problem, the FLASH has to get remapped to another
396 * EBC address which accepts bigger regions:
398 * 0xfc00.0000 -> 4.cc00.0000
401 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
402 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
403 mtebc(PB3CR
, CONFIG_SYS_FLASH_BASE_PHYS_L
| 0xda000);
405 mtebc(PB0CR
, CONFIG_SYS_FLASH_BASE_PHYS_L
| 0xda000);
408 /* Remove TLB entry of boot EBC mapping */
409 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR
, 16 << 20);
411 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
412 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS
, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_SIZE
,
416 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
417 * 0xfc00.0000 is possible
421 * Clear potential errors resulting from auto-calibration.
422 * If not done, then we could get an interrupt later on when
423 * exceptions are enabled.
425 set_mcsr(get_mcsr());
430 #if !defined(CONFIG_ARCHES)
431 int misc_init_r(void)
438 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
439 * This is board specific, so let's do it here.
441 mfsdr(SDR0_ETH_CFG
, eth_cfg
);
442 /* disable SGMII mode */
443 eth_cfg
&= ~(SDR0_ETH_CFG_SGMII2_ENABLE
|
444 SDR0_ETH_CFG_SGMII1_ENABLE
|
445 SDR0_ETH_CFG_SGMII0_ENABLE
);
446 /* Set the for 2 RGMII mode */
447 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
448 eth_cfg
&= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL
;
450 eth_cfg
|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL
;
452 eth_cfg
&= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL
;
453 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
456 * The AHB Bridge core is held in reset after power-on or reset
459 mfsdr(SDR0_SRST1
, sdr0_srst1
);
460 sdr0_srst1
&= ~SDR0_SRST1_AHB
;
461 mtsdr(SDR0_SRST1
, sdr0_srst1
);
465 * Disable square wave output: Batterie will be drained
466 * quickly, when this output is not disabled
468 val
= i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR
, 0xa);
470 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR
, 0xa, val
);
475 #else /* defined(CONFIG_ARCHES) */
477 int misc_init_r(void)
484 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
485 * This is board specific, so let's do it here.
488 /* enable SGMII mode */
489 eth_cfg
|= (SDR0_ETH_CFG_SGMII0_ENABLE
|
490 SDR0_ETH_CFG_SGMII1_ENABLE
|
491 SDR0_ETH_CFG_SGMII2_ENABLE
);
493 /* Set EMAC for MDIO */
494 eth_cfg
|= SDR0_ETH_CFG_MDIO_SEL_EMAC0
;
496 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
497 eth_cfg
|= (SDR0_ETH_CFG_TAHOE0_BYPASS
| SDR0_ETH_CFG_TAHOE1_BYPASS
);
499 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
501 /* reset all SGMII interfaces */
502 mfsdr(SDR0_SRST1
, reg
);
503 reg
|= (SDR0_SRST1_SGMII0
| SDR0_SRST1_SGMII1
| SDR0_SRST1_SGMII2
);
504 mtsdr(SDR0_SRST1
, reg
);
505 mtsdr(SDR0_ETH_STS
, 0xFFFFFFFF);
506 mtsdr(SDR0_SRST1
, 0x00000000);
509 mfsdr(SDR0_ETH_PLL
, eth_pll
);
510 } while (!(eth_pll
& SDR0_ETH_PLL_PLLLOCK
));
514 #endif /* !defined(CONFIG_ARCHES) */
516 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
517 extern void __ft_board_setup(void *blob
, bd_t
*bd
);
519 void ft_board_setup(void *blob
, bd_t
*bd
)
521 __ft_board_setup(blob
, bd
);
523 if (gd
->board_type
== BOARD_CANYONLANDS_SATA
) {
525 * When SATA is selected we need to disable the first PCIe
526 * node in the device tree, so that Linux doesn't initialize
529 fdt_find_and_setprop(blob
, "/plb/pciex@d00000000", "status",
530 "disabled", sizeof("disabled"), 1);
533 if (gd
->board_type
== BOARD_CANYONLANDS_PCIE
) {
535 * When PCIe is selected we need to disable the SATA
536 * node in the device tree, so that Linux doesn't initialize
539 fdt_find_and_setprop(blob
, "/plb/sata@bffd1000", "status",
540 "disabled", sizeof("disabled"), 1);
543 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */