[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/errno.h>

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

	struct board_bcsr {
		u8	board_id;
		u8	cpld_rev;
		u8	led_user;
		u8	board_status;
		u8	reset_ctrl;
		u8	flash_ctrl;
		u8	eth_ctrl;
		u8	usb_ctrl;
		u8	irq_ctrl;
};

#define BOARD_CANYONLANDS_PCIE	1
#define BOARD_CANYONLANDS_SATA	2
#define BOARD_GLACIER		3
#define BOARD_ARCHES		4

/*
 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
#if defined(CONFIG_ARCHES)
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
}
#else
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#endif

#if defined(CONFIG_ARCHES)
/*
 * FPGA read/write helper macros
 */
static inline int board_fpga_read(int offset)
{
	int data;

	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));

	return data;
}

static inline void board_fpga_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
}

/*
 * CPLD read/write helper macros
 */
static inline int board_cpld_read(int offset)
{
	int data;

	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));

	return data;
}

static inline void board_cpld_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
#else
static int pvr_460ex(void)
{
	u32 pvr = get_pvr();

	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
	    (pvr == PVR_460EX_RB))
		return 1;

	return 0;
}
#endif	/* defined(CONFIG_ARCHES) */

int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
	u32 sdr0_cust0;
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;

#endif

	/*
	 * Setup the interrupt controller polarities, triggers, etc.
	 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
	mtdcr(UIC2ER, 0x00000000);	/* disable all */
	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC2SR, 0xffffffff);	/* clear all */

	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
	mtdcr(UIC3ER, 0x00000000);	/* disable all */
	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC3SR, 0xffffffff);	/* clear all */

#if !defined(CONFIG_ARCHES)
	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);
#endif

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

#if !defined(CONFIG_ARCHES)
	/* Enable ethernet and take out of reset */
	out_8(&bcsr_data->eth_ctrl, 0) ;

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8(&bcsr_data->flash_ctrl, 0) ;
	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	/* Setup PLB4-AHB bridge based on the system address map */
	mtdcr(AHB_TOP, 0x8000004B);
	mtdcr(AHB_BOT, 0x8000004B);

	if (pvr_460ex()) {
		/*
		 * Configure USB-STP pins as alternate and not GPIO
		 * It seems to be neccessary to configure the STP pins as GPIO
		 * input at powerup (perhaps while USB reset is asserted). So
		 * we configure those pins to their "real" function now.
		 */
		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	}
#endif

	return 0;
}

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Enable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	return 0;
}

int usb_board_stop(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Disable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	return 0;
}

int usb_board_init_fail(void)
{
	return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */

#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
	u32 reg;

	if (board_type == BOARD_CANYONLANDS_SATA) {
		/* Put SATA in reset */
		SDR_WRITE(SDR0_SRST1, 0x00020001);

		/* Set the phy for SATA, not PCI-E port 0 */
		reg = SDR_READ(PESDR0_PHY_CTL_RST);
		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
		reg = SDR_READ(PESDR0_L0CLK);
		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
		SDR_WRITE(PESDR0_L0DRV, 0x00000104);

		/* Bring SATA out of reset */
		SDR_WRITE(SDR0_SRST1, 0x00000000);
	}
}
#endif	/* !defined(CONFIG_ARCHES) */

int get_cpu_num(void)
{
	int cpu = NA_OR_UNKNOWN_CPU;

#if defined(CONFIG_ARCHES)
	int cpu_num;

	cpu_num = board_fpga_read(0x3);

	/* sanity check; assume cpu numbering starts and increments from 0 */
	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
		cpu = cpu_num;
#endif

	return cpu;
}

#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	char *s = getenv("serial#");

	if (pvr_460ex()) {
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
			gd->board_type = BOARD_CANYONLANDS_PCIE;
		else
			gd->board_type = BOARD_CANYONLANDS_SATA;
	} else {
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
		gd->board_type = BOARD_GLACIER;
	}

	switch (gd->board_type) {
	case BOARD_CANYONLANDS_PCIE:
	case BOARD_GLACIER:
		puts(", 2*PCIe");
		break;

	case BOARD_CANYONLANDS_SATA:
		puts(", 1*PCIe/1*SATA");
		break;
	}

	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	canyonlands_sata_init(gd->board_type);

	return (0);
}

#else	/* defined(CONFIG_ARCHES) */

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	printf("       Revision %02x.%02x ",
				board_fpga_read(0x0), board_fpga_read(0x1));

	gd->board_type = BOARD_ARCHES;

	/* Only CPU0 has access to CPLD registers */
	if (get_cpu_num() == 0) {
		u8 cfg_sw = board_cpld_read(0x1);
		printf("(FPGA=%02x, CPLD=%02x)\n",
				board_fpga_read(0x2), board_cpld_read(0x0));
		printf("       Configuration Switch %d%d%d%d\n",
				((cfg_sw >> 3) & 0x01),
				((cfg_sw >> 2) & 0x01),
				((cfg_sw >> 1) & 0x01),
				((cfg_sw >> 0) & 0x01));
	} else
		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));


	if (s != NULL)
		printf("       Serial# %s\n", s);

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_NAND_U_BOOT)
/*
 * NAND booting U-Boot version uses a fixed initialization, since the whole
 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 * code.
 */
phys_size_t initdram(int board_type)
{
	return CONFIG_SYS_MBYTES_SDRAM << 20;
}
#endif

#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
	/*
	 * Canyonlands with SATA enabled has only one PCIe slot
	 * (2nd one).
	 */
	if (gd->board_type == BOARD_CANYONLANDS_SATA)
		return 1;

	return 0;
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	/*
	 * Clear potential errors resulting from auto-calibration.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return 0;
}

#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;
	u8 val;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	if (pvr_460ex())
		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	else
		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	/*
	 * RTC/M41T62:
	 * Disable square wave output: Batterie will be drained
	 * quickly, when this output is not disabled
	 */
	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
	val &= ~0x40;
	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);

	return 0;
}

#else	/* defined(CONFIG_ARCHES) */

int misc_init_r(void)
{
	u32 eth_cfg = 0;
	u32 eth_pll;
	u32 reg;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */

	/* enable SGMII mode */
	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
			SDR0_ETH_CFG_SGMII1_ENABLE |
			SDR0_ETH_CFG_SGMII2_ENABLE);

	/* Set EMAC for MDIO */
	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;

	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);

	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/* reset all SGMII interfaces */
	mfsdr(SDR0_SRST1,   reg);
	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
	mtsdr(SDR0_SRST1, reg);
	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	mtsdr(SDR0_SRST1,   0x00000000);

	do {
		mfsdr(SDR0_ETH_PLL, eth_pll);
	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
extern void __ft_board_setup(void *blob, bd_t *bd);

void ft_board_setup(void *blob, bd_t *bd)
{
	__ft_board_setup(blob, bd);

	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
		/*
		 * When SATA is selected we need to disable the first PCIe
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
		/*
		 * When PCIe is selected we need to disable the SATA
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
				     "disabled", sizeof("disabled"), 1);
	}
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
b36df561	22	#include <asm/ppc440.h>
8e1a3fe5 SR	23	#include <libfdt.h>
8e1a3fe5 SR	24	#include <fdt_support.h>
212ed906	25	#include <i2c.h>
8e1a3fe5 SR	26	#include <asm/processor.h>
	27	#include <asm/io.h>
	28	#include <asm/mmu.h>
	29	#include <asm/4xx_pcie.h>
09887762	30	#include <asm/ppc4xx-gpio.h>
06dfaeef	31	#include <asm/errno.h>
8e1a3fe5	32
6d0f6bcf	33	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
8e1a3fe5 SR	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
17a68444 RS	37	struct board_bcsr {
	38	u8 board_id;
	39	u8 cpld_rev;
	40	u8 led_user;
	41	u8 board_status;
	42	u8 reset_ctrl;
	43	u8 flash_ctrl;
	44	u8 eth_ctrl;
	45	u8 usb_ctrl;
	46	u8 irq_ctrl;
	47	};
cc8e839a SR	48
	49	#define BOARD_CANYONLANDS_PCIE 1
	50	#define BOARD_CANYONLANDS_SATA 2
	51	#define BOARD_GLACIER 3
f09f09d3 AG	52	#define BOARD_ARCHES 4
f09f09d3 AG	53
f3ed3c9b	54	/*
a47a12be	55	* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
f3ed3c9b SR	56	* board specific values.
	57	*/
	58	#if defined(CONFIG_ARCHES)
	59	u32 ddr_wrdtr(u32 default_val) {
	60	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_0_DEG \| 0x823);
	61	}
	62	#else
	63	u32 ddr_wrdtr(u32 default_val) {
	64	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
	65	}
	66
	67	u32 ddr_clktr(u32 default_val) {
	68	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
	69	}
	70	#endif
	71
f09f09d3 AG	72	#if defined(CONFIG_ARCHES)
	73	/*
	74	* FPGA read/write helper macros
	75	*/
	76	static inline int board_fpga_read(int offset)
	77	{
	78	int data;
	79
	80	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
	81
	82	return data;
	83	}
	84
	85	static inline void board_fpga_write(int offset, int data)
	86	{
	87	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
	88	}
	89
	90	/*
	91	* CPLD read/write helper macros
	92	*/
	93	static inline int board_cpld_read(int offset)
	94	{
	95	int data;
	96
	97	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	98	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
	99
	100	return data;
	101	}
	102
	103	static inline void board_cpld_write(int offset, int data)
	104	{
	105	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	106	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
	107	}
c3fa4f0c SR	108	#else
	109	static int pvr_460ex(void)
	110	{
	111	u32 pvr = get_pvr();
	112
	113	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA) \|\|
	114	(pvr == PVR_460EX_RB))
	115	return 1;
	116
	117	return 0;
	118	}
f09f09d3	119	#endif /* defined(CONFIG_ARCHES) */
cc8e839a	120
8e1a3fe5 SR	121	int board_early_init_f(void)
8e1a3fe5 SR	122	{
f09f09d3	123	#if !defined(CONFIG_ARCHES)
8e1a3fe5	124	u32 sdr0_cust0;
17a68444 RS	125	struct board_bcsr *bcsr_data =
	126	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	127
f09f09d3	128	#endif
8e1a3fe5	129
1c2926ab	130	/*
8e1a3fe5	131	* Setup the interrupt controller polarities, triggers, etc.
1c2926ab	132	*/
952e7760 SR	133	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	134	mtdcr(UIC0ER, 0x00000000); /* disable all */
	135	mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
	136	mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
	137	mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
	138	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
	139	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	140
	141	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	142	mtdcr(UIC1ER, 0x00000000); /* disable all */
	143	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	144	mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
	145	mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
	146	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
	147	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	148
	149	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	150	mtdcr(UIC2ER, 0x00000000); /* disable all */
	151	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	152	mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
	153	mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
	154	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
	155	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	156
	157	mtdcr(UIC3SR, 0xffffffff); /* clear all */
	158	mtdcr(UIC3ER, 0x00000000); /* disable all */
	159	mtdcr(UIC3CR, 0x00000000); /* all non-critical */
	160	mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
	161	mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
	162	mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
	163	mtdcr(UIC3SR, 0xffffffff); /* clear all */
8e1a3fe5	164
f09f09d3	165	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	166	/* SDR Setting - enable NDFC */
	167	mfsdr(SDR0_CUST0, sdr0_cust0);
	168	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
	169	SDR0_CUST0_NDFC_ENABLE \|
	170	SDR0_CUST0_NDFC_BW_8_BIT \|
	171	SDR0_CUST0_NDFC_ARE_MASK \|
	172	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
6d0f6bcf	173	(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
8e1a3fe5	174	mtsdr(SDR0_CUST0, sdr0_cust0);
f09f09d3	175	#endif
8e1a3fe5 SR	176
	177	/*
	178	* Configure PFC (Pin Function Control) registers
	179	* UART0: 4 pins
	180	*/
	181	mtsdr(SDR0_PFC1, 0x00040000);
	182
	183	/* Enable PCI host functionality in SDR0_PCI0 */
	184	mtsdr(SDR0_PCI0, 0xe0000000);
	185
f09f09d3	186	#if !defined(CONFIG_ARCHES)
8e1a3fe5	187	/* Enable ethernet and take out of reset */
17a68444	188	out_8(&bcsr_data->eth_ctrl, 0) ;
8e1a3fe5 SR	189
8e1a3fe5 SR	190	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
17a68444	191	out_8(&bcsr_data->flash_ctrl, 0) ;
8e1a3fe5 SR	192	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
8e1a3fe5 SR	193
41712b4e SR	194	/* Setup PLB4-AHB bridge based on the system address map */
	195	mtdcr(AHB_TOP, 0x8000004B);
	196	mtdcr(AHB_BOT, 0x8000004B);
	197
c3fa4f0c	198	if (pvr_460ex()) {
4c9e8557 SR	199	/*
	200	* Configure USB-STP pins as alternate and not GPIO
	201	* It seems to be neccessary to configure the STP pins as GPIO
	202	* input at powerup (perhaps while USB reset is asserted). So
	203	* we configure those pins to their "real" function now.
	204	*/
	205	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	206	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	207	}
f09f09d3	208	#endif
41712b4e	209
8e1a3fe5 SR	210	return 0;
	211	}
	212
17a68444 RS	213	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
	214	int usb_board_init(void)
	215	{
	216	struct board_bcsr *bcsr_data =
	217	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	218	u8 val;
	219
	220	/* Enable USB host & USB-OTG */
	221	val = in_8(&bcsr_data->usb_ctrl);
	222	val &= ~(BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	223	out_8(&bcsr_data->usb_ctrl, val);
	224
	225	return 0;
	226	}
	227
	228	int usb_board_stop(void)
	229	{
	230	struct board_bcsr *bcsr_data =
	231	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	232	u8 val;
	233
	234	/* Disable USB host & USB-OTG */
	235	val = in_8(&bcsr_data->usb_ctrl);
	236	val \|= (BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	237	out_8(&bcsr_data->usb_ctrl, val);
	238
	239	return 0;
	240	}
	241
	242	int usb_board_init_fail(void)
	243	{
	244	return usb_board_stop();
	245	}
	246	#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
	247
f09f09d3	248	#if !defined(CONFIG_ARCHES)
1c2926ab SR	249	static void canyonlands_sata_init(int board_type)
	250	{
	251	u32 reg;
	252
	253	if (board_type == BOARD_CANYONLANDS_SATA) {
	254	/* Put SATA in reset */
	255	SDR_WRITE(SDR0_SRST1, 0x00020001);
	256
	257	/* Set the phy for SATA, not PCI-E port 0 */
	258	reg = SDR_READ(PESDR0_PHY_CTL_RST);
	259	SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) \| 0x00000001);
	260	reg = SDR_READ(PESDR0_L0CLK);
	261	SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) \| 0x00000007);
	262	SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
	263	SDR_WRITE(PESDR0_L0DRV, 0x00000104);
	264
	265	/* Bring SATA out of reset */
	266	SDR_WRITE(SDR0_SRST1, 0x00000000);
	267	}
	268	}
f09f09d3 AG	269	#endif /* !defined(CONFIG_ARCHES) */
	270
	271	int get_cpu_num(void)
	272	{
	273	int cpu = NA_OR_UNKNOWN_CPU;
	274
	275	#if defined(CONFIG_ARCHES)
	276	int cpu_num;
	277
	278	cpu_num = board_fpga_read(0x3);
	279
	280	/* sanity check; assume cpu numbering starts and increments from 0 */
	281	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
	282	cpu = cpu_num;
	283	#endif
	284
	285	return cpu;
	286	}
1c2926ab	287
f09f09d3	288	#if !defined(CONFIG_ARCHES)
1c2926ab	289	int checkboard(void)
8e1a3fe5	290	{
17a68444 RS	291	struct board_bcsr *bcsr_data =
17a68444 RS	292	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
8e1a3fe5	293	char *s = getenv("serial#");
8e1a3fe5	294
c3fa4f0c	295	if (pvr_460ex()) {
8e1a3fe5	296	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
17a68444	297	if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
cc8e839a SR	298	gd->board_type = BOARD_CANYONLANDS_PCIE;
	299	else
	300	gd->board_type = BOARD_CANYONLANDS_SATA;
c3fa4f0c SR	301	} else {
	302	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	303	gd->board_type = BOARD_GLACIER;
cc8e839a SR	304	}
	305
	306	switch (gd->board_type) {
	307	case BOARD_CANYONLANDS_PCIE:
	308	case BOARD_GLACIER:
	309	puts(", 2*PCIe");
	310	break;
	311
	312	case BOARD_CANYONLANDS_SATA:
	313	puts(", 1PCIe/1SATA");
	314	break;
	315	}
	316
17a68444	317	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
8e1a3fe5 SR	318
	319	if (s != NULL) {
	320	puts(", serial# ");
	321	puts(s);
	322	}
	323	putc('\n');
	324
1c2926ab SR	325	canyonlands_sata_init(gd->board_type);
1c2926ab SR	326
8e1a3fe5 SR	327	return (0);
	328	}
	329
f09f09d3 AG	330	#else /* defined(CONFIG_ARCHES) */
	331
	332	int checkboard(void)
	333	{
	334	char *s = getenv("serial#");
	335
	336	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	337	printf(" Revision %02x.%02x ",
	338	board_fpga_read(0x0), board_fpga_read(0x1));
	339
	340	gd->board_type = BOARD_ARCHES;
	341
	342	/* Only CPU0 has access to CPLD registers */
	343	if (get_cpu_num() == 0) {
	344	u8 cfg_sw = board_cpld_read(0x1);
	345	printf("(FPGA=%02x, CPLD=%02x)\n",
	346	board_fpga_read(0x2), board_cpld_read(0x0));
	347	printf(" Configuration Switch %d%d%d%d\n",
	348	((cfg_sw >> 3) & 0x01),
	349	((cfg_sw >> 2) & 0x01),
	350	((cfg_sw >> 1) & 0x01),
	351	((cfg_sw >> 0) & 0x01));
	352	} else
	353	printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
	354
	355
	356	if (s != NULL)
	357	printf(" Serial# %s\n", s);
	358
	359	return 0;
	360	}
	361	#endif /* !defined(CONFIG_ARCHES) */
	362
71665ebf SR	363	#if defined(CONFIG_NAND_U_BOOT)
	364	/*
	365	* NAND booting U-Boot version uses a fixed initialization, since the whole
	366	* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
	367	* code.
	368	*/
9973e3c6	369	phys_size_t initdram(int board_type)
71665ebf	370	{
6d0f6bcf	371	return CONFIG_SYS_MBYTES_SDRAM << 20;
71665ebf SR	372	}
	373	#endif
	374
8e1a3fe5	375	#if defined(CONFIG_PCI)
b0b86746	376	int board_pcie_first(void)
8e1a3fe5	377	{
cc8e839a SR	378	/*
	379	* Canyonlands with SATA enabled has only one PCIe slot
	380	* (2nd one).
	381	*/
	382	if (gd->board_type == BOARD_CANYONLANDS_SATA)
b0b86746	383	return 1;
8e1a3fe5	384
b0b86746	385	return 0;
8e1a3fe5 SR	386	}
	387	#endif /* CONFIG_PCI */
	388
	389	int board_early_init_r (void)
	390	{
	391	/*
	392	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	393	* boot EBC mapping only supports a maximum of 16MBytes
	394	* (4.ff00.0000 - 4.ffff.ffff).
	395	* To solve this problem, the FLASH has to get remapped to another
	396	* EBC address which accepts bigger regions:
	397	*
	398	* 0xfc00.0000 -> 4.cc00.0000
8e1a3fe5 SR	399	*/
	400
	401	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
71665ebf	402	#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
d1c3b275	403	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
71665ebf	404	#else
d1c3b275	405	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
71665ebf	406	#endif
8e1a3fe5 SR	407
8e1a3fe5 SR	408	/* Remove TLB entry of boot EBC mapping */
6d0f6bcf	409	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
8e1a3fe5 SR	410
8e1a3fe5 SR	411	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
6d0f6bcf	412	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
8e1a3fe5 SR	413	TLB_WORD2_I_ENABLE);
	414
	415	/*
	416	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	417	* 0xfc00.0000 is possible
	418	*/
	419
71665ebf SR	420	/*
	421	* Clear potential errors resulting from auto-calibration.
	422	* If not done, then we could get an interrupt later on when
	423	* exceptions are enabled.
	424	*/
	425	set_mcsr(get_mcsr());
	426
8e1a3fe5 SR	427	return 0;
	428	}
	429
f09f09d3	430	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	431	int misc_init_r(void)
	432	{
	433	u32 sdr0_srst1 = 0;
	434	u32 eth_cfg;
212ed906	435	u8 val;
8e1a3fe5 SR	436
	437	/*
	438	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	439	* This is board specific, so let's do it here.
	440	*/
	441	mfsdr(SDR0_ETH_CFG, eth_cfg);
	442	/* disable SGMII mode */
	443	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
	444	SDR0_ETH_CFG_SGMII1_ENABLE \|
	445	SDR0_ETH_CFG_SGMII0_ENABLE);
	446	/* Set the for 2 RGMII mode */
	447	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	448	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
c3fa4f0c	449	if (pvr_460ex())
4c9e8557 SR	450	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	451	else
	452	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
8e1a3fe5 SR	453	mtsdr(SDR0_ETH_CFG, eth_cfg);
	454
	455	/*
	456	* The AHB Bridge core is held in reset after power-on or reset
	457	* so enable it now
	458	*/
	459	mfsdr(SDR0_SRST1, sdr0_srst1);
	460	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	461	mtsdr(SDR0_SRST1, sdr0_srst1);
	462
212ed906 SR	463	/*
	464	* RTC/M41T62:
	465	* Disable square wave output: Batterie will be drained
	466	* quickly, when this output is not disabled
	467	*/
6d0f6bcf	468	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
212ed906	469	val &= ~0x40;
6d0f6bcf	470	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
212ed906	471
8e1a3fe5 SR	472	return 0;
	473	}
	474
f09f09d3 AG	475	#else /* defined(CONFIG_ARCHES) */
	476
	477	int misc_init_r(void)
	478	{
	479	u32 eth_cfg = 0;
	480	u32 eth_pll;
	481	u32 reg;
	482
	483	/*
	484	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	485	* This is board specific, so let's do it here.
	486	*/
	487
	488	/* enable SGMII mode */
	489	eth_cfg \|= (SDR0_ETH_CFG_SGMII0_ENABLE \|
	490	SDR0_ETH_CFG_SGMII1_ENABLE \|
	491	SDR0_ETH_CFG_SGMII2_ENABLE);
	492
	493	/* Set EMAC for MDIO */
	494	eth_cfg \|= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
	495
	496	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	497	eth_cfg \|= (SDR0_ETH_CFG_TAHOE0_BYPASS \| SDR0_ETH_CFG_TAHOE1_BYPASS);
	498
	499	mtsdr(SDR0_ETH_CFG, eth_cfg);
	500
	501	/* reset all SGMII interfaces */
	502	mfsdr(SDR0_SRST1, reg);
	503	reg \|= (SDR0_SRST1_SGMII0 \| SDR0_SRST1_SGMII1 \| SDR0_SRST1_SGMII2);
	504	mtsdr(SDR0_SRST1, reg);
	505	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	506	mtsdr(SDR0_SRST1, 0x00000000);
	507
	508	do {
	509	mfsdr(SDR0_ETH_PLL, eth_pll);
	510	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
	511
	512	return 0;
	513	}
	514	#endif /* !defined(CONFIG_ARCHES) */
	515
8e1a3fe5	516	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
26d37f00 FR	517	extern void __ft_board_setup(void blob, bd_t bd);
26d37f00 FR	518
8e1a3fe5 SR	519	void ft_board_setup(void blob, bd_t bd)
8e1a3fe5 SR	520	{
26d37f00	521	__ft_board_setup(blob, bd);
8e1a3fe5	522
16bedc66 SR	523	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
	524	/*
	525	* When SATA is selected we need to disable the first PCIe
	526	* node in the device tree, so that Linux doesn't initialize
	527	* it.
	528	*/
8fd4166c SR	529	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
8fd4166c SR	530	"disabled", sizeof("disabled"), 1);
16bedc66 SR	531	}
	532
	533	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
	534	/*
	535	* When PCIe is selected we need to disable the SATA
	536	* node in the device tree, so that Linux doesn't initialize
	537	* it.
	538	*/
8fd4166c SR	539	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
8fd4166c SR	540	"disabled", sizeof("disabled"), 1);
16bedc66	541	}
8e1a3fe5 SR	542	}
8e1a3fe5 SR	543	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */