2 * Copyright (C) 2012 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
16 #include <atmel_hlcdc.h>
17 #ifdef CONFIG_LCD_INFO
22 DECLARE_GLOBAL_DATA_PTR
;
24 /* ------------------------------------------------------------------------- */
26 * Miscelaneous platform dependent initialisations
28 #ifdef CONFIG_CMD_NAND
29 static void at91sam9x5ek_nand_hw_init(void)
31 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
32 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
36 csa
= readl(&matrix
->ebicsa
);
37 csa
|= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA
;
38 /* NAND flash on D16 */
39 csa
|= AT91_MATRIX_NFD0_ON_D16
;
41 /* Configure IO drive */
42 csa
&= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
44 writel(csa
, &matrix
->ebicsa
);
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
51 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
53 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
55 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
56 AT91_SMC_MODE_EXNW_DISABLE
|
57 #ifdef CONFIG_SYS_NAND_DBW_16
58 AT91_SMC_MODE_DBW_16
|
59 #else /* CONFIG_SYS_NAND_DBW_8 */
62 AT91_SMC_MODE_TDF_CYCLE(1),
65 at91_periph_clk_enable(ATMEL_ID_PIOCD
);
67 /* Configure RDY/BSY */
68 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
69 /* Enable NandFlash */
70 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
72 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 0, 1); /* NAND OE */
73 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 1, 1); /* NAND WE */
74 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 2, 1); /* NAND ALE */
75 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 3, 1); /* NAND CLE */
76 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 6, 1);
77 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 7, 1);
78 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 8, 1);
79 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 9, 1);
80 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 10, 1);
81 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 11, 1);
82 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 12, 1);
83 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 13, 1);
88 vidinfo_t panel_info
= {
92 .vl_sync
= LCDC_LCDCFG5_HSPOL
| LCDC_LCDCFG5_VSPOL
,
98 .vl_right_margin
= 64,
100 .vl_upper_margin
= 22,
101 .vl_lower_margin
= 21,
102 .mmio
= ATMEL_BASE_LCDC
,
105 void lcd_enable(void)
108 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 29, 1); /* power up */
111 void lcd_disable(void)
114 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 29, 0); /* power down */
117 static void at91sam9x5ek_lcd_hw_init(void)
120 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 26, 0); /* LCDPWM */
121 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 27, 0); /* LCDVSYNC */
122 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 28, 0); /* LCDHSYNC */
123 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 24, 0); /* LCDDISP */
124 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 29, 0); /* LCDDEN */
125 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 30, 0); /* LCDPCK */
127 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 0, 0); /* LCDD0 */
128 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 1, 0); /* LCDD1 */
129 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 2, 0); /* LCDD2 */
130 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 3, 0); /* LCDD3 */
131 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 4, 0); /* LCDD4 */
132 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 5, 0); /* LCDD5 */
133 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 6, 0); /* LCDD6 */
134 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 7, 0); /* LCDD7 */
135 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 8, 0); /* LCDD8 */
136 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 9, 0); /* LCDD9 */
137 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 10, 0); /* LCDD10 */
138 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 11, 0); /* LCDD11 */
139 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 12, 0); /* LCDD12 */
140 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 13, 0); /* LCDD13 */
141 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 14, 0); /* LCDD14 */
142 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 15, 0); /* LCDD15 */
143 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 16, 0); /* LCDD16 */
144 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 17, 0); /* LCDD17 */
145 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 18, 0); /* LCDD18 */
146 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 19, 0); /* LCDD19 */
147 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 20, 0); /* LCDD20 */
148 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 21, 0); /* LCDD21 */
149 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 22, 0); /* LCDD22 */
150 at91_pio3_set_a_periph(AT91_PIO_PORTC
, 23, 0); /* LCDD23 */
152 at91_periph_clk_enable(ATMEL_ID_LCDC
);
156 #ifdef CONFIG_LCD_INFO
157 void lcd_show_board_info(void)
159 ulong dram_size
, nand_size
;
164 lcd_printf("%s\n", U_BOOT_VERSION
);
165 lcd_printf("(C) 2012 ATMEL Corp\n");
166 lcd_printf("at91support@atmel.com\n");
167 lcd_printf("%s CPU at %s MHz\n",
169 strmhz(temp
, get_cpu_clk_rate()));
172 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
173 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
175 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
176 nand_size
+= nand_info
[i
]->size
;
177 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
182 #endif /* CONFIG_LCD_INFO */
183 #endif /* CONFIG_LCD */
185 int board_early_init_f(void)
187 at91_seriald_hw_init();
193 /* arch number of AT91SAM9X5EK-Board */
194 gd
->bd
->bi_arch_number
= MACH_TYPE_AT91SAM9X5EK
;
196 /* adress of boot parameters */
197 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
199 #ifdef CONFIG_CMD_NAND
200 at91sam9x5ek_nand_hw_init();
203 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
207 at91sam9x5ek_lcd_hw_init();
214 gd
->ram_size
= get_ram_size((void *) CONFIG_SYS_SDRAM_BASE
,
215 CONFIG_SYS_SDRAM_SIZE
);
219 #if defined(CONFIG_SPL_BUILD)
223 void at91_spl_board_init(void)
225 #ifdef CONFIG_SYS_USE_MMC
227 #elif CONFIG_SYS_USE_NANDFLASH
228 at91sam9x5ek_nand_hw_init();
232 #include <asm/arch/atmel_mpddrc.h>
233 static void ddr2_conf(struct atmel_mpddrc_config
*ddr2
)
235 ddr2
->md
= (ATMEL_MPDDRC_MD_DBW_16_BITS
| ATMEL_MPDDRC_MD_DDR2_SDRAM
);
237 ddr2
->cr
= (ATMEL_MPDDRC_CR_NC_COL_10
|
238 ATMEL_MPDDRC_CR_NR_ROW_13
|
239 ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
240 ATMEL_MPDDRC_CR_NB_8BANKS
|
241 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
);
245 ddr2
->tpr0
= (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
246 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
247 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
248 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
249 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
250 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
251 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
252 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
254 ddr2
->tpr1
= (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
255 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
256 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
257 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
259 ddr2
->tpr2
= (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET
|
260 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
261 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
262 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
263 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
268 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
269 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
270 struct atmel_mpddrc_config ddr2
;
275 /* enable DDR2 clock */
276 writel(AT91_PMC_DDR
, &pmc
->scer
);
278 /* Chip select 1 is for DDR2/SDRAM */
279 csa
= readl(&matrix
->ebicsa
);
280 csa
|= AT91_MATRIX_EBI_CS1A_SDRAMC
;
281 csa
&= ~AT91_MATRIX_EBI_DBPU_OFF
;
282 csa
|= AT91_MATRIX_EBI_DBPD_OFF
;
283 csa
|= AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
284 writel(csa
, &matrix
->ebicsa
);
286 /* DDRAM2 Controller initialize */
287 ddr2_init(ATMEL_BASE_DDRSDRC
, ATMEL_BASE_CS1
, &ddr2
);